JPS62195924A - Counter circuit - Google Patents

Abstract

PURPOSE:To obtain an up/down counter output signal with less number of components by using a multiplexer circuit outputting alternatively one of up/ down count signals to a binary counter circuit having a noninverting and an inverting output according to the up/down count control signal. CONSTITUTION:The first stage circuit consists of a counter circuit section FF1 and a multiplexer circuit MPX1. The multiplexer circuit MPX1 consists of clocked inverter circuits N7, N8 receiving respectively a noninverting output signal Q and an inverting output signal Q from the counter circuit FF1 and an output inverter circuit N9 receiving a signal of the output terminals of the circuits N7, N8 connected in common. A counter output RQ1 is outputted from the output terminal of the circuit N9. The said circuit N7 is made operative by the high level of the up/down control signal DWN' and the circuit N8 is made operative by the high level of the inverted control signal DWN by an inverter circuit N10. The noninverting output signal Q of the 1st stage circuit is sent to the counter circuit FF2 of the next stage as a carry signal. The counter circuit is constituted by the cascade connection of the counter circuits FF2-FF4 similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter circuit, and relates to a technique that is effective for use in an up/down counter circuit.

[Conventional technology]

As an up/down counter circuit, one with an output switching method as shown in Figure 6 is available, for example, from ■Radio Gijutsusha.
This is known from Digital IC Practical Circuit Manual J Yokoi Yotsugube, published July 25, 1975, page 175.

This up/down counter is provided with a true value/complement switching circuit consisting of exclusive OR circuits EXI to EX3 at each output of a flip-flop circuit constituting the piery counter circuit.

[Problem that the invention seeks to solve]

The up/down counter circuit described above requires a relatively large number of circuit elements because the exclusive OR circuits EXI to EX3 are composed of a combination of multiple gate circuits, as is well known. becomes.

An object of the present invention is to provide a counter circuit with a reduced number of circuit elements.

The above and other objects and novel features of this invention are:
It will become clear from the description of the present invention w1@ and the attached drawings.

[Means for solving problems]

A brief summary of typical inventions disclosed in this application is as follows.

That is, the complementary output signals of each bit of the binary up/down counter circuit are selectively outputted according to the up/down switching system 'aJ(').

[For production]

According to the above-mentioned means, by utilizing the fact that the complementary output signals in the binary counter circuit are directly output as counting/down counting outputs, by simply adding a simple multiplexer circuit, A typical up/down counting operation can be performed.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of the present invention. Each circuit element in the figure is formed on a semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

In the figure, a specific circuit of a unit circuit for one bit is exemplarily shown as a representative.

The first stage circuit includes the counting circuit section FF, as shown by the dotted line in the figure.
It consists of a multiplexer circuit MPXI and a multiplexer circuit MPXI.

The counting circuit FFI is a flip-flop circuit with negative feedback. That is, the clocked inverter circuit N1 constitutes an input gate circuit that is activated by the input signal C, and supplies its output signal to one input of the NOR gate circuit G1. Between the output terminal of this NOR gate circuit Gl and the above one input terminal,
A feedback clocked inverter circuit N2 is provided which is activated by an input signal C inverted by an inverter circuit N6. Further, a reset signal R is supplied to the other input of the NOR gate circuit G1. This constitutes a master flip-flop circuit. A slave flip-flop circuit consisting of a clocked inverter circuit N3 as an input gate circuit similar to the master flip-flop circuit, a NOR gate circuit G2, and a feedback clocked inverter circuit N4 is provided. The output signal of the NOR gate circuit G1 as the output signal of the master flip-flop circuit is transmitted to the input terminal of the clocked inverter circuit N3. In addition, the input signal C is reversed to that of the master flip-flop circuit, and an inverted input signal C is supplied to the input clocked inverter circuit N3 constituting the slave flip-flop circuit. A non-inverted input signal C is supplied to the inverter circuit N4. The output signal of the NOR gate circuit G2 constituting the slave flip-flop circuit is converted into a non-inverted output signal Q, and an inverted output signal Q is also outputted by the inverter circuit N5 that receives it. This inverted output Q is fed back to the input of the clocked inverter circuit N1 for input to the master flip-flop circuit.

The multiplexer circuit MPXI receives signals from clocked inverter circuits N7 and N8 which receive the non-inverted output signal Q and inverted output signal Q, respectively, and the commonly connected output terminals of these clocked inverter circuits N7 and N8. It is composed of an output inverter circuit N9. Counting output RQ from the output terminal of this output impark circuit N9
I is output. The clocked inverter circuit N7 is activated by the high level of the up/down control signal DWN, and the clocked inverter circuit N8 is activated by the high level of the control signal DWN inverted by the inverter circuit NIO.

The non-inverting output signal Q of the first stage circuit is applied to the next stage counting circuit FF.
2 as a carry signal. Similarly, each of the counting circuits FF2 to FF4 is connected in series to form a binary counter circuit.

The operation of this embodiment circuit will be explained according to the timing diagram shown in FIG.

Before the start of the counting operation, the reset signal R is set to high level, and the master/slave flip-flop circuit of each bit is placed in a reset state. That is, in the first stage circuit FFI, the output signals of the NOR gate circuits G1 and G2 are set to a low level (logic "0"), and this also applies to the other counting circuits FF2 to FF4.

In this state, when the input signal C (not shown) is set to high level, the input inverter circuit N1 of the master flip-flop circuit is activated, so that the high level (logic "1") of the inverted output signal Q is inverted. And Noah gate circuit G
Tell 1. As a result, the output signal of the NOR gate circuit G1 changes from low level to high level. At this time, the feedback clocked inverter circuit N2 is rendered inactive by the low level of the inverted input signal C.

When the input signal C changes from high level to low level, the input impark circuit N of the master flip-flop circuit
1 is in the non-operating state, and the feedback clocked inverter circuit N
2 is activated. This causes the master flip-flop circuit to enter an information holding state. In addition, in response to the low level of the input signal C, the inverter circuit N6
Since the output signal of is set to high level, the input inverter circuit N3 of the slave flip-flop circuit is activated. As a result, the high level (logic "1") of the output signal of the master flip-flop circuit is inverted and transmitted to the NOR gate circuit G2.

As a result, the output signal of the NOR gate circuit G2 changes from low level to high level. Note that at this time, the feedback clocked inverter circuit N4 is rendered inactive by the low level of the non-inverted input signal C.

Thereby, a counting operation is performed in which the output signal of the first stage circuit FFI changes corresponding to one cycle of the input signal C.

Similarly, the output of the next stage circuit FF2 is changed every cycle of the carry (output Q) from the first stage circuit FFI. Thereafter, a binary counting operation is performed in a similar manner.

In the above counting operation, for example, if the control signal DWN is at a high level, the clocked inverter circuit N7 constituting the multiplexer circuit MPX1 is activated.
The non-inverted output signal Q is output as an output signal RQI. Similarly, the other multiplexers MPX2 to MPX3 output non-inverted output signals Q as counting outputs RQ1 to RQ4, respectively, so that up counting outputs are obtained as shown in the figure.

For example, when the control signal DWN is set to a low level at the timing when the output signal Q of the final stage circuit FF4 changes from high level to low level, in other words, after one rotation of this counter circuit, the multiplexer circuit MPXI
Since the clocked inverter circuit N8 is activated in place of N7, it outputs the inverted output Q of the counting circuit FFI. This also applies to the other multiplexer circuits MPX2 to MPX4.

As a result, each of the counting circuits FFI to FF4 outputs an inverted output Q, so that even though the counting circuits FF1 to FF4 perform the above-mentioned amplifier counting operation, the output signals RQI to RQ4 are as shown in the figure. As shown, it becomes a down count output signal.

In this embodiment, the counting circuit itself is simplified by adopting a clocked inverter circuit, and by using the multiplexer circuit described above, compared to the case where an output switching circuit using an exclusive OR circuit as in the past is used. Up/down counting output signals can be obtained as described above with a significantly smaller number of elements.

[Embodiment 2] FIG. 3 shows a circuit diagram of another embodiment of the present invention.

In the embodiment circuit of FIG. 1, for example, the switching of the count output from up to down is expressed in decimal notation as 14-
It changes like 15-15-14. This is 14-15
In order to avoid duplicate outputs at the switching portion, as shown in -14, the circuit of FIG. 3 is configured as follows.

The circuit configurations of the counting circuit and multiplexer circuit of this embodiment are the same as those shown in FIG. 1 above, and therefore their explanation will be omitted.

The count output RQI of the least significant bit is the first stage count circuit FFI.
The non-inverted output Q of is output as is.

Then, the output signal RQI' of the first stage multiplexer circuit MPXI is sent as a carry signal to the next stage circuit FF2. In addition, the first stage counting circuit FF1 and the next stage counting circuit F
F2 is supplied with its reset signal differently from other counting circuits. That is, the reset signal R° is supplied to the first stage circuit FFI. The next stage circuit FF2 is the master 79
The same reset signal R' as the first stage counting circuit FFI is supplied to the 717071 circuit, and a reset signal R different from the reset signal R' is supplied to the slave flip-flop circuit and the other counting circuits FF3 and FF4. Ru.

The operation of this embodiment circuit will now be described with reference to the timing diagram shown in FIG.

The up-counting operation performed by the high level of the control signal DWN is the same as that of the circuit of the embodiment shown in FIG. 1, so its explanation will be omitted.

After the 4-bit counting circuit counts up to 15 in decimal notation, when the control signal DWN is set to low level, a down-counting operation is started. At this time, the reset signal R
The slave flip-flop circuit of counting circuit FF2 and counting circuits FF3 to FF are set to high level once.
4 to the reset state.

Since the output signal RQI of the first stage circuit FFI counts the input signal C as it is, it is set to a low level at the start of down counting. At this time, the output signal RQI of the next stage circuit FF2 is outputted via the multiplexer circuit MPX2 to which the inverted output Q has been switched by the reset operation on the slave side. Further, the other counting circuits FF3 and FF4 are reset as described above, and the multiplexer circuits MPX3 and MPX4 are reset.
Since the inverted output Q is outputted through the inverted output Q, it is set to high level. As a result, the count output signals RQI to RQ4
The count value shown by is 14 in decimal notation.

Due to the low level of the control signal DWN, the inverted signal Q of the first stage counting circuit FFI is sent out as the carry signal RQI' of the next stage circuit FF2 via the multiplexer circuit MPXI. As a result, in one cycle of the next input signal C, when the signal RQ1° changes from a high level to a low level, the slave flip-flop circuit of the counting circuit FF2 has a master flip-flop circuit due to not being reset. The high-level output signal held in the slave flip-flop circuit is transmitted to the slave flip-flop circuit, and the output signal is inverted. That is, at this time, the inverted output Q output as the count output signal RQ2 changes from high level to low level.

At this time, the count output RQI of the first stage circuit FFI changes to high level in synchronization with the change in the low level of the input signal C, so the count value indicated by the count output signals RQI to RQ4 becomes 13 in decimal notation. Thereafter, the down counting operation will be performed in the same manner.

In this embodiment, in the case of a 4-pin counter circuit, the up/down counting operation is switched from 14 to 15-14 without duplication at the switching portion.

[Embodiment 3] FIG. 5 shows a block diagram of an embodiment of a sine wave generating circuit in which the counter circuit according to the present invention is utilized.

Although not particularly limited, this sine wave generating circuit is used as a billing signal generating circuit in a digital telephone exchange.

As the up/down counter circuit U/DCOUNT, the circuit shown in FIG. 3 (or FIG. 1) above is used. The count output signal of this counter circuit U/DCOtJNT operates as an address generation circuit of a read-only memory (hereinafter simply referred to as ROM). In order to generate the above-mentioned sine wave with a small storage capacity, only a quarter period of the digital signal corresponding to the waveform of the sine wave indicated by the vertical line in the figure is written in the ROM. . The output signal of the ROM is transmitted to the digital/analog conversion circuit D/A, where it is converted into an analog signal.

By the up operation of the counter circuit U/DCOUNT, the information stored in the ROM is then read out, and 174 cycles of digital signals are sent out. When the digital signal up to the above-mentioned 1/4 period is sent out, the operation is switched to down counting operation.

As a result, the digital signal in the ROM is read out in reverse, so that a positive half wave can be obtained. A negative half wave is formed by repeating similar operations and switching the output polarity of the digital/analog conversion circuit. As a result, one period of a sine wave can be generated using as few digital signals as 1/4 period as described above.

The effects obtained from the above embodiments are as follows. In other words, (1) By using a multiplexer circuit that selectively outputs one of the binary counting circuits having non-inverted and inverted outputs according to the up/down counting control signal, it is possible to perform The effect is that up/down count output signals can be obtained with a significantly smaller number of elements than in the case of using an output switching circuit using a circuit.

(By using a master/slave flip-flow 71 circuit using a clocked inverter circuit as a 2-bin counting circuit, in combination with the above (1), the up/down counting output signal is This has the effect of being able to obtain the following.

(3) The output signal of the first-stage 81 number circuit is outputted as a counting output as it is, and the output signal passed through the multiplexer circuit provided in the first-stage counting circuit is sent as a carry to the next-stage counting circuit, and the output signal of the next-stage counting circuit is By providing a function to reset the slave-side flip-flop circuit and the subsequent counting circuit, it is possible to obtain a counting output that can be switched from up to down without duplication.

(4) By using the above amplifier/down counter circuit, it is possible to obtain a signal with a symmetrical waveform every 1/4 period using a ROM with a small storage capacity.

(5) As is clear from the comparison between FIG. 1 and FIG. 3, it is possible to easily change the count configuration by changing the wiring to a circuit consisting of substantially the same circuit. Therefore, it is suitable as a so-called cell circuit in an integrated circuit.

In the above description, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above examples (and various changes can be made without departing from the gist thereof). Needless to say, the multiplexer circuit may be constructed using transmission MOSFETs or logic gate circuits. Moreover, the specific circuit of the counting circuit can take various embodiments.

This invention can be widely used as an up/down counter circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, in a binary counting circuit with non-inverting and inverting outputs,
By using a multiplexer circuit that selectively outputs one of the up/down counting control signals, up/down counting output signals can be obtained with a small number of elements.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the counter circuit according to the present invention, FIG. 2 is a timing diagram showing an example of its operation, and FIG. 3 is a circuit diagram showing an example of the counter circuit according to the present invention. FIG. 4 is a timing diagram showing an example of its operation; FIG. 5 is a block diagram showing an application example of the counter circuit according to the present invention; FIG. 6 is a conventional up/down counter circuit diagram. FIG. 2 is a circuit diagram showing an example of a counter circuit. FF1~F F4... Counting circuit, M P X 1~M
Px4...multiplexer circuit, ROM...read-only memory, U/DCOUNT...up/down counter, D/A...digital/analog conversion circuit,
EXI~EX3...Exclusive OR circuit

Claims (1)

[Claims] A multiplexer circuit that receives a binary up/down counter circuit and a complementary output signal of each bit of the counter circuit and selectively outputs it in accordance with an up/down switching control signal. A counter circuit comprising: 2. The multiplexer circuit includes a three-state output circuit that is brought into a complementary state of operation according to the switching control signal;
2. The counter circuit according to claim 1, further comprising an output buffer circuit that receives an output signal from said three-state output circuit. 3. In the counter circuit, the carry output of the first stage circuit is an output signal via the multiplexer circuit,
3. The counter circuit according to claim 1, wherein the output signal of the first stage circuit is the output signal of one of the multiplexer circuits as is.