JPH04212521A - Ring counter - Google Patents

Abstract

PURPOSE:To reduce circuit scale by constituting a shift register by using latch circuits. CONSTITUTION:The shift register is provided to input a clock CLK while serially connecting the off-number steps, for example, the four steps of latch circuits 41-44 in the shape of a loop so that one of the adjacent latch circuits 41-44 can be turned to a through state and the other can be turned to a hold state. On the other hand, AND gates 51-54 are provided to output the prescribed value of one bit, for example, to output '1' when the output value of the adjacent latch circuit is the prescribed value of two bits, for example, it is '11'. For obtaining an initial state, a reset signal RSTX is supplied to preset signal input terminals PR or clear signal input terminals CLR of the respective latch circuits 41-44.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ring counters.

0002

2. Description of the Related Art Ring counters are used in various electronic devices as signal generating circuits for sequential control. It is also used in semiconductor integrated circuits, such as test signal generation circuits. Since this test generator circuit is not used at all during normal operation, it is desirable to reduce the circuit scale as much as possible.

FIG. 11 shows the basic type of a conventional ring counter. This ring counter has four stages of D flip-flops 11 to 14 connected in cascade in a ring shape. A clock CLK is supplied as a shift pulse to each clock input terminal CK of the D flip-flops 11 to 14. The outputs of the ring counter are Q1, Q2, Q3, and Q4 output from each non-inverting output terminal Q of the D flip-flops 11-14. In order to initialize this output to the binary number 1001, the preset signal input terminal PR of the D flip-flop 11 is
A reset signal RSTX is supplied to the clear signal input terminals CLR of the D flip-flops 12 to 14. When the clock CLK is supplied in this state, a bit of 1 is cyclically shifted for each pulse of the clock CLK.

The D flip-flops 11 to 14 have the same configuration, and the D flip-flop 11 is, for example, shown in FIG.
2, it is constructed using two latch circuits 21 and 22 and an inverter 23. Latch circuit 21
and 22 have the same configuration, and the latch circuit 22 includes four NAND gates 31 to 34, as shown in FIG. 13, for example.
It is configured using

[0005]

As described above, one flip-flop itself has a relatively large number of constituent elements. On the other hand, L
The number of stages of ring counter flip-flops normally used in SI test signal generation circuits is large, ranging from tens to hundreds of stages. Therefore, the circuit scale of the ring counter becomes large, and the circuit scale of the test signal generation circuit, which is not used at all during normal operation, also becomes large.

SUMMARY OF THE INVENTION In view of these problems, it is an object of the present invention to provide a ring counter with a small circuit scale.

[0007]

[Means for Solving the Problems and Their Effects] A ring counter according to the present invention will be explained with reference to the drawings.

In this ring counter, as shown in FIG. 1, an even number of stages, for example four stages, of latch circuits 41 to 44 are cascaded in a ring, and one of the adjacent latch circuits 41 to 44 is in a through state and the other is in a hold state. a shift register to which a clock CLK is input so that the output value of an adjacent latch circuit is 11, and a decoder circuit that outputs a 1-bit predetermined value, such as 1, when the output value of an adjacent latch circuit is a 2-bit predetermined value, such as 11; A reset signal RSTX is supplied to the preset signal input terminal PR or clear signal input terminal CLR of each latch circuit 41 to 44 in order to set the latch circuits to an initial state.

In the present invention, a shift register is constructed using a latch circuit, and a simple decoding circuit is added to the shift register to construct a ring counter.The latch circuit is constructed with approximately half the number of elements of a flip-flop. Therefore, the circuit scale of the ring counter can be made much smaller than in the past.

In the ring counter, the latch circuit has, for example, an output end of the emitter of a multi-emitter transistor, and the decode circuit is a circuit in which the emitters of adjacent latch circuits are connected to create a wired OR.

In this configuration, the decoding circuit is simplified, and therefore the configuration of the ring counter is further simplified.

Further, in the above ring counter, the latch circuit has, for example, an output end of the collector of a multi-collector transistor, and the decode circuit is a circuit in which the collectors of adjacent latch circuits are connected to each other in order to create a wired AND. be.

[0013] Also in this configuration, the decoding circuit is simplified, and therefore the configuration of the ring counter is further simplified.

In other ring counters, for example, as shown in FIG. 6, latch circuits 41 to 44 have an even number of n stages, for example, four stages.
are connected in cascade, and the clock CL is set so that one of the adjacent latch circuits is in a through state and the other is in a hold state.
A shift register to which K is input, and a decoding circuit that outputs a 1-bit predetermined value, for example, 1, when the output value of the adjacent latch circuit is a 2-bit predetermined value, for example, 11, such as AND gates 51 to 54. , when either the non-inverting output or the inverting output of each of the latch circuits in the second to n-1 stages is the same value, for example 1, the input terminal of the latch circuit in the first stage is supplied with a value opposite to the same value. An automatic reset circuit, for example, an AND gate 55, is provided to supply a value of 0, for example, 0.

[0015] This ring counter is self-correcting type,
An automatic reset will be applied. The automatic reset circuit, for example in the case of FIG. 6, can be configured with one AND gate, and the circuit scale of this ring counter is also significantly smaller than that of the conventional circuit for the same reason as above.

The ring counter described above uses latch circuits in even stages to output even bits, but the ring counter of the present invention, which uses latch circuits in even stages to output odd bits, is constructed as follows. .

That is, as shown in FIG. 7 or 9, for example, in this ring counter, an even number of stages, for example, four stages of latch circuits 41 to 44 are cascaded in a ring, with one of the adjacent latch circuits 41 to 44 being a through-hole. When the output value of the shift register to which the clock CLK is input and the adjacent latch circuit is a 2-bit predetermined value, e.g. 11, so that the other is in the hold state, a 1-bit predetermined value, e.g. 1, is output. Decode circuit, e.g. AND gates 51 to 54
When the reset signal RST is input from the outside or the output of the logic circuit for one latch becomes the specific value, the preset signal input terminal PR or clear signal input of each latch circuit 41 to 44 A reset circuit that supplies a reset signal to the terminal CLR, simultaneously inverts the clock level and returns it to the original state, and sets the outputs of the decoding circuits 51 to 53 to the initial state, for example, the AND gate 54 and the NOR gate 62 shown in FIG. and a T flip-flop 61, or an AND gate 54, a NOR gate 62, an exclusive OR gate 63, and a T flip-flop shown in FIG.
It has a reset circuit consisting of a flip-flop 64.

The reset circuit has a simple configuration in which the number of elements does not depend on the number of stages in the latch circuit, as will be clear from the following embodiments.For the same reason as above, this ring counter also has a circuit scale that is smaller than conventional circuits. will be significantly smaller than.

[0019]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

In order to simplify the explanation, a ring counter using a four-stage latch circuit will be described below.

1). First Embodiment FIG. 1 shows a ring counter of a first embodiment. This ring counter includes a shift register in which even stages (four stages) of latch circuits 41 to 44 are cascaded in a ring. That is, the non-inverting output terminal Q of the latch circuit 41 and the data input terminal D of the latch circuit 42 are connected, the non-inverting output terminal Q of the latch circuit 42 and the data input terminal D of the latch circuit 43 are connected, and the latch circuit The non-inverting output terminal Q of the latch circuit 43 is connected to the data input terminal D of the latch circuit 44.
The non-inverting output terminal Q of the latch circuit 41 and the data input terminal D of the latch circuit 41 are connected to form a four-stage shift register. At each clock input terminal CK of the latch circuits 41 to 44,
Wiring for supplying the clock CLK is commonly connected, and wiring for supplying the reset signal RSTX is connected to the clear signal input terminals CLR of the latch circuits 42 and 43 and the preset signal input terminals PR of the latch circuits 41 and 44. connected in common.

For example, the latch circuits 41 and 43 are shown in FIG.
As shown in FIG. 13, the latch circuits 42 and 44 are constructed using four NAND gates 31 to 34, and one inverter (not shown) is additionally connected to the clock input terminal CK of FIG.

In FIG. 13, when the clock input terminal CK, the clear signal input terminal CLR, and the preset signal input terminal PR are at high level, the data input terminal D and the non-inverting output terminal Q are at the same level, that is, a through state occurs. In this state, if the clock input terminal CK is set to low level, the non-inverting output terminal Q
The level is constant even if the level of the data input terminal D is changed, that is, it is in a hold state. Also, regardless of the level of the clock input terminal CK, if the clear signal input terminal CLR is set to a low level and the preset signal input terminal PR is set to a high level,
The non-inverting output terminal Q becomes a low level, and the inverting output terminal QX becomes a high level. Conversely, when the clear signal input terminal CLR is set to a high level and the preset signal input terminal PR is set to a low level, the non-inverting output terminal Q becomes a high level and the inverting output terminal QX becomes a low level.

In FIG. 1, latch circuit 4i (i=1 to
The data input terminal D and non-inverting output terminal Q of 4) are connected to the input terminal of an AND gate 5i (i=1 to 4) serving as a decoding circuit. The outputs of the ring counter are the outputs Q1, Q2, Q3, and Q4 of the AND gates 51-54.

In the first embodiment, a shift register is constructed with a latch circuit composed of about half the number of elements of a D flip-flop, and a simple decoding circuit is added to this to construct a ring counter. , the circuit scale of the ring counter can be reduced to about half of the conventional one. This effect is
This problem becomes significant when the number of output bits of the ring counter increases to several tens to hundreds as is commonly used in LSI test generation circuits.

Next, the operation of the ring counter configured as described above will be explained with reference to the timing chart shown in FIG.

(1) As shown in FIG. 2(A), the clock CLK is initially at a high level, so the latch circuits 41 and 43 are in the through state, and the latch circuits 42 and 44 are in the hold state. There is.

(2) In this state, when a negative pulse reset signal RSTX as shown in FIG. 2B is supplied, the non-inverting output terminal Q of the latch circuit 42 becomes low level,
The non-inverting output terminal Q of 4 becomes high level, and the latch circuit 41
The non-inverting output terminal Q of ~44 becomes the binary number 1001. Therefore, the output Q1Q2Q3Q4 of the ring counter is initially set to the binary number 1000 as shown in FIG. 2(G).

(3) When the clock CLK transitions to a low level, the latch circuits 41 and 43 are in the hold state and the latch circuits 42 and 44 are in the through state, so that the non-inverting output terminals Q of the latch circuits 41 to 44 are binary numbers. It becomes 1100. Therefore, the output Q1Q2Q3Q4 of the ring counter becomes the binary number 0100. That is, the latch circuits 41 and 42 function as one D flip-flop 11 constituting a conventional ring counter, hold the high level supplied to the data input terminal D of the latch circuit 41, and output the non-inverted output of the latch circuit 42. This is output from end Q. Similarly, the latch circuits 43 and 44 function as one D flip-flop 11 constituting a conventional ring counter, and hold the low level supplied to the data input terminal D of the latch circuit 43, so that the latch circuit 44 is not inverted. This is output from the output terminal Q.

(4) When the clock CLK transitions to a high level, the latch circuits 41 and 43 enter the through state and the latch circuits 42 and 44 enter the hold state, so that the non-inverting output terminals Q of the latch circuits 41 to 44 become binary numbers. It becomes 0110. Therefore, the output Q1Q2Q3Q4 of the ring counter becomes the binary number 0010. That is, the latch circuits 42 and 43 function as one D flip-flop 11 constituting a conventional ring counter, hold the high level supplied to the data input terminal D of the latch circuit 42, and output the non-inverted output of the latch circuit 43. This is output from end Q. Similarly, the latch circuit 44 and the latch circuit 41 function as one D flip-flop 11 constituting a conventional ring counter, and hold the low level supplied to the data input terminal D of the latch circuit 44 to output the latch circuit 41. This is output from the non-inverting output terminal Q.

(5) When the clock CLK transitions to a low level, the latch circuits 41 and 43 enter the hold state and the latch circuits 42 and 44 enter the through state, as described above.
The non-inverting output terminals Q of the latch circuits 41 to 44 are binary 001
It becomes 1. Therefore, the output of the ring counter Q1Q2
Q3Q4 becomes the binary number 0001.

(6) When the clock CLK transitions to a high level, the latch circuits 41 and 43 enter the through state and the latch circuits 42 and 44 enter the hold state, as described above.
The non-inverting output terminals Q of the latch circuits 41 to 44 are 100 in binary
It becomes 1. Therefore, the output of the ring counter Q1Q2
Q3Q4 returns to the initial state of binary number 1000.

Thereafter, the operations (3) to (6) above are repeated.

[0034] 2). Second example FIG. 3 shows a ring counter of a second embodiment.

Outputs Q1 to Q4 of the ring counter can be freely determined as the first bit, and in this embodiment, output Q2 is used as the first bit.

This ring counter has a latch circuit 4i (
The data input terminal D and the inverted output terminal QX of i=1 to 4) are
AND gate 5i (i=1 to 4) as a decoding circuit
It is the same as in FIG. 1 except that it is connected to the input terminal of.

As can be easily seen from the explanation of the first embodiment, the outputs Q1 to Q4 of the ring counter are based on the clock CL.
Each time K flips, the binary numbers 0100, 0010, 000
It changes as 1, 1000, 0100...

In this second embodiment, the output of the ring counter is the AND of the non-inverting output terminal Q on the rear stage side of the adjacent latch circuits and the inverting output terminal QX on the front stage side. The configuration may be such that the logical product of the side inverted output terminal QX and the previous stage side non-inverted output terminal Q is output from the ring counter. In this case, the output of the ring counter will be binary numbers 0001 and 1000 each time the clock CLK is inverted.
, 0100, 0010, 0001, etc.

[0039] 3). Third embodiment FIG. 4 shows a ring counter of a third embodiment.

This ring counter latch circuit 41A~
In 44A, the non-inverting output terminal Q is the emitter of a multi-emitter transistor, and the decoding circuit is a wired-OR circuit in which the non-inverting output terminals Q of adjacent latch circuits are simply connected. Therefore, the output of the ring counter is negative logic, and contrary to the case in FIG.
Wiring for supplying the reset signal RSTX is commonly connected to both.

Furthermore, the latch circuits 41A and 43A are supplied with the clock CLK, and the latch circuits 42A and 44A are supplied with the clock CLK.
is the clock CLK which is the inverted level of the clock CLK.
X is supplied.

Outputs Q1 to Q4 of this ring counter are as follows:
As can be easily seen from the explanation of the first embodiment, each time the clock CLK is inverted, the binary numbers 0111, 1011, 1
It changes as 101, 1110, 0111...

[0043] 4). Fourth example FIG. 5 shows a ring counter of a fourth embodiment.

Latch circuit 41B of this ring counter
In 44B, the non-inverting output terminal Q is the collector of a multi-collector transistor, and the decoding circuit is a wired AND circuit in which the non-inverting output terminals Q of adjacent latch circuits are simply connected. Therefore, as in FIG. 1, the output of the ring counter is positive logic, and the signal wiring for initialization is the same as in FIG. The clock supply is the same as in FIG.

Changes in the outputs Q1 to Q4 of this ring counter are the same as in the first embodiment.

[0046] 5). Fifth example FIG. 6 shows a ring counter of a fifth embodiment.

[0047] This ring counter is self-correcting type,
A reset signal is automatically generated. That is, the inverted output terminals QX of the latch circuits 42 and 43 are supplied to the AND gate 55, the output of the AND gate 55 is supplied to the data input terminal D of the latch circuit 41, and unlike the case of FIG. The non-inverting output terminal Q of the latch circuit 41 is not connected to the data input terminal D of the latch circuit 41. Other points are the same as in FIG.

Non-inverting output terminals Q of latch circuits 42 and 43
If both are not logical 0, a logical value 0 is supplied to the data input terminal D of the latch circuit 41. Therefore, the non-inverting output terminals Q of the latch circuits 42 and 43 both have a logical value 0 when the clock is inverted twice or less. At this time, the data input terminal D of the latch circuit 41 has a logic value of 0. When the latch circuit 41 enters the through state in this state or the next clock inversion, the output Q1Q2Q3Q4 of the ring counter becomes 1000 in binary.

After that, every time the clock CLK is inverted, the binary numbers 0100, 0010, 0001, 1000, 0
It changes as 100...

6). Sixth Embodiment In the first to fifth embodiments described above, a ring counter that outputs even bits using an even stage latch circuit 41 was explained, but a ring counter that outputs an odd bit using an even stage latch circuit 41 is configured. It is also possible to do this, which will be explained next.

FIG. 7 shows the circuit configuration of the ring counter of the sixth embodiment. The difference from FIG. 1 is that the clock CLK is
In order to change the output value in units of one clock as in the conventional ring counter, a T flip-flop 61 is used to change the output value by 1/2.
The frequency is divided and supplied to each clock input terminal CK of the latch circuits 41 to 44, and the reset signal RST is passed through the NOR gate 62 to the clear signal input terminal CLR of the latch circuits 41 to 43 and the preset of the latch circuit 44. The signal is supplied to the signal input terminal PR, and the output of the AND gate 54 is supplied to the other input terminal of the NOR gate 62. The outputs of this ring counter are Q1, Q2, and Q3 output from AND gates 51-53. The other points are the same as in FIG. 1, and like the first embodiment, the circuit scale of the ring counter can be reduced to about half of the conventional one.

Next, the operation of the ring counter configured as described above will be explained with reference to the timing chart shown in FIG.

(1) As shown in FIGS. 8(A) and (D),
The clock CLK and the non-inverting output terminal Q of the T flip-flop 61 are initially at a low level, so the latch circuits 41 and 43 are in a hold state, and the latch circuits 42 and 44 are in a through state.

(2) In this state, when a positive pulse reset signal RST as shown in FIG. Non-inverting output terminal Q of flip-flop 61
transitions to high level, the latch circuits 41 and 43 are in the through state, and the latch circuits 42 and 44 are in the hold state. Therefore, the non-inverting output terminal Q of the latch circuits 41 to 44 becomes the binary number 1001, and the output Q of the ring counter
1Q2Q3 is initialized to the binary number 100 as shown in FIG. 8(I).

(3) When the clock CLK transitions to a high level, the non-inverting output terminal Q of the T flip-flop 61 transitions to a low level as shown in FIG. 8(D), and the latch circuit 41
and 43 are in the hold state, and the latch circuits 42 and 44 are in the through state, so that the non-inverting output terminals Q of the latch circuits 41 to 44 become 1100 in binary. Therefore, the output Q1Q2Q3 of the ring counter becomes the binary number 010.

Next, even when the clock CLK transitions to a low level, the non-inverting output terminal Q of the T flip-flop 61 does not change, so the output of the ring counter also does not change.

(4) When the clock CLK transitions to a high level, the non-inverting output terminal Q of the T flip-flop 61 transitions to a high level as shown in FIG. 8(D), and the latch circuit 41
and 43 are in the through state, and the latch circuits 42 and 44 are in the hold state, so that the non-inverting output terminals Q of the latch circuits 41 to 44 become the binary number 0110. Therefore, the output Q1Q2Q3 of the ring counter becomes the binary number 001.

Next, even when the clock CLK transitions to a low level, the non-inverting output terminal Q of the T flip-flop 61 does not change, so the output of the ring counter also does not change.

(5) When the clock CLK transitions to a high level, the non-inverting output terminal Q of the T flip-flop 61 transitions to a low level in the same manner as described above, and the latch circuits 41 and 43 are in the hold state, and the latch circuits 42 and 44 are in the hold state. is in the through state, so the non-inverting output terminals Q of the latch circuits 41 to 44 are
The base number becomes 0011. However, the output of the AND gate 54 changes to high level and the output of the NOR gate 62 changes to low level as shown in FIG.
4's non-inverting output terminal Q immediately becomes the binary number 0001, which causes the output of the AND gate 54 to transition to a low level,
The same operation as at the first initial reset is performed. Therefore, the non-inverting output terminal Q of the latch circuits 41 to 44
immediately becomes the binary number 1001, and the output Q1Q2Q3 of the ring counter becomes the binary number 100. That is, the initial reset is automatically performed at the third clock pulse.

Next, even when the clock CLK transitions to a low level, the non-inverting output terminal Q of the T flip-flop 61 does not change, so the output of the ring counter also does not change.

Thereafter, the operations (3) to (5) above are repeated.

7). Seventh Embodiment In the sixth embodiment described above, the case where the clock CLK is divided by 1/2 by the T flip-flop 61 has been explained. can be configured, which will be explained next.

FIG. 9 shows the circuit configuration of a ring counter according to the seventh embodiment. The difference from FIG. 7 is that the clock CLK is passed through the exclusive OR gate 63 to the latch circuit 41.
~44 clock input terminal CK, AND gate 5
4 is supplied to the input terminal of the exclusive OR gate 63 via the T flip-flop 64, and the T flip-flop 64 is preset by the reset signal RST. In this seventh embodiment, as in the first embodiment, the circuit scale of the ring counter can be reduced to about half of the conventional one.

Next, the operation of the ring counter configured as described above will be explained with reference to the timing chart shown in FIG.

(1) As shown in FIGS. 10A and 10D, the clock CLK and the non-inverting output terminal Q of the T flip-flop 64 are initially at a low level, and the exclusive OR gate 63 The output is also at a low level. Therefore, the latch circuits 41 and 43 are in the hold state,
The latch circuits 42 and 44 are in a through state.

(2) In this state, when a positive pulse reset signal RST as shown in FIG. Since the non-inverting output terminal Q of the flip-flop 64 transitions to high level, the latch circuits 41 and 43
is in the through state, and the latch circuits 42 and 44 are in the hold state. Therefore, the non-inverting output terminals Q of the latch circuits 41 to 44 become the binary number 1001, and the outputs Q1Q2Q3 of the ring counter are initially set to the binary number 100 as shown in FIG. 10(J).

(3) When the clock CLK transitions to a high level, the non-inverting output terminal Q of the exclusive OR gate 63 transitions to a low level as shown in FIG. 10(E), and the latch circuits 41 and 43 are held. Since the latch circuits 42 and 44 are in the through state, the latch circuits 41 to 44
The non-inverting output terminal Q of is the binary number 1100. Therefore, the output Q1Q2Q3 of the ring counter is the binary number 010
becomes.

(4) When the clock CLK transitions to a low level, the non-inverting output terminal Q of the exclusive OR gate 63 transitions to a high level as shown in FIG. Since the latch circuits 42 and 44 are in the hold state, the latch circuits 41 to 44
The non-inverting output terminal Q becomes the binary number 0110. Therefore, the output Q1Q2Q3 of the ring counter is the binary number 001
becomes.

(5) When the clock CLK transitions to a high level, the non-inverting output terminal Q of the exclusive OR gate 63 transitions to a low level in the same way as described above, causing the latch circuits 41 and 43 to be in the hold state, and the latch circuit 42 to be in the hold state. and 44 are in the through state, so the non-inverting output terminals Q of the latch circuits 41 to 44 become the binary number 0011. However, and gate 5
4 transitions to high level, and the output of T flip-flop 64 becomes low level as shown in FIG. 10(D).
The non-inverting output terminals Q of the latch circuits 41 to 44 immediately become the binary number 0001, which causes the output of the AND gate 54 to transition to a low level, and the same operation as that at the first initial reset is performed. Therefore, latch circuits 41 to 4
The non-inverting output Q of 4 immediately becomes 1001 in binary, and the output Q1Q2Q3 of the ring counter becomes 100 in binary. That is, when the level of the clock CLK is inverted three times, the initial reset is automatically performed.

Thereafter, the operations (3) to (5) above are repeated.

Note that the present invention includes various other modifications. For example, a NAND gate may be used instead of the AND gates 51 to 54. In addition, latch circuits 41 to 4
For each of the AND gates 51 to 54, a decoding circuit that outputs 1 when the logical value of the data input terminal D and the non-inverting output terminal Q is 01 or 10 may be used in place of the AND gates 51 to 54. It goes without saying that the present invention also includes modifications in which the sixth and seventh embodiments are combined with the concepts of the second to fifth embodiments.

[0072]

As explained above, in the ring counter according to the present invention, a shift register is constructed using a latch circuit, a simple decoding circuit is added to this, and when the number of output bits is an odd number, A ring counter is constructed by adding a simple reset circuit whose number of elements does not depend on the number of stages of the latch circuit.Since the latch circuit is constructed with approximately half the number of elements of a flip-flop, the circuit scale of the ring counter can be reduced. It has the effect of being able to be made much smaller than the conventional one, and greatly contributes to substantially higher integration of semiconductor integrated circuits and reduction in chip area.

If the output terminal of the latch circuit is the emitter of a multi-emitter transistor, and the decoder circuit is a circuit in which the emitters of adjacent latch circuits are connected to create a wired OR, or the output terminal of the latch circuit is If the collector of a multi-collector transistor is used and the decode circuit is a circuit in which the collectors of adjacent latch circuits are connected to create a wired AND, the circuit scale of the ring counter can be further reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a ring counter of a first embodiment.

FIG. 2 is a timing chart of the circuit of FIG. 1;

FIG. 3 is a circuit diagram of a ring counter of a second embodiment.

FIG. 4 is a circuit diagram of a ring counter of a third embodiment.

FIG. 5 is a circuit diagram of a ring counter of a fourth embodiment.

FIG. 6 is a circuit diagram of a ring counter of a fifth embodiment.

FIG. 7 is a circuit diagram of a ring counter according to a sixth embodiment.

FIG. 8 is a timing chart of the circuit of FIG. 7;

FIG. 9 is a circuit diagram of a ring counter according to a seventh embodiment.

FIG. 10 is a timing chart of the circuit of FIG. 9;

FIG. 11 is a circuit diagram of a conventional ring counter.

FIG. 12 is a circuit diagram of a master-slave type D flip-flop.

13 is a diagram of a latch circuit forming the circuit of FIG. 12. FIG.

[Explanation of symbols]

21, 22, 41-44, 41A-44A, 41B-4
4B Latch circuit 23 Inverters 31 to 34 NAND gates 51 to 54, 55 AND gates 61, 64 T flip-flop 62 NOR gate 63 Exclusive OR gate CK Clock input terminal D Data input terminal Q Non-inverting output terminal CLR Clear signal input terminal PR Preset signal input end

Claims (8)

[Claims] Claim 1: Even-numbered stage latch circuits (41 to 44, 4
1A to 44A, 41B to 44B) are cascaded in a ring, and the clocks (CLK, CLKX
), and the decoding circuits (51 to 54) are provided with an even number of decoding circuits that receive the output values of the adjacent latch circuits and output one bit, and are in an initial state. The preset signal input terminal (RR) or clear signal input terminal (CLR) of each latch circuit
1. A ring counter, wherein a reset signal (RSTX) is supplied to the ring counter, only one bit of the output of the even-numbered decoding circuit is inverted from other bits, and the inverted bit transitions with the clock. 2. The decoding circuit includes AND gates (51 to 54) to which output values of the adjacent latch circuits are supplied.
) The ring counter according to claim 1. 3. The output end of each of the latch circuits (41A to 44A) is an emitter of a multi-emitter transistor, and the decode circuit is a circuit in which the emitters of adjacent latch circuits are connected to each other to create a wired OR. The ring counter according to claim 1, characterized in that: 4. The latch circuits (41B to 44B) have output terminals that are collectors of multi-collector transistors, and the decode circuit is a circuit in which the collectors of adjacent latch circuits are connected to each other to create a wired AND. The ring counter according to claim 1, characterized in that: [Claim 5] Latch circuit with even n stages (41 to 44)
are connected in cascade, and one of the adjacent latch circuits is in a through state and the other is in a hold state.
The decoding circuits (51 to 54) are provided with an even number of shift registers to which LK) is input and decoding circuits to which the output values of the adjacent latch circuits are input and output one bit.
When one of the non-inverting output and the inverting output of each of the second to n-1 stage latch circuits has the same value, a value opposite to the same value is applied to the input terminal of the first stage latch circuit. and an automatic reset circuit (55) that supplies the output of the even-numbered decoding circuit, only one bit of the output of the even-numbered decoding circuit is inverted from the other bits, and the inverted bit transitions with the clock. ring counter. 6. A shift device in which an even number of stages of latch circuits (41 to 44) are cascaded in a ring, and a clock (CLK) is input so that one of the adjacent latch circuits is in a through state and the other is in a hold state. A register, an odd number of decoding circuits (51 to 53) which are one less than an even number of decoding circuits that output 1 bit by inputting the output value of the adjacent latch circuit, and a reset signal (R
ST) is input, or when the output of the logic circuit for one latch becomes the specific value, the preset signal input terminal (PR) or clear signal input terminal (CLR) of each of the latch circuits is input. a reset circuit (54, 61) that supplies a reset signal and simultaneously inverts the level of the clock and returns it to its original state to bring the output of the decoding circuit to an initial state;
~64), wherein only one bit of the output of the odd-numbered decoding circuit is inverted from other bits, and the inverted bit transitions with the clock. A ring counter characterized by: 7. In the shift register, a latch circuit whose clock input terminal is in a through state when the clock input terminal is at a high level and a latch circuit whose clock input terminal is in a through state when the clock input terminal is at a low level are alternately connected in cascade, and each of the clock input terminals is connected in series. 7. The ring counter according to claim 1, wherein a single-phase clock is input to the ring counter. 8. The shift register is characterized in that latch circuits having the same configuration are connected in cascade, and clocks having mutually opposite phases are input to the clock input terminals of the adjacent latch circuits. The ring counter described in any one of.