JPS62192836A - Enciphered storage device - Google Patents

Abstract

PURPOSE:To protect a function so as to be well-adapted to an attribute of a data, b constituting the titled device so that a write data cannot be read out of a memory circuit, unless a cipher key data which is inputted at the time of write is inputted to a pseudo random pattern generating circuit at the time of read-out. CONSTITUTION:A write data 10 is converted to a serial write data 14 by a parallel-serial converting circuit 2, and inputted to an exclusive OR circuit 6. Also, a pseudo random pattern 13 which is generated by pseudo random pattern generating circuit 8, based on a cipher key data 12 is inputted to the exclusive OR circuit 6. An output signal 15 of the exclusive OR circuit 6 is stored in a memory circuit 1. On the other hand, at the time of read-out of a signal, a read-out signal 17 of a memory circuit 1 and the pseudo random pattern 13 are inputted to an exclusive OR circuit 7. Subsequently, an exclusive OR output (series signal) 19 is converted to a parallel signal, and outputted as a read-out data 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an encrypted storage device, and particularly to an encrypted storage device that prevents unauthorized copying and If#g of contents.

(Prior art) Conventionally, in this type of encrypted storage device,
As disclosed in No. 988 as "Be protection method for stored data," leakage of secret data is prevented by rearranging bits using an array conversion circuit when writing data to memory.

(Problems to be Solved by the Invention) The conventional encrypted storage device described above uses bit recombination by an array conversion circuit, so it is not suitable, for example, when maintaining fixed secrecy for the entire memory. be. However, in cases where security protection that is appropriate for data attributes, such as ownership or confidentiality level, is required, using such an encrypted storage device requires multiple array conversion circuits, which increases costs. It will become bulky. Furthermore, when such an encrypted storage device is connected to a type I'ii array conversion circuit, the possibility of introducing noise components increases accordingly, reducing the reliability of the circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide an encrypted storage device that has a simple circuit configuration and is capable of ensuring functionality tailored to the attributes of data.

(Means for solving the problem) The encrypted storage device provided by the present invention to solve the above problem includes a pseudo-random pattern generation circuit that generates a pseudo-random pattern according to input encryption key data, and a write a first exclusive OR circuit that receives data and the pseudo-random pattern as input; a memory circuit that stores the output of the first exclusive OR circuit; and the data read from the memory circuit and the random pattern. An encrypted storage device comprising a second exclusive OR circuit which receives as input a pseudorandom pattern generated by a generation circuit, and uses the output of the second exclusive OR circuit as read data. .

(Example) Next, an encrypted storage device of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the encrypted storage device of the present invention. In this figure, numeral 1 is a memory circuit, 2 and 3 are parallel-to-serial conversion circuits, 4.5 is a clear-to-parallel conversion circuit, 6.7 is an exclusive OR circuit,
8 is a pseudo-random pattern generation circuit. This pseudo-random pattern generation circuit 8 uses a feedback type shift register, and by changing the number of stages of the register and the take-out position of the feedback pulse, the period and pulse pattern of the generated pulse series can be easily changed. Reference numeral 10 represents write data, and 11 represents read data. Reference numeral 12 is encryption key data, and when the encryption key data 12 is input to the pseudo-random pattern generation circuit 8,
The repetition period of the pseudo-random pattern pulse is determined based on the encrypted data. Write data 10 input to the parallel-serial conversion circuit 2 is converted into a serial signal by the parallel-serial conversion circuit 2 and input to the exclusive OR circuit 6. The other signal input to the exclusive OR circuit 6 is a pseudo-random pattern 1 generated by the pseudo-random pattern generation circuit 8 based on the encryption key data 12 input to the pseudo-random pattern generation circuit 8.
It is 3.

This pseudo-random pattern 13 is generated by the exclusive OR circuit 6
The serial write data 14 is scrambled. As shown in FIGS. 2(a) and 2(b), the exclusive OR circuit 6 is configured such that only one of the input signals has a logical value of "1".
The output signal 15 is set to a logical value "1" only when this happens. The output signal 15 of the exclusive OR circuits is shown in FIG. 2(c). Next, the serial-parallel conversion circuit 4 converts the signal 15 into a parallel signal. The memory circuit 1 stores display data of the output signal 15 of the clear-to-parallel conversion circuit 4. On the other hand, signal reading is performed as follows.

First, the data stored in the memory circuit is extracted as a parallel signal. This readout signal 17 is shown in FIG. 2(d).
Shown below. Then, the parallel-serial conversion circuit 3 converts the serial signal into a parallel signal, and outputs the converted signal 18 to the exclusive OR circuit 7. In this case, the pseudo-random Hull-y generating circuit 8 may also be used as the pseudo-random pattern 13.
is input to the exclusive OR circuit 7. The pseudorandom pattern 13 at this time is the same pseudorandom signal ((e) in the same figure) as in (b) of the same figure. That is, the same encryption key data 12 that was input to the pseudo-random pattern generation circuit 8 at the time of writing is input to the pseudo-random pattern generation circuit 8. The exclusive OR circuit 7 restores the write data by setting the logic value of the output signal 19 to rlJ only when either of the two input signals has a logic value of "1". The serial-parallel conversion circuit 5 has an exclusive OR output (serial signal) 1
9 is converted into a parallel signal and output as read data 11. This read data is shown in FIG. 4(f).

In the encrypted storage device of this embodiment, the operator memorizes the encryption key data 12 input at the time of writing until it is read out, and does not input the encryption key data 12 to the pseudo-random pattern generation circuit 8 at the time of reading. Write data as long as 10
cannot be read out from the memory circuit 1, so it is possible to adapt to the 4-ratio of data (good protection).

Furthermore, since the encrypted storage device of this embodiment has a simple circuit configuration, it is possible to reduce costs.

(Effects of the Invention) As described above, according to the present invention, it is possible to perform security protection that is appropriate to the attributes of data, thereby preventing data leakage and theft. Furthermore, since the encrypted storage device of the present invention has a simple circuit configuration, it is possible to reduce costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the encrypted storage device of the present invention, and FIGS. 2(a) to 2(f) are timing diagrams explaining the operation of the embodiment of FIG. 1...Memory circuit, 2, 3...Parallel-serial conversion circuit, 4, 5.../Real-to-parallel conversion circuit, 6, 7...Exclusive OR circuit, 8...Pseudo-random pattern generation circuit. Figure 1

Claims (1)

[Claims] a pseudo-random pattern generation circuit that generates a pseudo-random pattern according to input encryption key data; a first exclusive OR circuit that receives write data and the pseudo-random pattern; comprising a memory circuit that stores the output of the OR circuit; and a second exclusive OR circuit that receives as input the data read from the memory circuit and the pseudo-random pattern generated by the random pattern generation circuit; An encrypted storage device characterized in that the output of two exclusive OR circuits is read data.