JPH02112082A - Microprocessor and ic card to use same - Google Patents

Abstract

PURPOSE:To execute encoding processing at a high speed by providing a processing unit, an input/output means, a memory means, a random number generating means, an encoding means and a decoding means on an integrated circuit substrate. CONSTITUTION:When a microprocessor 100 is connected to an external equipment and activated, a processing unit 10 executes the initialization processing of a random number generating means 140 at first and permits the generation of a dummy random number according to the instruction of a program which is housed to a memory means 160. Then, the input/output processing of data to an encoding means 120 and a decoding means 130, the writing and reading processing of data to the memory means 160 and data processing such as arithmetic computation or logical arithmetic is executed. At such a time, since the random number generating means 140, encoding means 120 and decoding means 130 are provided on the same integrated circuit substrate, danger that a generated dummy random number string RN or decoded general sentence data RD, etc., leak out of the external part of the microprocessor 100 is extremely limited. Thus, the encoding processing can be safely executed at the high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microprocessor that mainly performs data input/output, storage, arithmetic processing, etc., and an IC card in which the microprocessor is incorporated into a portable card. It is something.

BACKGROUND OF THE INVENTION FIG. 3 shows a conventional example of a microprocessor.

In FIG. 3, the microprocessor 300 includes a processing unit 31o that mainly performs data processing such as arithmetic calculations and logical operations, an input/output means 360 that performs data input/output processing to connected external devices, and Units)
It is comprised of memory means 360 for storing programs for specifying the operation of the 3ffO and data input from the input/output means 360.

The operation of the conventional microprocessor configured as described above will be described below.

The microprocessor 300 is connected to an external device (not shown), a power supply VaC, and a clock signal CLK.

When the reset signal R5T etc. is supplied, the processing unit)
310 performs data processing such as arithmetic calculations and logical operations according to the instructions of the program stored in the memory means 360;
It performs data input/output processing with respect to the input/output means 360, data writing/reading processing with respect to the memory means 360, and the like.

Generally, data input from connected external devices is
The input data is input to the processing unit 310 by the input/output means 360, and the processing unit 31o performs predetermined data processing on this input data and writes it into the memory means 360. Further, the data recorded in the memory means 360 is read out by the processing unit 310, subjected to predetermined data processing, and then outputted to the external device via the input/output means 350.

When such a microprocessor 300 is incorporated into an IC card and used, encryption is often used for security purposes, such as preventing counterfeiting of the IC card and external devices connected to it, and preventing data being exchanged from being concealed or tampered with. Processing techniques are utilized. Such cryptographic processing is sequentially executed in the processing unit 310 according to instructions from a program stored in the memory means 310, like other processing.

Problems to be Solved by the Invention However, in such a conventional microprocessor configuration, cryptographic processing is realized by software in the processing unit 31o, so data input/output processing and cryptographic processing are performed sequentially. Can not. Therefore,
The problem has been that the response time of the IC card to the external device is considerably longer than when no cryptographic processing is performed.

Furthermore, in order to realize cryptographic processing by software,
- If a simple encryption method is adopted, a program of 1 to 2 bytes is required, which places a considerable burden on the microprocessor 300 with the built-in memory means 360.

Therefore, when cryptographic processing was introduced into an IC card, there were problems such as the size of the application program became relatively small and the functions of the card had to be reduced.

The present invention solves these conventional problems by providing a microprocessor that can perform high-speed and secure cryptographic processing without increasing the program size, and an IC card incorporating this microprocessor. It is intended to.

Means for Solving the Problems In order to achieve the above object, the microprocessor of the present invention includes, in addition to a processing unit, an input/output means, and a memory means.
random number generation means for generating a pseudo-random number sequence specified by the processing unit; and encryption means for encrypting transmission data output from the processing unit using the pseudo-random number sequence obtained from the random number generation means-75-; A decoding means for decoding received data obtained from the input/output means using a pseudo-random number sequence obtained from the random number generation means is provided on the integrated circuit board.

According to the above-described structure, when the microprocessor is connected to an external device and activated, the processing unit first performs the following operations according to the instructions of the program stored in the memory means.
Performs initialization processing of the random number generation means to permit generation of a pseudo-random number sequence, performs data input/output processing to the encryption means and decryption means, data writing/reading processing to the memory means, arithmetic calculations, logical operations, etc. Perform data processing.

Generally, encrypted data inputted from the external device is inputted into a microprocessor by an input/output means, decrypted into plaintext data by a pseudorandom number sequence obtained from a random number generation means in a decryption means, and inputted to a processing unit. Ru. This processing unit performs predetermined data processing on input plaintext data, and writes and records the results in memory means.

Furthermore, the data recorded in the memory means is read out by the processing unit, subjected to predetermined data processing, and then input to the encryption means. The encryption means uses a pseudo-random number sequence obtained from the random number generation means to encrypt input data, and outputs the encrypted data from the input/output means to an external device connected to the input/output means.

At this time, since the random number generation means and the encryption and decryption means are provided on the integrated circuit board, there is extremely little risk that the generated pseudorandom number sequence and decrypted plaintext data will leak outside the microprocessor.

As described above, the microprocessor of the present invention can perform cryptographic processing at high speed and safely without increasing the program size.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing an embodiment of a microprocessor of the present invention.

In FIG. 1, IIQ is a processing unit that mainly performs data processing such as arithmetic calculations and logical operations, 150 is an input/output means that performs data input/output processing for connected external equipment, and 160 is the operation of the processing unit 110. This is a memory means for holding a program for specifying a program and data input from the input/output means 160. Further, 140 is a random number generation means for generating a pseudo-random number sequence RN specified by the processing unit 110, and 120 is a cipher for encrypting the transmission data output from the processing unit 11o using the pseudo-random number sequence RN obtained from the random number generation means 140. The decoding means 130 is a decoding means for decoding the received data obtained from the input/output means 160 using the pseudo random number sequence RN obtained from the random number generation means 140, and each of the above components is provided on a single integrated circuit board. A microprocessor 100 is configured.

For a microprocessor configured as above,
The operation will be explained below.

When the microprocessor 1oO is connected to an external device (not shown) and activated by supplying a predetermined power supply VCa, clock signal CLK, reset signal R8T, etc., the processing unit 110 executes the program stored in the memory means 160. After initializing the random number generation means 14Q according to the instructions, the random number generation permission signal gNB permits generation of a pseudorandom number sequence RN in synchronization with the timing of data transmission and reception, and the encryption and decryption means 120 , 130, data writing/reading processing to and from the memory means 160, and data processing such as arithmetic calculations and logical operations.

Encrypted data E (RD) is generally input from the external device.
) is output to the microprocessor 1 by output means 'J50.
00, is decoded by the decoding means 13) into plain text data HD using the pseudo random number sequence RN obtained from the random number generation means 140, and is input to the processing unit) 110. In the processing unit 110, input plaintext data RD
is subjected to predetermined data processing, and the results are stored in the memory means 16.
Write to 0 and record. Furthermore, the data recorded in the memory means '760 is read out by the processing unit 110, subjected to predetermined data processing, and then input to the encryption means 120. The encryption means 120 encrypts the input data SD using the pseudo-random number sequence RN obtained from the random number generation means 14Q, and the encrypted data E (SD) is connected from the input/output means 15Q. output to an external device.

At this time, since the random number generation means 140 and the encryption and decryption means 120 and 130 are provided on the same integrated circuit board, the generated pseudorandom number sequence RN, decrypted plain text data RD, etc. are stored in the microprocessor 1oo. The risk of leakage to the outside is extremely low.

As described above, according to this embodiment, the processing unit 11o
By providing the random number generation means 140, the encryption means 12o, and the decryption means 130 on a single substrate in the microprocessor 100 having the input/output means 150 and the memory means 160, cryptographic processing can be performed at high speed and safely. It can be carried out.

(Embodiment 2) FIG. 2 is a block diagram showing an embodiment of the microprocessor of the present invention.

In FIG. 2, 210 is a processing unit), 260 is an input/output means, and 260 is a memory means, all of which are similar to the configuration shown in FIG. 1.

241 is an n-bit shift register composed of n flip-flops connected in series, and 242 is the output Q1 of the final stage in the shift register 241 and the m-th stage counting from the final stage (where m(n) The output Q1 of the shift register 241 is sent to the first stage of the same shift register 241 via the first exclusive OR gate 242. Since it is feedbanked to the input Dn, it has a configuration of a linear feedback shift register, and from the above, a random number generation means is configured.

Further, 220 is a second exclusive OR gate which performs an exclusive OR operation between the transmitting gate 8D outputted from the processing unit 210 and the pseudo random number sequence RN obtained from the shift register 241; Become. 23-o is a receiving gator IC (HD) outputted from the input/output means 250,! : A third exclusive OR gate that performs an exclusive OR operation with the pseudo random number sequence RN obtained from the shift register 241 serves as a decoding means.

For a microprocessor configured as above,
The operation will be explained below.

When the microprocessor 200 is connected to an external device (not shown) and activated by supplying a predetermined power supply Vaa, clock signal CLK, reset signal RfST, etc., the processing unit 210 executes the program stored in the memory means 260. According to the instructions, for the shift register 241,
Clear signal 1 (LR is turned off, and while supplying a predetermined shift register clock signal 5RCLK, the initial value IRN of the pseudo random number sequence is loaded into each register of the shift register 241, and a data input/output request is waited for.

When transmitting encrypted data from the microprocessor 200, the processing unit 210 supplies a shift register clock signal 8RCLK to the shift register 241 in synchronization with the data transmission, and generates a pseudo-random number sequence RN. The second exclusive OR group) 220 includes the processing unit 21o
The plaintext transmission data SD sent from the shift register 241 is logically ORed with the pseudorandom number sequence RN obtained from the shift register 241, and the transmission data is encrypted. The encrypted transmission data x(sn) is outputted from the microprocessor 200 to the external device by the input/output means 260.

When the microprocessor 200 receives encrypted data from the external device, the processing unit 210 generates the shift register clock signal 5 in synchronization with the received data.
RCLK is supplied to the shift register 241 to generate a pseudo random number sequence RN. This pseudo-random number sequence RN is input to the third exclusive OR gate 230, where the input/output means 26
A logical OR operation is performed with the encrypted received data K (RD) obtained from 0, and the received data K (HD) is decrypted into plain text and input to the processing unit 21<). Ru.

Generally, it is known that in a linear feedback shift register using an n-bit shift register 241, a pseudorandom number sequence generated by calculation can be estimated by using a pair of 2n-bit plaintext data and encrypted data.

However, since the plaintext data exists only inside the microprocessor 200 and there is very little possibility of it being leaked to the outside, it is necessary to adopt a sufficiently large value n and to periodically change the initial value IRN of the pseudorandom number sequence. This results in an extremely secure system.

As described above, in the microprocessor 200, by using the shift register 24.1 as the random number generation means and the exclusive OR group 242 as the encryption and decryption means, the microprocessor 200 can be realized at high speed with an extremely simple configuration. Can perform encryption processing.

Effects of the Invention As described above, the microprocessor of the present invention has the following effects:
By providing a processing unit, an input/output means, a memory means, a random number generation means, an encryption means, and a decryption means on an integrated circuit board, cryptographic processing is performed at high speed without increasing the program size. It is possible to realize an excellent microprocessor that can.

Furthermore, in the microprocessor of the present invention, since the random number generation means and the encryption and decryption means are configured on an integrated circuit board, there is no risk that the generated pseudorandom number sequence or decrypted plaintext data will be leaked to the outside. Extremely rare and safe I
A C card device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprocessor according to a first embodiment of the invention, FIG. 2 is a block diagram of a second embodiment of the invention, and FIG. 3 is a block diagram of a conventional microprocessor. 100.200...Microprocessor j5Q
. 250... Input/output means, 180.260...
... Memory means, 120 ... Encryption means, 1
30...Decoding means, 140...Random number generation means, 220, 230°242...Exclusive OR gate, 241...Shift register. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 7m Microbrosevsa

Claims (3)

[Claims] (1) A processing unit that mainly performs data processing such as arithmetic calculations and logical operations, an input/output means that performs data input/output processing to connected external devices, and a program that specifies the operation of the processing unit. a memory means for retaining data inputted from the input/output means; a random number generation means for generating a pseudorandom number sequence specified by the processing unit; Encryption means for encrypting transmitted data to be output, and decoding means for decoding received data obtained from said input/output means using a pseudo-random number sequence obtained from said random number generation means, are provided on an integrated circuit board. microprocessor. (2) The microprocessor according to claim 1, wherein the random number generation means comprises a shift register comprising a plurality of flip-flops connected in series and one or more exclusive OR gates. (3) I having the microprocessor according to claim 1
C card device.