JPS62190715A - Manufacture of semiconductor thin film crystal layer - Google Patents
Manufacture of semiconductor thin film crystal layerInfo
- Publication number
- JPS62190715A JPS62190715A JP3179186A JP3179186A JPS62190715A JP S62190715 A JPS62190715 A JP S62190715A JP 3179186 A JP3179186 A JP 3179186A JP 3179186 A JP3179186 A JP 3179186A JP S62190715 A JPS62190715 A JP S62190715A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- semiconductor thin
- crystal layer
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000010409 thin film Substances 0.000 title claims abstract description 33
- 239000013078 crystal Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010408 film Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000010894 electron beam technology Methods 0.000 claims abstract description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 238000000137 annealing Methods 0.000 abstract description 7
- 238000009826 distribution Methods 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract 2
- 230000001788 irregular Effects 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 20
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、絶縁膜上に単結晶シリコン等の半導体薄膜結
晶層を形成する半導体i’1ml結晶層の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor i'1ml crystal layer in which a semiconductor thin film crystal layer of single crystal silicon or the like is formed on an insulating film.
近年、電子ビームやレーザビーム等を用いたビームアニ
ール法で、絶縁股上に半導体単結晶層を形成する、所謂
5OI(絶縁膜上のシリコン膜)技術の開発が盛んに行
われている。さらに、このSol技術を利用して、素子
を3次元的に形成する3次元ICの開発も進められてい
る。3次元ICを実現するには、半導体ウェハ表面に形
成された素子(下層素子)上にSOI技術により半導体
単結晶層を形成する。しかるのち、この単結晶層に素子
(上層素子)を形成することにより、積層構造素子が形
成されることになる。In recent years, so-called 5OI (silicon film on insulating film) technology has been actively developed in which a semiconductor single crystal layer is formed on an insulating layer by a beam annealing method using an electron beam, a laser beam, or the like. Furthermore, the development of three-dimensional ICs in which elements are formed three-dimensionally is also progressing using this Sol technology. To realize a three-dimensional IC, a semiconductor single crystal layer is formed using SOI technology on elements (lower layer elements) formed on the surface of a semiconductor wafer. Thereafter, a layered structure element is formed by forming an element (upper layer element) on this single crystal layer.
ところで、エネルギービームによって上層素子形成用の
半導体単結晶層を作成する際には、層間絶縁膜の開口部
より下部半導体基板を結晶成長の種として結晶成長が行
われる。しかし、第3図(a)に示す如き従来の試料構
造では、開口部に露出した半導体基板の熱伝導度と絶縁
膜の熱伝導度とが大きく異なることから、エネルギービ
ームにより半導体層を溶融した際に、層間絶縁膜の肩部
での温度分布が著しく不均一となる。このため、半導体
層が肩部で収縮し、第3図(1))に示す如く欠落部を
生じてしまうと云う問題があった。なお、第3図におい
て31は単結晶シリコン基板、32は層間絶縁膜として
のシリコン酸化膜、33は開口部、34はシリコン薄膜
、35は保護膜、36はエネルギービーム、37は欠落
部を示している。By the way, when forming a semiconductor single crystal layer for forming an upper layer element using an energy beam, crystal growth is performed using the lower semiconductor substrate as a crystal growth seed through an opening in an interlayer insulating film. However, in the conventional sample structure as shown in Figure 3(a), the thermal conductivity of the semiconductor substrate exposed through the opening is significantly different from that of the insulating film, so it is difficult to melt the semiconductor layer with an energy beam. In this case, the temperature distribution at the shoulder portion of the interlayer insulating film becomes significantly non-uniform. For this reason, there is a problem in that the semiconductor layer contracts at the shoulder portion, resulting in a missing portion as shown in FIG. 3(1)). In FIG. 3, 31 is a single crystal silicon substrate, 32 is a silicon oxide film as an interlayer insulating film, 33 is an opening, 34 is a silicon thin film, 35 is a protective film, 36 is an energy beam, and 37 is a missing part. ing.
本発明は上記事情を考慮してなされたもので、その目的
とするところは、ビームアニール時における半導体薄膜
の収縮を少なくすることができ、絶縁膜上に欠落部の発
生等のない半導体単結晶層を容易に作成することのでき
る半導体薄膜結晶層の製造方法を提供することにある。The present invention has been made in consideration of the above circumstances, and its purpose is to reduce the shrinkage of a semiconductor thin film during beam annealing, and to reduce the shrinkage of a semiconductor single crystal without the occurrence of missing parts on an insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor thin film crystal layer, which allows the layer to be easily created.
本発明の骨子は、ビームアニール時に半導体薄膜の温度
分布が不均一となる部分の膜厚を他の部分よりも厚く形
成することにより、半導体薄膜の収縮を低減することに
ある。The gist of the present invention is to reduce shrinkage of the semiconductor thin film by forming a portion of the semiconductor thin film where the temperature distribution is non-uniform during beam annealing to be thicker than other portions.
即ち本発明は、半導体基板上にストライプ状の開口部が
設けられた絶縁膜を形成したのち、上記開口部及び絶縁
膜上に多結晶若しくは非晶質の半導体薄膜を形成し、次
いでこの半導体薄膜上でエネルギービームを走査して該
半導体薄膜を溶融・再結晶化する半導体薄膜結晶層の製
造方法において、前記半導体薄膜の膜厚を前記開口部及
びその周辺部の方が他の部分よりも厚くなるよう形成す
るようにした方法である。That is, in the present invention, an insulating film having striped openings is formed on a semiconductor substrate, a polycrystalline or amorphous semiconductor thin film is formed on the openings and the insulating film, and then this semiconductor thin film is In the method for manufacturing a semiconductor thin film crystal layer, the semiconductor thin film is melted and recrystallized by scanning an energy beam on the semiconductor thin film, the semiconductor thin film being thicker in the opening and its surrounding area than in other parts. This is a method that allows the formation of
本発明によれば、開口部と層間絶縁膜の平坦部との境界
上の半導体薄膜が厚く形成されているので、エネルギー
ビームにより半導体薄膜を溶融した際、温度分布が不均
一な場合でも半導体薄膜の収縮が発生し難くなる。□こ
のため、欠落部のない半導体薄膜結晶層を得ることが容
易となる。According to the present invention, since the semiconductor thin film on the boundary between the opening and the flat part of the interlayer insulating film is formed thickly, when the semiconductor thin film is melted by an energy beam, even if the temperature distribution is uneven, the semiconductor thin film shrinkage is less likely to occur. □For this reason, it becomes easy to obtain a semiconductor thin film crystal layer without any missing portions.
以下、本発明の詳細を図示の実施例によって説明する。 Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第1図(a)〜(C)は本発明の一実施例方法に係わる
シリコン単結晶層の製造工程を示す断面図である。FIGS. 1A to 1C are cross-sectional views showing the manufacturing process of a silicon single crystal layer according to an embodiment of the present invention.
まず、第1図(a)に示す如く、面方位(100)の単
結晶シリコン基板(半導体基板)11上にCVD法等に
より厚さ1.3[μTrL]のシリコン酸化膜(絶縁膜
)12を形成し、このシリコン酸化膜12に底部幅2[
μm]のストライプ状の開口部13を形成する。この開
口部13は、結晶成長のシードとして作用するもので、
開口上側が広がるテーパ形状を持つものとした。First, as shown in FIG. 1(a), a silicon oxide film (insulating film) 12 with a thickness of 1.3 [μTrL] is deposited on a single crystal silicon substrate (semiconductor substrate) 11 with a plane orientation of (100) by CVD or the like. is formed, and this silicon oxide film 12 has a bottom width of 2 [
[mu]m] stripe-shaped openings 13 are formed. This opening 13 acts as a seed for crystal growth,
It has a tapered shape where the upper side of the opening widens.
次いで、第1図(b)に示す如く、全面に多結晶シリコ
ン膜(半導体薄膜)14を堆積し、このシリコン膜14
の膜厚を次のようにした。即ち、シリコン酸化1112
上の膜厚の薄い部分で0.6Cμm〕、シリコン酸化s
!12上の膜厚の厚い部分で1[μm]とした。また、
ストライプ状の開口部13からビーム走査方向の前方の
多結晶シリコン膜14の厚くなっている部分の開口部1
3からの距離が30[μm1以上となるように形成した
。Next, as shown in FIG. 1(b), a polycrystalline silicon film (semiconductor thin film) 14 is deposited on the entire surface, and this silicon film 14
The film thickness was set as follows. That is, silicon oxide 1112
0.6 Cμm in the thin part of the upper film], silicon oxide s
! The thick part of the film on No. 12 was set to 1 [μm]. Also,
Opening 1 in the thicker part of the polycrystalline silicon film 14 in front of the striped opening 13 in the beam scanning direction
It was formed so that the distance from No. 3 was 30 μm or more.
なお、上記多結晶シリコン膜14の形成方法としては、
例えば、全面に厚さ0.6[μ7FL]の多結晶シリコ
ン膜をCVD法等で堆積したのち、膜厚を厚くすべき部
分にリフトオフ法等により、更に厚さ0.4[μm]の
多結晶シリコン膜を選択的に形成すればよい。また、全
面にCVD法等に6一
より厚さ1[μ7rL]の多結晶シリコン膜を堆積した
のち、膜厚を厚くすべき部分以外を0.4Lμmコ程度
エツチングするようにしてもよい。Note that the method for forming the polycrystalline silicon film 14 is as follows:
For example, after depositing a polycrystalline silicon film with a thickness of 0.6 [μ7FL] on the entire surface by CVD method, etc., a polycrystalline silicon film with a thickness of 0.4 [μm] is deposited on the areas where the film should be thickened by lift-off method, etc. A crystalline silicon film may be selectively formed. Alternatively, after depositing a polycrystalline silicon film with a thickness of 1 [μ7rL] over the entire surface by CVD or the like, etching is performed by about 0.4Lμm in areas other than those where the film thickness should be increased.
次いで、第1図(C)に示す如く多結晶シリコン膜14
上に厚さ0.5[μTrL]のシリコン酸化膜(保護膜
)15を形成する。この試料を、疑似線状電子ビーム1
6の走査によりアニールし、多結晶シリコン膜14を溶
融・再結晶化して単結晶化した。ここで、疑似線状電子
ビームとは、微小スポット径の電子ビームを一方向に高
速偏向することにより得られる等制約な線状ビームのこ
とである。そして、この疑似線状電子ビームを上記高速
偏向方向とは直交する方向に走査することにより、比較
的大きな幅を帯状にビームアニールできることになる。Next, as shown in FIG. 1(C), a polycrystalline silicon film 14 is formed.
A silicon oxide film (protective film) 15 having a thickness of 0.5 [μTrL] is formed thereon. This sample was exposed to the pseudo linear electron beam 1
6, the polycrystalline silicon film 14 was melted and recrystallized to form a single crystal. Here, the pseudo-linear electron beam refers to a uniformly constrained linear beam obtained by deflecting an electron beam with a minute spot diameter in one direction at high speed. By scanning this pseudo-linear electron beam in a direction perpendicular to the high-speed deflection direction, it is possible to perform beam annealing over a relatively large width in the form of a band.
かくして得られた単結晶シリコン層は、シリコン膜の収
縮に起因する欠落部の発生も見られず、−、良好な結晶
特性を示した。また、第2図に示す如−1:≧、ストラ
イプ状開口部13からビーム走査方向の前方の多結晶シ
リコン膜14の他の部分よりも膜厚が厚い部分のビーム
走査方向でのストライプ状開口部13までの距離をXと
し、この距離Xを10、’20.30[μm]として3
つの試料を作成し、これらをそれぞれビームアニールに
より単結晶化し、欠落部発生状況について調べたところ
次のような結果が得られた。The single-crystal silicon layer thus obtained exhibited good crystal properties, with no cracks caused by shrinkage of the silicon film. In addition, as shown in FIG. 2, -1: ≧, a striped opening in the beam scanning direction in a part of the polycrystalline silicon film 14 that is thicker than other parts of the polycrystalline silicon film 14 in front of the striped opening 13 in the beam scanning direction. Let the distance to part 13 be X, and this distance X be 10, '20.30 [μm], 3
Two samples were prepared, each of which was made into a single crystal by beam annealing, and the occurrence of missing portions was investigated, and the following results were obtained.
即ち、上記距離Xが10[μynlの場合においては、
従来問題となったシリコン膜の10[μ風口]程度の欠
落部は、ストライプ状開口部13の100[μTrL]
当り2〜3箇所の割合で発生していた。また、距離Xが
20[μTrL]では欠落部の発生率は1〜2箇所とな
り、距離Xが30[μ7FL]では欠落部の発生は殆ど
見られなかった。That is, when the distance X is 10 [μynl,
The lack of about 10 [μTrL] of the silicon film, which has been a problem in the past, is due to the 100 [μTrL] of the striped opening 13.
This occurred in 2 to 3 locations per day. Further, when the distance X was 20 [μTrL], the occurrence rate of missing parts was 1 to 2 places, and when the distance X was 30 [μ7FL], almost no missing parts were observed.
つまり、多結晶シリコン膜14の膜厚を厚くすべき部分
のストライプ状開口部13からの距離Xを30[μ′r
rL]以上としておくことにより、欠落部の発生を防止
できることが判る。In other words, the distance
rL] or more, it is understood that the occurrence of missing portions can be prevented.
このように本実施例方法によれば、シリコン酸化膜12
の開口部13及びこの開口部13近傍の多結晶シリコン
膜14を他の部分よりも厚く形成しているので、電子ビ
ームを用いてビームアニールする際のシリコン膜14の
温度分布不均一に起因する収縮を少なくすることができ
、欠落部の発生を防止することができる。このため、シ
リコン酸化1!12上に良質のシリコン単結晶層を形成
することができ、3次元IC等の製造等に極めて有効で
ある。In this way, according to the method of this embodiment, the silicon oxide film 12
Since the opening 13 and the polycrystalline silicon film 14 near this opening 13 are formed thicker than other parts, this is caused by uneven temperature distribution of the silicon film 14 during beam annealing using an electron beam. Shrinkage can be reduced and the occurrence of missing parts can be prevented. Therefore, a high-quality silicon single crystal layer can be formed on silicon oxide 1!12, which is extremely effective for manufacturing three-dimensional ICs and the like.
なお、本発明は上述した実施例方法に限定されるもので
はない。例えば、前記半導体薄膜の他の部分よりも厚く
する部分の開口部からの距離Xは、半導体薄膜の厚さ及
び開口部の大きさ等の条件に応じて適宜定めればよい。Note that the present invention is not limited to the method of the embodiment described above. For example, the distance X from the opening of a portion of the semiconductor thin film that is made thicker than other portions may be determined as appropriate depending on conditions such as the thickness of the semiconductor thin film and the size of the opening.
さらに、上記距離Xはストライプ状開口部の両側で同じ
にする必要はなく、ビーム走査方向の前方で前記欠落部
の発生を抑制できるに十分な長さとし、ビーム走査方向
の後方ではこれより短いものであってもよい。Furthermore, the above-mentioned distance It may be.
また、前記エネルギービームは電子ビームに限るもので
はなく、レーザビームを用いることもできる。また、ビ
ームアニールすべき半導体薄膜としては、多結晶シリコ
ンの代りに非晶質シリコンを用いることができ、さらに
他の半導体を用いることも可能である。また、絶縁膜の
膜厚、ストライプ状開口部の形状及び大きさ等の条件は
、仕様に応じて適宜変更可能である。その他、本発明の
要旨を逸脱しない範囲で、種々変形して実施することが
できる。Further, the energy beam is not limited to an electron beam, and a laser beam may also be used. Further, as the semiconductor thin film to be beam-annealed, amorphous silicon can be used instead of polycrystalline silicon, and it is also possible to use other semiconductors. Further, conditions such as the thickness of the insulating film, the shape and size of the striped openings, etc. can be changed as appropriate depending on the specifications. In addition, various modifications can be made without departing from the gist of the present invention.
第1図(a)〜(C)は本発明の一実施例方法に係わる
シリコン単結晶層の製造工程を示す断面、□口、第2図
は上記実施例方法の作用を説明するための模式図、第3
図(a)(b)は従来の問題点を説明するための工程断
面図である。
11・・・単結晶シリコン基板(半導体基板)、12・
・・シリコン酸化I!(絶縁Ml)、13・・・開口部
、14・・・多結晶シリコン膜(半導体薄膜)、15・
・・シリコン酸化膜(保護膜)、16・・・電子ビーム
(エネルギービーム)。FIGS. 1(a) to (C) are cross sections showing the manufacturing process of a silicon single crystal layer according to an embodiment method of the present invention, and FIG. 2 is a schematic diagram for explaining the operation of the above embodiment method. Figure, 3rd
Figures (a) and (b) are process cross-sectional views for explaining conventional problems. 11... Single crystal silicon substrate (semiconductor substrate), 12.
...Silicon oxidation I! (insulating Ml), 13... opening, 14... polycrystalline silicon film (semiconductor thin film), 15...
...Silicon oxide film (protective film), 16...Electron beam (energy beam).
Claims (4)
た絶縁膜を形成する工程と、上記開口部及び絶縁膜上に
多結晶若しくは非晶質の半導体薄膜を形成し、且つこの
半導体薄膜の膜厚を上記開口部及びその周辺部の方が他
の部分よりも厚くなるように形成する工程と、上記半導
体薄膜上でエネルギービームを走査して該半導体薄膜を
溶融・再結晶化する工程とを含むことを特徴とする半導
体薄膜結晶層の製造方法。(1) Forming an insulating film with striped openings on a semiconductor substrate, forming a polycrystalline or amorphous semiconductor thin film on the openings and the insulating film, and a step of forming a film so that the opening and its surroundings are thicker than other parts; and a step of scanning an energy beam on the semiconductor thin film to melt and recrystallize the semiconductor thin film. A method for manufacturing a semiconductor thin film crystal layer, comprising:
膜の他の部分より膜厚が厚くなつている部分のビーム走
査方向での距離が、ストライプ状開口部からビーム走査
方向の前方の方がビーム走査方向の後方より長い構造で
あることを特徴とする特許請求の範囲第1項記載の半導
体薄膜結晶層の製造方法。(2) The distance in the beam scanning direction from the striped opening to the parts of the semiconductor thin film on both sides that are thicker than the other parts is such that the distance from the striped opening to the front in the beam scanning direction is 2. The method of manufacturing a semiconductor thin film crystal layer according to claim 1, wherein the structure is longer than the rear in the scanning direction.
レーザビームを用いたことを特徴とする特許請求の範囲
第1項記載の半導体薄膜結晶層の製造方法。(3) The method for manufacturing a semiconductor thin film crystal layer according to claim 1, wherein an electron beam or a laser beam is used as the energy beam.
絶縁膜としてシリコン酸化膜、前記半導体薄膜として多
結晶シリコン膜或いは非晶質シリコン膜を用いたことを
特徴とする特許請求の範囲第1項記載の半導体薄膜結晶
層の製造方法。(4) A single crystal silicon substrate is used as the semiconductor substrate, a silicon oxide film is used as the insulating film, and a polycrystalline silicon film or an amorphous silicon film is used as the semiconductor thin film. A method for manufacturing a semiconductor thin film crystal layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61031791A JP2569402B2 (en) | 1986-02-18 | 1986-02-18 | Manufacturing method of semiconductor thin film crystal layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61031791A JP2569402B2 (en) | 1986-02-18 | 1986-02-18 | Manufacturing method of semiconductor thin film crystal layer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62190715A true JPS62190715A (en) | 1987-08-20 |
JP2569402B2 JP2569402B2 (en) | 1997-01-08 |
Family
ID=12340890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61031791A Expired - Lifetime JP2569402B2 (en) | 1986-02-18 | 1986-02-18 | Manufacturing method of semiconductor thin film crystal layer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2569402B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5893220A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Preparation of semiconductor single crystal film |
-
1986
- 1986-02-18 JP JP61031791A patent/JP2569402B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5893220A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Preparation of semiconductor single crystal film |
Also Published As
Publication number | Publication date |
---|---|
JP2569402B2 (en) | 1997-01-08 |
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Legal Events
Date | Code | Title | Description |
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EXPY | Cancellation because of completion of term |