JPS62186375A - Picture pattern data expanding device - Google Patents

Abstract

PURPOSE:To miniaturize a character generator and to attain the high picture quality of print or display by converting a picture pattern original data into a picture pattern expansion data whose oblique line quantized noise is improved without deteriorating the picture resolution. CONSTITUTION:The titled device consists of a picture pattern generator 100, a reference pattern segmentation circuit 200, an expanded data generating circuit 300, an output buffer memory 400 and a read/write control circuit 500. The pattern generator 100 uses a 3X3 register 200 to read a reference pattern data PPM, the logic circuit 300 applies the operation to generate the expanded data EPM, which is stored tentatively in the buffer memory 400. The control circuit 500 controls the data flow and the components and outputs as required the picture pattern expansion data to an output interface for a printer or the like from the buffer memory 400. Then the picture pattern original data is doubled in lateral direction in the lateral double angle mode, doubled in longitudinal direction in the longitudinal double angle mode and doubled in both the longitudinal and lateral directions in the full double angle mode for the purpose of output.

Description

Detailed Description of the Invention ■Field of the Invention The present invention relates to recording and displaying of image patterns in which figures, characters, symbols, etc. (hereinafter referred to as characters) are represented by a two-dimensional distribution of pixels with image components and pixels without image components. 5 used for etc.
Image component presence/absence data with a bit number corresponding to the number of pixels constituting the image pattern (hereinafter referred to as image pattern original data) is converted to image component presence/absence data with a larger (for example, double or quadruple) bit number (hereinafter referred to as image pattern original data). The present invention relates to a single image pattern data expansion device that converts (expands) this into image pattern expansion data (referred to as image pattern expansion data).

■Conventional technology For example, in some types of word processors, characters are divided into 24 horizontal x 24 vertical pixels with and without image components (
The pixels with acid content in the following image are black pixels.

24X per character to represent an image pattern consisting of pixels without image components (pixels without image components are called white pixels)
The 24-bit image pattern original data is stored in a pattern memory for the required number of characters, and the image pattern original data corresponding to the key-in character is read out from the memory in response to the operator's key operation and applied to the CRT display unit, or It is given to a dot printer to display and print out an image pattern corresponding to the key-in character.

In this type of word processor, in order to emphasize the title characters of sentences being written or edited, a 48 x 24
Compatible with an image pattern of pixels (meaning 48 pixels horizontally x 24 pixels vertically; the same applies hereinafter), corresponding to an image pattern of 24 x 48 pixels with twice the number of pixels in the vertical direction, or,
It is now possible to create image pattern extension data that corresponds to an image pattern of 48 x 48 pixels, which doubles the number of pixels in the horizontal direction and the number of pixels in the vertical direction.
In the following, an image pattern expressed by image pattern original data will be referred to as an original image pattern, and an image pattern expressed by image pattern extension data will be referred to as an extended image pattern).

For example, in the pattern memory k, the image pattern original data corresponding to each character is stored in the first line and the first bit (data corresponding to the leftmost pixel of the pixels lined up in the first row of the image pattern).

1st line 2nd bit, ..., 1st line 24th bit (data corresponding to the rightmost pixel), 2nd line 1st bit
Bit, ..., 24th line, 24th bit, etc. are stored in order, and each bit is read out in this order (actually, the order is the same as this). is stored as one to several bytes of data, and is often converted from parallel to serial when read out).The creation of the image pattern extension data can be explained as follows.

Thumb, each bit of the image pattern original data corresponding to the specified character is consecutively
48 x 24 bits (48 bits horizontally x 24 bits vertically, the same applies below) image pattern expansion data is created by reading out the character twice in the horizontal direction; Each line of the original image pattern data corresponding to the character is read out twice for each line, and the character is read out twice in the vertical direction.
Create 24x48-bit expanded image pattern data that has been enlarged twice; Alternatively, each bit of the original image pattern data corresponding to the specified character is read twice in succession, and this! The multiple readings are repeated twice for each line to create 43x48-bit image pattern expansion data in which the character is expanded twice in the horizontal direction and twice in the vertical direction.

See Figure 5a. This figure shows an image pattern in which the character "ei" is quantized by allocating 24 x 24 pixels per character. For example, the pattern memory contains
The black pixel of this image pattern is t 1 n, and the white pixel is 0'
'' is stored. Therefore, the image pattern original data corresponding to the character "ei" is read out from the pattern memory, and the area corresponding to one pixel (
If a dot (hereinafter referred to as one dot) is printed out using a square printer, an original image pattern as shown in Figure 5a will be obtained (however, the dot of a general printer is much smaller than this, and if it is circular ).

By the way, the image pattern original data corresponding to the character "ei" in this pattern memory is read twice in succession for each bit, for example k as shown above, and this repeated reading is repeated twice for each line. When the 48×48 bit image pattern expansion data created by the above process is printed out using the same printer, an expanded image pattern as shown in FIG. 5b is obtained. Comparing the original image pattern shown in FIG. 5a and the extended image pattern shown in FIG. 5b, it is true that the extended image pattern "Ei" shown in FIG. 5B is different from the original image pattern "Ei" shown in FIG. 5A. 2
Although it is twice the size (linear ratio), it is limited to simply assigning 2 pixels horizontally x 2 pixels vertically to 1 bit of the image pattern original data and printing the same image pattern original data. Even if each dot 1~ is printed out using a square printer that is four times the size (area ratio) of the printer that printed out the image pattern shown in FIG. 5a, the expanded image shown in FIG. 5b will still be obtained. An original image pattern identical to the pattern is obtained (for this reason, Fig. 5b is replaced with Fig. 5a).
(referred to as the simple 2x enlarged image of the figure). In other words, the appearance is 1 above.
This is equivalent to enlarging the dot twice in the vertical and horizontal directions, and the quantization noise of the original image pattern is also enlarged, resulting in an image that is difficult to see with noticeable roughness in curves and diagonal lines.

Similarly, Figure 6a is an image pattern obtained by quantizing horizontal, vertical, and diagonal lines (the diagonal lines are rotated by 45 degrees and 135 degrees counterclockwise from the horizontal line, and the same is true for lines 2 and below) using 24 x 24 pixels. , FIG. 6b is a simple double magnification image of FIG. 6a. Moreover, FIG. 7a is an image pattern obtained by quantizing the symbol rOJ with 24×24 pixels h, and FIG. 7b is a simple double enlarged image of FIG. 7a. The same drawbacks as those described above can be pointed out by referring to any of these drawings. Furthermore, although this drawback is not shown in the figure, it can be pointed out similarly for extended image patterns in which only the horizontal direction is doubled in the number of pixels, or only in the vertical direction is converted to twice the number of pixels. .

In other words, the conversion of the number of pixels as seen in the above simple double enlarged image does not improve the resolution even though the number of pixels per image pattern increases, and is only meaningful in enlarging the size of the image. Ah, and it has nothing to do with improving image resolution by increasing pixel density.

Therefore, for example, in a facsimile, 8
It would be meaningless for the receiving side to expand the image data read at 7mm (dots per millimeter) to 4 times the number of bits on the receiving side and reproduce it using a 16dot, 7mm recording device. In this case, the data of 1 dot read at 1/8 mm is expanded to 2 x 2 bits, and 1
Even if the dots are printed using a 1/16 mm printer, the size is not converted, so the pixel density is converted, but the apparent size of one dot in the resulting image pattern is the same).

As a solution to these problems, an apparatus has been proposed that further smoothes the simple double-enlarged image. In this process, image pattern expansion data corresponding to a simple double enlarged image is first created from the image pattern original data, and a two-dimensional arrangement of black bits (black pixels: corresponding to pixels with image components) of this data is created. , and interpolates the missing black bits in the detected sequence to create image pattern expansion data. To put it simply, processing is performed to supplement discontinuous parts in the arrangement of black pixels in a simple double-enlarged image. Therefore, the level of the diagonal quantization noise is lowered by one dot,
Regarding diagonal lines, quantization noise of image pattern extension data is improved.

However, interpolation using black pixels is also performed at the intersections of vertical lines and horizontal lines (usually there are many such intersections in kanji), so the resolution of the image in these areas deteriorates. The problem is that you end up doing it. Further, since smoothing processing for interpolating black bits is performed after processing the data as image pattern extension data corresponding to a -transparent or a simple double enlarged image, there is a problem that additional processing time is required.

■Purpose of the Invention The object of the present invention is to provide an image pattern data expansion device that converts original image pattern data into image pattern expansion data with improved diagonal line quantization noise without deteriorating the resolution of one image. do.

■Structure of the invention In order to achieve the above object, in the present invention.

Image pattern data memory means storing image pattern data representing image patterns such as figures, characters, symbols, etc.
, bit data corresponding to the pixel of interest to be converted, and bit data corresponding to each of at least eight pixels adjacent to the pixel of interest in the image pattern are used as reference patterns to sequentially update the pixel of interest. Image pattern data reading means for sequentially reading out bit data corresponding to the pixel of interest; at least bits corresponding to an extended pattern having a total of 4 pixels, 2 pixels parallel to the set reference line x 2 pixels perpendicular to the reference line. Extended data generation means for expanding data, the two-dimensional arrangement of bit data corresponding to pixels with image components in the reference pattern with respect to the set reference line, at least an arrangement corresponding to a 45 degree declination angle;
A sequence corresponding to a declination angle of 135 degrees, a sequence corresponding to an intermediate declination angle between a declination angle of 0 degrees and a declination angle of 45 degrees, and an intermediate declination angle between a declination angle of 45 degrees and a declination angle of 90 degrees. The sequence corresponding to .

A sequence corresponding to an intermediate declination angle between a declination angle of 90 degrees and a declination angle of 135 degrees, a sequence corresponding to an intermediate declination angle between a declination angle of 135 degrees and a declination angle of 180 degrees, and other deviations. Extended data generating means for discriminating seven types of alignments corresponding to corners, and extracting at least one column of extended data of bit data corresponding to an expanded pattern of pixel arrays with and without image components according to the discriminated alignments; and extended data memory means for storing the extended data.

The gist of the invention described above will be further explained in detail with reference to specific examples.

The image pattern is composed of two-dimensionally distributed black pixels and white pixels, and is nothing but a quantized character (two figures, symbols, etc.), which is a combination of straight lines and curved lines, using these pixels. The straight lines and curved lines that make up a character have a direction, and the directional component can be expressed as k, horizontal (=O') component (1), as shown in Figure 8, for example.
-1').

45° component (3-3'), vertical (=90°) component (55
') h35° component (7-7') and horizontal component and 45
00 to 45° component (2-2') in the middle of ' component, 4
45° to 90° component (4-
4'), 90° to 13 between the vertical component and the 135° component
5° component (6-6'), 135° to 180° component (8-8') between the 135° component and the horizontal component.

Classify into.

Figures 9a to 9Q are patterns in which the above eight components are quantized using three black pixels (the mouth represents a black pixel). The pattern shown in Fig. 9a is the horizontal component, and the pattern shown in Fig. 9b or 9c is Oa~4.
The pattern shown in Figure 9d is the 45' component.
The pattern shown in Figure 9e or Figure 9f is 45°~9
The pattern shown in Fig. 9g is the vertical component, and the pattern shown in Fig. 9h or 91 is the 0° component.
The pattern shown in Figure 9j is a 135° component, and the pattern shown in Figure 9 or 9Ω is a 135' component.
~180° components are shown, respectively.

By the way, among the patterns shown in Figures 9a to 9Q, except for the patterns in which horizontal and vertical components are quantized (that is, the patterns shown in Figures 9a and 9g), the arrangement in that direction is not dense. Therefore, parts that are forced to be black pixels during quantization or forced white pixels (in this case, the background)
The part that was said to be.

It has so-called quantization noise.

Figure 10a is identical to the pattern shown in Figure 9b (black pixels are shown with solid lines, white pixels relevant to the explanation are shown with dashed lines; other white pixels are the background), but each pixel of this pattern is If each can be divided into four parts, it would be smoother to represent it as shown in Figure 10b.

That is, quantization noise is improved. This is 0°~4
It can be considered that the black pixels protruding to the upper side of the quantization pattern of the 5° component are deleted, and the black pixels are added to the lower side. That is, when expanding the bit data corresponding to each pixel of the pattern as shown in FIG. 10a to bit data corresponding to 2×2 pixels, the bit data corresponding to the black pixel bO is expanded to the white pixel, The bit data corresponding to white pixels wO is quantized by expanding the bit data k in which the lower row and lower cloth are black pixels, and the bit data k in which Shonin and Joko are black pixels, and the lower row and lower cloth are white pixels, respectively. Noise can be improved (
For bit data corresponding to other pixels, the same type 2
2 or less (same as bit data corresponding to X2 pixels).

Although FIG. 10c is the same as the pattern shown in FIG. 9d, if each pixel constituting this pattern can be divided into four, the representation as shown in FIG. 10d will be smoother. This can be considered as removing the black pixels that protrude above the quantized pattern of the 45' component and adding the black pixels below. That is, when expanding bit data corresponding to each pixel of the pattern as shown in FIG. 10c to bit data corresponding to 2×2 pixels, black pixels b1,
For the bit data corresponding to b2 and b3, the bit data k has the jonin as a white pixel, and the upper cloth, lower row, and lower cloth as black pixels, and for the bit data corresponding to white pixels W1 and W2, the jonin as a black pixel, respectively. Quantization noise can be improved by expanding bit data k in which the upper cloth, lower row, and lower cloth are white WJM.

Although FIG. 10a is the same as the pattern shown in FIG. 9e, if each pixel constituting this pattern can be divided into four, it will be smoother if it is represented as shown in FIG. 10f. This removes the black pixels that protrude above the quantized pattern of the 45'' to 90° components.

This amount can be regarded as being replenished on the lower side.

That is, when expanding the bit data corresponding to each pixel of the pattern as shown in FIG. For the bit data corresponding to the white pixel w3, the bit data k has black pixels in the lower row, and the bit data k has black pixels in the upper and lower rows, and white pixels in the upper and lower rows. It can be improved.

FIG. 10g is the same as the pattern shown in FIG. 9h, but if each pixel constituting this pattern can be divided into four, the representation as shown in FIG. 10h will be smoother. This can be considered as removing the black pixels that protrude above the 90' to 135° component quantization pattern and adding the black pixels below. That is, the bit data corresponding to each pixel of the pattern as shown in FIG. 10g is
When expanding data to Pi1, which supports 2 pixels,
For the bit data corresponding to black pixel b5, the bit data k has the earth and stone and the lower cloth as white pixels, and the upper and lower rows as black pixels, and for the bit data corresponding to white pixel W4, the earth and stone and the lower cloth have black pixels and the upper row. Quantization noise can be improved by expanding the bit data k in which the lower and lower pixels are white pixels.

Although FIG. 10i is the same as the pattern shown in FIG. 9j, if each pixel constituting this pattern can be divided into four, the representation as shown in FIG. 10j will be smoother. This can be considered as removing the black pixels that protrude above the quantized pattern of the 45° component and adding the black pixels below. That is, when expanding bit data corresponding to each pixel of the pattern as shown in FIG. 10i to bit data corresponding to 2×2 pixels, black pixels b6,
For bit data corresponding to b7 and b8, the earth and stone are white pixels, and the top water, bottom row, and bottom cloth are black pixels, respectively.Bit data k corresponding to white pixels W5 and w6, respectively, are earth and stone black pixels, Quantization noise can be improved by expanding the bit data k in which the top row, bottom row, and bottom row are white pixels.

The tenth figure is the same as the pattern shown in the ninth figure, but if each pixel constituting this pattern can be divided into four, it would be smoother to represent it as shown in the tenth ohm diagram. This can be considered as removing the black pixels that protrude above the quantization pattern of the 135° to 180° components and adding the black pixels below. That is, tenthly, the bit data corresponding to each pixel of the pattern as shown in the figure is divided into two parts.
When expanding to bit data corresponding to X2 pixels.

For the bit data corresponding to black pixel b9, the upper row and the earth and stones are white pixels, and for the bit data k that corresponds to the lower row and lower cloth, the upper row and earth and stones are black pixels, and for the bit data corresponding to white pixel w7, the upper row and earth and stones are black pixels, and the lower row and lower cloth are black pixels. Quantization noise can be improved by expanding the bit data k in which the base pixel is a white pixel.

Thumb h, k as above, 0° ~ 45° component, 45° component, 45' ~ 90'' component, 90' ~ 135' component,
In the quantization pattern of the 135' component or the 135° to 180@component, the corners of the black pixels that protrude upward are removed, and the depressions at the bottom are filled in to improve quantization noise.

On the other hand, the above is inverse k, 0''~456 component, 45' component, 45'~90'' component, 90e~135' component, 1
Quantization pattern of 35'' component or 135° to 180' component.

Quantization noise can be similarly improved by cutting the corners of black pixels that protrude downward and filling in the recesses on the upper side.

Fig. ha shows the same pattern as shown in Fig. 9c, but when expanding the bit data corresponding to each pixel constituting this pattern to bit data corresponding to 2 x 2 pixels, the black pixel blo For the corresponding bit data, the lower row and lower cloth are white pixels, and the upper row and earth and stones are black pixels, and for the bit data corresponding to the white pixel wlO, the lower row and lower cloth are black pixels, and the upper row and earth and stone are black pixels. Bit data k, where is a white pixel, are expanded respectively,
Extended data corresponding to the pattern shown in FIG. fib is created.

FIG. hc is the same pattern as shown in FIG. 9d, but when expanding the bit data corresponding to each pixel constituting this pattern to bit data corresponding to 2×2 pixels, the black pixels bll, b12 and b1
Regarding the bit data corresponding to 3, bit data k where the bottom cloth is a white pixel, the top water, the bottom row, and the bottom cloth are black pixels, respectively.
, the bit data corresponding to white pixels wll and w12 are expanded to bit data k, where the bottom pixel is a black pixel, and the top, top, and bottom pixels are white pixels, respectively, and the hth pixel is expanded.
Create extended data corresponding to the pattern shown in Figure d.

Figure 1ie is the same as the pattern shown in Figure 9f, but when expanding the bit data corresponding to each pixel constituting this pattern to bit data corresponding to 2x2 pixels, For bit data k that corresponds to the white pixel w13, the upper cloth and lower cloth are white pixels, the upper row and lower cloth are black pixels, and the upper cloth and lower cloth are black pixels, and the upper row and lower cloth are white. Each pixel bit data k is expanded to h-th
Create extended data corresponding to the pattern shown in figure f.

Figure hg is identical to the pattern shown in Figure 91, but
The bit data corresponding to each pixel that makes up this pattern is
When expanding to bit data corresponding to 2×2 pixels, the bit data corresponding to black pixel b15 is the bit data k corresponding to white pixel w14, where the upper row and lower cloth are white pixels, and the upper cloth and lower cloth are black pixels. As for the bit data, the upper row and lower row are black pixels, the upper row and lower row are white pixels, bit data k is extended, and the hh-th
Create extended data corresponding to the pattern shown in the figure.

do.

Figure hi is identical to the pattern shown in Figure 9j, but
The bit data corresponding to each pixel that makes up this pattern is
When expanding to bit data corresponding to 2×2 pixels, the bit data corresponding to black pixels b16, b17 and b18 are converted to bit data k, white, with white pixel for Genin, black pixel for upper row, upper row, and lower cloth, respectively. pixel w
The bit data corresponding to No. 15 and W16 is expanded to bit data k, which uses black pixels for Genin and white pixels for Josui 2 upper right and lower cloth, respectively, to create extended data corresponding to the pattern shown in Figure hj. do.

Figure h is identical to the pattern shown in Figure 9i, but
The bit data corresponding to each pixel that makes up this pattern is
When expanding to bit data corresponding to 2×2 pixels, the bit data corresponding to black pixel b19 is bit data k, white pixel w17, where the lower row and upper cloth are white pixels, the upper row and upper cloth are black pixels. For the corresponding bit data, expand the bit data k in which the lower row and upper cloth are black pixels, the upper row and upper cloth are white pixels, and obtain the hΩth
Create extended data corresponding to the pattern shown in the figure.

Kono et al., Oa ~ 45° component, 45' component, 45'
For the quantization pattern of ~90' component, 90'~135'' component, 135'' component, or 135m~180° component, remove the corners of black pixels that protrude to the right, fill in the dents on the left, or The quantization noise can also be improved in the same manner as described above by cutting the corners of the black pixels that protrude from the top and filling the dents on the right side. There is no essential difference between these methods except for the criteria for determining protrusions and depressions of black pixels in the quantization pattern. Therefore, in a preferred embodiment of the present invention, 0''~45@component, 4
5' component, 45a-90' component.

90″~135m component, 135″ component *r: C, 1
In the quantization pattern of the 35' to 180a components, the corners of the black pixels that protrude upward are removed, and the depressions at the bottom are filled in to improve the quantization noise.

By the way, in the preferred embodiment, each pixel of the original image pattern is focused on (pixel of interest), and the pixel of interest and eight pixels surrounding it are extracted as a reference pattern, and the pixel of interest is one of the pixels mentioned above. (bo~b9.wo~w7)
Alternatively, it is expanded by determining whether it corresponds to another pixel.

As shown in Figure th, the original image pattern data is scanned with a 3x37 trix register to extract the reference pattern data PPM, and the data of interest (corresponding to the pixel of interest) is extracted according to the contents of bit data a to j. data) is extended to extended data EPM consisting of four bit data j*kem and n corresponding to 2×2 pixels.

This will be explained in detail with reference to FIGS. 12a to 15h.

In addition, in FIGS. 12a to 15h, b is black data (
(bit data corresponding to black pixels) +w is white data (bit data corresponding to white pixels), b or W surrounded by an O mark is data of interest, blank is arbitrary data (black data or white data)
shall be.

The data of interest in the reference pattern data PPM shown in FIG. 12a is considered to correspond to at least the black pixel b3 of the pattern shown in FIG. 10c, and the data of interest in the reference pattern data PPM shown in FIG. 12b is
It is considered that this corresponds to at least the black pixel b1 of the pattern shown in FIG. 10c. Therefore, when the extracted reference pattern data PPM matches FIG. 12a and/or FIG. 12b, extended data EPM is set in which the upper row is white data and the other rows are black data, as shown in FIG. 12c.

Among the reference pattern data PPM that matches FIG. 12b, if the upper right of the data of interest is white data and the right neighbor of the data of interest is black data, as shown in FIG. 12d, then the data of interest at this time is Since it corresponds to the black pixel bo in the pattern shown in FIG. 10a, k as shown in FIG. 12e
, and the extended data EPM with the older data as white data.

Of the reference pattern data PPM that matches FIG. 12a, if the lower left of the data of interest is white data and the data directly below the data of interest is black data, as shown in FIG. 12f, the data of interest at this time is Since it corresponds to black pixel b4 in the pattern shown in Figure 10e, k as shown in Figure 12g
, and further assume that the table below is extended data E P M as white data.

The data of interest in the reference pattern data PPM shown in FIG. 13a is considered to correspond to at least the black pixel b8 of the pattern shown in FIG. 10i.

Furthermore, it is considered that the data of interest in the reference pattern data PPM shown in FIG. 13b corresponds to at least the black pixel b6 of the pattern shown in FIG. 10i. Therefore, the extracted reference pattern data PPM are shown in FIG.
Or, when it matches FIG. 13b, as shown in FIG. 13c, k is extended data EPM in which the old and old data are white data and the other data are black data.

Of the reference pattern data PPM that matches Fig. 13a, if the lower right of the data of interest is white data and the data directly below the data of interest is black data, as shown in Fig. 13d, then the data of interest at this time is Since it corresponds to black pixel b5 in the pattern shown in FIG. 10g, k
, and the extended data EPM in which the lower cloth is white data.

Of the reference pattern data PPM that matches FIG. 13b, if the upper left of the data of interest is white data and the left neighbor of the data of interest is black data, as shown in FIG. 13f, the data of interest at this time is 10th, since it corresponds to black pixel b9 in the pattern shown in the figure, k as shown in Figure 13g.
, and the upper row is expanded data EPM with white data.

In the reference pattern data PPM shown in FIG. 14a, the data of interest is considered to correspond to at least the white pixel w2 of the pattern shown in FIG. 10c, and
The data of interest in the reference pattern data PPM shown in FIG. 10e is considered to correspond to at least the white pixel wl of the pattern shown in FIG. This is considered to correspond to the white pixel w1 or w2 of the pattern. Therefore, when the extracted reference pattern data PPM matches FIG. 14a, FIG. 14b, and/or FIG. 14c, k as shown in FIG. 14d,
Extended data E where the top row is black data and the other rows are white data
PM.

Of the reference pattern data PPM that matches FIG. 14b, if the upper right of the data of interest is black data and the right neighbor of the data of interest is white data, as shown in FIG. 14e, the data of interest at this time is Since it corresponds to the white pixel wO of the pattern shown in FIG. 10a, k
, furthermore, the extended data EPM is made with the older data as black data.

Of the reference pattern data PPM that matches FIG. 14a, if the lower left of the data of interest is black data and the data directly below the data of interest is white data, as shown in FIG. 14g, then the data of interest at this time is Since it corresponds to white pixel w3 in the pattern shown in Figure 108, k as shown in Figure 14h
, and further assume that the table below is extended data EPM with black data.

The data of interest in the reference pattern data PPM shown in FIG. 15a is considered to correspond to at least the white pixel w6 of the pattern shown in FIG. 10j, and the data of interest in the reference pattern data PPM shown in FIG. 15b is
It is considered that this corresponds to at least the white pixel W5 of the pattern shown in FIG. 10j, and in the reference pattern data PPM shown in FIG. 15c, the data of interest is at least the 10j
It is considered that this corresponds to the white pixel w5 or W6 of the pattern shown in the figure. Therefore, the extracted reference pattern data P
PM is shown in Figures 15a, 15b and/or 15c.
When it matches the figure, k is extended data EPM in which black data is set for the upper cloth and white data is set for the other parts, as shown in Fig. 15d.

Of the reference pattern data PPM that matches FIG. 15a, if the lower right of the data of interest is black data and the data directly below the data of interest is white data, as shown in FIG. 158, then the data of interest at this time is Since it corresponds to the white pixel w4 in the pattern shown in Figure 10g, k
, furthermore, the extended data EPM is made with the older data as black data.

Of the reference pattern data PPM that matches FIG. 15b, if the upper left of the noted data is black data and the left neighbor of the noted data is white data, as shown in FIG. 15g, the noted data at this time is 10th corresponds to the white pixel W7 in the pattern shown in the figure, so as shown in Fig. 15h,
, and the upper row is extended data EPM with black data.

Please refer now to Figure 16a (the mouth shows a black pixel lf! and the background shows a white pixel). A pattern like this in Figure 16a is often seen in the decoration of letters, but black pixel b20
If we pay attention to, the reference pattern data PPM matches the pattern shown in FIG. 12d, so if we extend the data corresponding to b20 to the extended data shown in FIG. PPM is the first
Since it matches the pattern shown in Figure 3f, the data corresponding to b21 is extended to the extended data shown in Figure 13g. As a result, the pattern shown in FIG. 16a becomes the pattern shown in FIG. 16b, 1 for example, the decoration of letters is crushed. Therefore, when the reference pattern data PPM matches the pattern shown in FIG. 13f, the data of interest is extended to the extended data shown in FIG. 13g, and k
, the upper row and upper cloth of the extended data based on the data of interest immediately before (that is, the bit data corresponding to the adjacent pixel on the left) are corrected to black data. In other words, the extended data corresponding to h, b20 in Fig. 16a becomes as shown in Fig. 12e, but the upper row and upper cloth data of the extended data corresponding to h, b20 are corrected by the extended data corresponding to b21, so As shown in FIG. 16c, an extended image pattern is obtained in which bit data j'''' and j'' are added. Therefore, for example, quantization noise in decorative parts of characters is improved.

Based on the above, the patterns shown in Figures 12a, 12b, 14d, and 12f are replaced by the patterns shown in Figures 13a, 13b, 14d, and 13f. The 14th pattern is given priority over the pattern shown in
Figure a, Figure 14b.

15a, 15b, 15c, 158.
The created truth tables are shown in Figures 2d and 2e.
2f and 2g. In this, a
, b, c, d#f+grhr1 is reference pattern data P
The PM bit data (see Figure 1h) is h, j, k,
m.

n is the bit data of the extended data EPM corresponding to the current data of interest (■) (see Figure 1h). This is bit data of the upper row and top cloth of the extended data EPM.

Also, here It I h is black data, IJ Ogg
indicates white data.

First, FIGS. 2d and 2e are truth tables when the data of interest (2) is black data. This is h, j-+ k
-, jt k, m, and n, the following logical expressions ("・" indicates logical product, h 10g indicates logical sum, and underline indicates negation, respectively) are obtained.

j-=ni=earth・Σ・c−d−f−g・i+earth・1・c
-clf・g・i−上上=Supreme y−earth・d・work・work・i +earth・upper・μ・d・work・g−work, ± 10work・−b−・C, d−work・gh-1+a-b-C-
d-g +a-b-c-d, -(2)↓
= Yu-in y-earth, d, work, g-work, ±+ earth, ↓, earth, d
・Work・gh−1 + 地°上上L°工゛工°i +a−b−c−d−f−g +a−b−c−f ・・・ (
3) Construction = earth, top, c-d△■, h...(
4) n= a-b-c-fh-i
-(5) Figures 2f and 2g are truth tables when the data of interest ○ is white data. From this -jtk
, m, and n, the following logical formula (the meanings of the symbols are the same as above) is obtained.

j= a・b−d+a−b−clf−h−i+a
-b-c-d-f +a-b-earth, d-f-t, 10a, b-c-d, eng, top... (6) k=
E, b-e, f+b-c-d, engineering, g, h+ a-b-
c-d-f +a-b-earth・d-f-1・h +a-b・and・d-f-g tena-b-c-d-f-h・i +a・b-c-d −f−g−X・± −(7)m=
b・earth・d・work・g-upper ... (8)n
= a-b-d-Lh-i ・=
(9) When the data of interest ○ is black data, calculate the expansion data EP by calculating the above equations (1) 2 to (5) according to each bit data a-1 of the reference pattern data PPM.
Find J−yk− of each bit data J r k+ m*n of M and the extended data EPM of the previous data of interest, and when the data of interest O is white data, perform the above (6) 2~
It is sufficient to calculate each bit data 3 t k+ m+ n of the extended data EPM by calculating equation (9).

Next, the present invention will be explained in detail.

FIG. 1a shows an image pattern data expansion device according to an embodiment of the present invention. Referring to FIG. 1a, this apparatus is broadly divided into an image pattern generator 100, a reference pattern cutting circuit 200. Extension data generation circuit 300. Output buffer memory 400 and read/write control circuit 500
It is composed of A block diagram showing a simplified data flow of this device is shown in FIG. 3a. In this case, the pattern generator 100 is the pattern generator 100k shown in FIG. 1a, the 3X3 register (matrix register) 200 is the reference pattern extraction circuit 200k shown in FIG. to the extended data generation circuit 300 shown.

The buffer memory 400 corresponds to the output buffer memory 400k shown in FIG. 1a, and the controller 500 corresponds to the read/write control circuit 500k shown in FIG. 1a. In other words, the reference pattern data PPM is extracted from the pattern generator 100 by the 3×3 register 200, and the logic circuit 300 performs the calculations of equations (1) to (9) above to create extended data EPM. Buffer memory 400
Temporarily closed. Controller 500 controls the data flow and these components, and outputs image pattern extension data from buffer memory 400 to an output interface to a printer or the like as necessary.

To briefly explain the operation of the device shown in FIG. 1a, the microprocessor (CPU) of the read/write control circuit 500
In response to a character designation signal from an input device such as a keyboard (not shown), a host processor of a base unit, or a text memory connected to 18, the original image pattern data is input in the original mode, and the original image pattern data is input in the horizontal double-angle mode. Image pattern expansion data expanded twice in the direction.

In double-height mode, the original image pattern data is expanded twice in the vertical direction, and in full-width mode, the original image pattern data is expanded twice in both the vertical and horizontal directions. , dot printer, bit memory (page memory), facsimile, computer, or other output device or information processing device.

The image pattern generator 100 generates the required number of characters.
Original image pattern data of 24×24 bits per character is stored. in fact.

Each image pattern original data stored in this image pattern generator 100 has a linear form, but here, for convenience of explanation, the image pattern original data (ODP) is expressed as 24×24 horizontally as shown in FIG. 24 bit bit data is 2
Dimensionally lined up, it is 1 as shown in Figure 1j.
It is assumed that 24 lines (horizontal arrangement) of 3-byte data are stored. Therefore, in the following, any byte in any line of the image pattern original data ODP corresponding to the specified character will be referred to as the 1st theta byte, and for example, the 2nd byte of the 3rd line will be referred to as the 32nd byte. do. Further, each image pattern original data ODP is designated by a character address from the CPU 18 of the read/write control circuit 500, and each line of the designated image pattern original data ODP is designated by a line address from the CPU 18.

Reading is performed for each line specified by the line address, and the read data (line data) is given to the data selector 15 of the reference pattern cutting circuit 200.

In the original mode, the data selector 15 immediately transfers the received line data to the multiplexer 16 of the extended data generation circuit 300, but in other modes (double-width mode, double-height mode, or full-double-angle mode), the line data is Parallel in/serial out shift register (below).

(referred to as P/S register) 2. This P/S register 2 includes 8-bit P/S registers 21 and 2, respectively.
2 and 23 series connection, total 24 bits (
(3 bytes) P/S register.

The data selector 15 sets the first byte of the received line data to 21k, the second
Distribute 22k bytes and 23k third bytes, respectively.

The line data stored in the P/S register 2 is transferred to the next stage shift register 5 as serial 24-bit data.

The shift register 5 includes a shift register 51 . of 8 bits from the beginning. Similarly, the 8-bit shift register 52 and the 9-bit shift register 53 are connected in series to form a total of 25-bit shift register.As will be described later, after one line of data has been input, dummy data is stored in the 25th bit. Enter (white data 20). register 5
is at least the first register 5! 1st bit, 2nd bit
A serial-in/parallel-out shift register (hereinafter referred to as S/P) that can output bits and the third bit in parallel.
It is called a register).

Regarding shift register 4 and shift register 3,
It has exactly the same configuration as shift register 5, and these shift registers 3, 4.5 are connected in series to form a 25 x 3 bit shift register as a whole, and all are synchronized with register 2. energized to shift. Therefore, the bit data of the same bit number stored in each shift register 3, 4.5 is shifted by one line, and the bit data stored in shift register 4 is stored in shift register 3. The data is read out one line after the current bit data.
The bit data stored in the shift register 5 is data read out one line after the bit data stored in the shift register 4. That is, the first bit of each shift register 3, 4 and 5,
S/P that outputs the 2nd and 3rd bits in parallel
The registers can constitute the aforementioned 3x3 matrix register.

This will be explained in detail with reference to Figure 1g.
Bit data (data of interest) corresponding to the pixel of interest is stored in the second bit of the shift register 4 (41), and the first
Bit data d corresponding to the pixel adjacent to the left of the pixel of interest is stored in the bit, and bit data f corresponding to the pixel adjacent to the right of the pixel of interest is stored in the third bit.

Each bit data stored in the shift register 3 is
Since the data is exactly one line before each bit data stored in the shift register 4, the first bit of the shift register 3 (31) contains the bit data a corresponding to the upper left pixel of the pixel of interest. The second bit stores bit data b corresponding to the pixel directly above the pixel of interest, and the third bit stores bit data C corresponding to the pixel on the upper right of the pixel of interest.

Each bit data stored in the shift register 5 is
Since the data is exactly one line after each bit data stored in the shift register 4, the first bit of the shift register 5 (51) contains the bit data g corresponding to the lower left pixel of the pixel of interest. The second bit contains bit data h corresponding to the pixel immediately below the pixel of interest, and the third bit contains bit data i corresponding to the pixel immediately below the pixel of interest.
are stored respectively.

Therefore, reference pattern data PPM having a two-dimensional arrangement as shown in FIG. 1h is extracted. The reference pattern data PPM is provided to the information distribution pattern detection circuit 6 of the extended data generation circuit 300.

The information distribution pattern detection circuit 6 has a k
, black data expansion circuit 61. It is composed of a white data expansion circuit 62, a selection delay circuit 63, and the like.

The black data expansion circuit 61 converts the bit data of the reference pattern data PPM as be Cy d+ f+ g+
The above-mentioned equations (1) and (2) are determined by h and i.

The bit data J-y k-s j' (subscript tr 1r
r indicates that it is valid when the data of interest 0 is black data, exactly rr 1 , 2 or less), k'', m'
and output nl.

The white data expansion circuit 62 uses the bit data a, b, c, dy, ft gy h, and i of the reference pattern data PPM to satisfy the above-mentioned equations (6) and (7).

Compute equations (8) and (9) to obtain bit data j
0 (the subscript II OrT indicates that it is valid when the data of interest ■ is white data, that is, h0 I+; 2 or less are the same)'k' r m' and no are output.

The selection delay circuit 63 selects the black data extension circuit 61 outputs jL, k"2m1 and n1° or the white data extension circuit 62 outputs j', m', and no in accordance with the data of interest 0. As described above, the data expansion circuit 61 extracts bit data j belonging to the previous expansion data.
In order to output - and -, each selected bit data is delayed by one data of interest and corrected by the bit data j- and -.

It is output as 1+m- and n- to the extended data J-+ of the previous data of interest.

Details of the black data expansion circuit 61 are shown in FIG. 2a.

Referring to FIG. 2a, black data expansion circuit 61 includes AND gates ANI, AN2 . AN3. AN4゜AN5. A
N6. AN7. AN8. AN9. ANlo, OR Gate OR1, Noah Gate NOR1.

N0R2, and inverters INI and IN2 constitute a 7-person AND gate having five inverting input terminals and two non-inverting input terminals. The first term and the second term (second) are the following calculations: 1, tate, and d, k, k, i rT (the meanings of the symbols are the same for 2 and below as described above). Each of the five inverting input terminals of h, ANl is connected to the input line of bit data a, b, c, f, and g, and each of the two non-inverting input terminals of ANI is connected to the input line of bit data d and i. connected to the input line.

AN2 is an 8-person AND gate having six inverting input terminals and two non-inverting input terminals, in which the above-mentioned (1) second term, (2) Daito second term, and ( 3
) The 1st term of the fire brother, pa tanjo y-mutual, d-work, g-e, ±
In other words, each of the six inverting input terminals of h and AN2 receives bit data a and b.

It is connected to the input lines of c, f, h, and i, and each of the two non-inverting input terminals of AN2 is connected to the input line of bit data d and g.

AN3 is an 8-person gate having four inverting input terminals and four non-inverting input terminals, in which the above-mentioned (1) 3rd term, (2) 3rd term, and ( 3
) Daito 2 terms.

The following operations are performed: up, ↓, ±, d, engineering, g-h-i '''.In other words, each of the four inverting input terminals of h and AN3 is connected to the input line of bit data a, beC, and f. , AN3 are connected to input lines of bit data dy gr h and i, respectively.

In OR gate ○R1, Ant game) - AN1 output, A
Compute the logical sum of the N2 output and the AN3 output. In other words, AND gate ANI, AN2. The calculation of the above-mentioned equation (1) is performed in AN3 and OR gate ○R1, and - is obtained in bit data j-+.

AN4 is a five-person gate having four inverting input terminals and one non-inverting input terminal, and in this, the above-mentioned (2) Valor 4 term, 1・-b-・, , d
, gH are performed. Each of the four inverting input terminals of h and AN4 receives bit data at b.

The non-inverting input terminal of AN4 is connected to the input line of bit data g.

AN5 is a four-person AND gate having three inverting input terminals and one non-inverting input terminal, and is the above-mentioned item (2) Daito 5.

The operations II a, l, , c, d II are performed. Each of the three inverting input terminals of AN5 is connected to the input line of bit data a, b, and d, and the non-inverting input terminal of AN5 is connected to the input line of bit data C.

In NOR gate N0R1, AND gate ANI output, A
Computes the logical sum of the N2 output, AN3 output, AN4 output, and AN5 output. In other words, and gate ANI,
AN2. AN3. AN4゜AN5 and Noah Gate N0
In R1, the negation operation of the above-mentioned equation (2) is performed to obtain bit data j1.

AN6 is a six-person AND gate having five inverting input terminals and one non-inverting input terminal, in which the above-mentioned (3) large cylinder three terms, a-b-c-1.l -1
In other words, each of the five inverting input terminals of h and AN6 has bit data at b.

It is connected to the input lines of c, f, and g, and the non-inverting input terminal of AN6 is connected to the input line of bit data i.

AN7 is a six-person gate having four inverting input terminals and two non-inverting input terminals, and is the above-mentioned item (3) Valor 4.

The following calculation is performed: "a""' d-f-g u. In other words, each of the four inverting input terminals of h and AN7 receives bit data a and b.

The two non-inverting input terminals of AN7 are connected to the input lines of bit data f and g, respectively.

AN8 is a four-person AND gate having three inverting input terminals and one non-inverting input terminal, in which the above-mentioned (3) Daito term 5, "a-b-c-f
” is performed. In other words, each of the four inverting input terminals of h, AN8 is connected to the input line of bit data b, c, and f, and the non-inverting input terminal of AN8 is connected to the input line of bit data a. It is connected.

The NOR gate N0R2 calculates the logical sum of the AND gates A N 2 output, AN 3 output, AN 6 output, AN 7 output, and AN 8 output. In other words, AND GATE AN
2. AN3. AN6. The NOT operation of the above-mentioned equation (3) is performed in AN7°A N8 and NOR gate N0R2, and 1 is obtained in the bit data.

AN9 is a six-person AND gate having four inverting input terminals and two non-inverting input terminals, and in this, the above-mentioned equation (4), h” is performed. Each of the four inverting input terminals of h and AN9 receives bit data at brd and g.
The two non-inverting input terminals of AN9 are connected to the input lines of bit data C and h, respectively.

The output of this AND gate AN9 is inverted by an inverter INVl and becomes bit data m1.

ANIO is a six-person AND gate with four inverting input terminals and two non-inverting input terminals, in which:
The following calculation, which is the above-mentioned equation (5), is performed. Tsume h
, ANIO each have bit data b, c.

f and i input lines, and each of the two non-inverting input terminals of ANIO receives bit data a and h
connected to the input line.

This AND gate ANIO output is the inverter INV2
is inverted to become bit data n1.

Details of the white data expansion circuit 62 are shown in FIG. 2b.

Referring to FIG. 2b, white data expansion circuit 62 includes AND gates ANI1. ANI 2. ANI 3. ANI
4. ANI5. ANI6. ANI7. ANI8゜ANI
9. AN20. AN21. AN22. AN23, AN2
4. And, it is constituted by OR gates OR2 and ○R3.

ANII is a three-person gate with one inverting input terminal and two non-inverting input terminals.

In this regard, it is the above-mentioned item (6) Valor 1.

An operation "a-b-d" is performed. In other words, the inverting input terminal of h, ANII is connected to the input line of bit data a, and ANll
Each of the two non-inverting input terminals of
and d are connected to the input lines.

ANI2 is a six-person AND gate with three inverting input terminals and three non-inverting input terminals, in which:
The above-mentioned (6) large cylinder 2 term, a-b-d-f・h-
1'' is performed. That is, h, each of the three inverting input terminals of ANI2 is connected to the input line of bit data d, h, and i, and each of the three non-inverting input terminals of ANI2 is connected to the input line of bit data d, h, and i. Connected to input lines a, b and f.

ANI3 is a five-person AND gate with two inverting input terminals and three non-inverting input terminals, in which:
The third term of the above-mentioned equation (6) is “a・b−c−d−
An operation f'' is performed. In other words, h, each of the two inverting input terminals of ANI3 is connected to the input line of bit data C and f, and each of the three non-inverting input terminals of ANI3 is connected to the input line of bit data a.

Connected to the b and d input lines.

ANI4 is a seven-person gate with three inverting input terminals and four non-inverting input terminals.

In this, it is the above-mentioned (6) large cylinder item 4.

The following calculation is performed: ``a-b-t, t3-fgh''. In other words, each of the three inverting input terminals of ANI4 is connected to the input line of bit data Ctg and h, and each of the four non-inverting input terminals of ANI4 is connected to the input line of bit data a, b, d, and f. It is connected to the.

ANI5 is a six-person AND gate with two inverting input terminals and four non-inverting input terminals, in which:
A-b, c-d-g-, which is the above-mentioned item (6) Daito 5.
An operation Σ'' is performed. That is, each of the two inverting input terminals of ANI5 is connected to the input line of bit data g and h, and each of the four non-inverting input terminals of ANI5 is connected to the input line of bit data a.

Connected to the b, c and d input lines.

In OR gate OR2, AND gate AN1.1 output,
AN12 output, AN13 output, A, N14 output and A
Compute the logical OR of the N15 output. In other words, and gate A
NI 1. ANI 2. ANI 3゜ANI 4. AN
I 5 and orgate Q, the above-mentioned (6) in R2
) is performed to obtain bit data j0.

ANI6 is a four-person AND gate with two inverting input terminals and two non-inverting input terminals, in which:
This is the above-mentioned item (7) large cylinder item 1.

1'a-b-d-f'' is performed.That is, the two inverting input terminals of ANI6 are connected to the input lines of bit data a and d, and the two non-inverting input terminals of ANI6 are connected to the input lines of bit data a and d. are connected to input lines of bit data b and f, respectively.

ANI7 is a six-person AND gate having three inverting input terminals and three non-inverting input terminals, in which:
The above-mentioned (7) second term of the large cylinder, the calculation "b-c-clf-to-present" is performed. In other words, each of the three inverting input terminals of ANI7 is connected to the input line of bit data fig and h, and each of the three non-inverting input terminals of ANI7 is connected to the input line of bit data b, c, and d. 9AN18 is a five-person AND gate with two inverting input terminals and three non-inverting input terminals.

In this case, the third term of the above-mentioned equation (7) is “
a-b-c-cLf'' is performed.In other words, h, each of the two inverting input terminals of ANI8 is connected to the input line of bit data C and d, and each of the three non-inverting input terminals of ANI8 is connected to the input line of bit data C and d. is bit data a.

Connected to the b and f input lines.

ANI9 is a seven-person AND gate with two inverting input terminals and five non-inverting input terminals, in which:
This is the fourth term of the above-mentioned equation (7).

The following calculation is performed: a-b-c-d-f-1 h''.In other words, h, the two inverting input terminals of ANI9 are connected to the input lines of bit data C and g, and the five input terminals of ANI9 are connected to the input lines of bit data C and g. Each of the non-inverting input terminals has bit data a.

Connected to the b, d, f and h input lines.

AN20 is a six-person AND gate having one inverting input terminal and five non-inverting input terminals, in which:
This is Section 5 of the above-mentioned (7) large cylinder.

The calculation 1'a-b-1-df-gTt is performed. In other words, the inverting input terminal of AN20 is connected to the input line of bit data C, and the AN20
Each of the five non-inverting input terminals of
, b, d, f and g input lines.

AN21 is a seven-person AND gate having three inverting input terminals and four non-inverting input terminals, in which:
'a-b-c-d-f, which is the 6th term of the above-mentioned (7) large cylinder.
-h-1'' is performed.That is, h, each of the three inverting input terminals of AN21 is connected to the input line of bit data d, h, and i, and each of the four non-inverting input terminals of AN21 is connected to the input line of bit data d, h, and i. , are connected to the input lines of bit data a, b, c and f.

AN22 is an eight-person AND gate with two inverting input terminals and six non-inverting input terminals.

In this case, the seventh term of the above-mentioned equation (7), "a-
b-c-d-f-g-1-up'' is performed.In other words, h, the two inverting input terminals of AN22 are connected to the input lines of bit data h and i, and the five input terminals of AN22 are Each of the non-inverting input terminals has bit data a.

Connected to input lines b, c, d, f and g.

In OR gate OR3, AND gate AN 16 output,
AN17 output, AN18 output, AN19 output, AN20
The logical sum of the output, AN21 output, and AN22 output is calculated. In other words, AND gate AN16. AN17. AN1
8. ANI9. AN20°AN21. The above-mentioned equation (7) is calculated in AN22 and OR gate ○R3, and 0 is obtained in the pit data.

AN23 is a six-person AND gate having three inverting input terminals and three non-inverting input terminals, in which:
This is the above-mentioned equation (8).

hb,...・df・gh'' is performed.In other words, h, the three inverting input terminals of AN23 are connected to the input lines of bit data c, f, and h, and the three inverting input terminals of AN23 are connected to the input lines of bit data c, f, and h. Each of the non-inverting input terminals is connected to an input line for bit data b, d, and g.

The AN23 output becomes bit data m0.

AN24 is a six-person AND gate having three inverting input terminals and three non-inverting input terminals, in which:
The calculation a-b-d-f-h-1'', which is the above-mentioned equation (9), is performed.In other words, h, each of the three inverting input terminals of AN24 is connected to the bit data a, d, and h. Each of the three non-inverting input terminals of AN24 is connected to the input line of bit data b, f, and j.

The AN24 output becomes bit data n0.

Details of the selection delay circuit 63 are shown in FIG. 2C. Referring to FIG. 2b, the selection delay circuit 63 includes an AND gate AN3
1, AN32. AN33. AN34゜AN35. AN
36. AN37. AN38. AN39, ORGATE OR
31,0R32,0R33゜0R34,0R35,OR
36 and a delay circuit DLY.

AN31. AN32. AN33. AN34 and AN3
5 is a two-person AND gate having two non-inverting input terminals, AN36. AN37. AN38 and AN39
are two-person gates each having one inverting and one non-inverting input terminal.

ANDGATE AN31. AN32. AN33゜AN34
and one non-inverting input terminal of AN35, and AND gate AN36. AN37. AN38 and AN39
The inverting input terminal of is connected to the input line of the data of interest @.

Thumb, when the pixel of interest is a black pixel, the data of interest O is rr
1, g, so the AND gate AN31. AN3
2, AN33. AN34 and AN35 are on.

ANDGATE AN36. AN37. AN38 and AN
39 is off h, and when the pixel of interest is a white pixel, the data of interest O becomes II 071, so the AND gate AN31
．． AN32. AN33. AN34 and AN35 are off, and gate AN36. AN37, AN38 and A
N39 turns on.

The other non-inverting input terminal of the AND gate AN32 is the NOR gate NoR1 output terminal k of the black data expansion circuit 61, and the other non-inverting input terminal of the AND gate AN33 is the NOR gate NoR2 output terminal k of the black data expansion circuit 61. The other non-inverting input terminal is the inverter INVI output terminal k of the black data expansion circuit 61, and the other non-inverting input terminal of the AND gate AN35 is the black data expansion circuit 6.
Since the inverter INV2 output terminal k of No. 1 is connected to each other, when the data of interest ■ is "1" (when it is black data), the OR gates 0R31, 0R32, OR
33 and 0R34, the bit data j1. to 1
．． ml and nl are applied to delay circuit DLY.

The non-inverting input terminal of the AND gate AN36 is the OR gate OR2 output terminal k of the white data expansion circuit 62, the non-inverting input terminal of the AND gate AN37 is the OR gate OR3 output terminal k of the white data expansion circuit 62, and the non-inverting input of the AND gate AN38. The terminal is the AND gate AN23 output terminal k of the white data expansion circuit 62, and the non-inverting input terminal of the AND gate AN39 is the AND gate AN2 of the white data expansion circuit 62.
Since the four output terminals k are connected to each other, when the data of interest ■ is it O'' (when it is white data), it is output to the bit data j' through OR gates ○R31, ○R32, 0R33 and 0R34. ', m' and no are given to the delay circuit DLY.

Delay circuit DLY is a D-flip-flop array h and is activated in synchronization with shift registers 2, 3, 4, and 5. Therefore, the DLY output becomes extended data (corresponding to the pixel to the left of the pixel of interest in the original image pattern) of the previous data of interest.

On the other hand, the OR gate ORI output terminal of the black data expansion circuit 61 is connected to another non-inverting input terminal of the AND gate AN31, and the AN31 has the data of interest rr.
I When II (when it is black data), it turns on h, bit data j'''', - OR gate 0R35 and 0
Give to R36. As a result, the OR gates 0R35 and 0R36 correct the output of the delay circuit DLY.

In this way, the information distribution pattern detection circuit 6 calculates the above-mentioned equations (1) to (9) using each bit data of the reference pattern data PPM, and calculates the previous data of interest. (Thumb h, corresponding to the pixel to the left of the pixel of interest in the original image pattern), extended data j-, ni-ichi, m- and n-
generate.

The output of the information distribution pattern detection circuit 6, that is, the extended data J-+ "9m" and n- are 4-bit parallel data, but the bit data j- is a 4-bit S/P register (serial in/parallel Out shift register) 7 and 8-bit S/P register h, bit data - to 4-bit S/P register 8, bit data m
- is given to 4-bit S/P register 9 and 8-bit S/P register 12, and bit data n- is given to 4-bit S/P register 10, respectively. S/P register7.
8,9,10,h. and 12 are shifted and activated by the same shift pulse, respectively, and the extended data j +, l
Each parallel output of c-, m-, n- is shifted one bit to the left.

In S/P registers 7 and 8, the first bit of register 7 (the stored bit data is j+; the following is synonymous) output is the first bit input k of latch 13, and the first bit of register 8 (kl). ) output is the second bit input k of the latch 13, the second bit (j2) of the register 7, the output is the third bit input k of the latch 13, the second bit (j2 of the register 8)
kl) output is the 4th bit input k of latch I3,...
, etc. are alternately connected to the 8-bit latch 13. The latch 13 stores the first data (data corresponding to the pixel four positions before the pixel of interest at that time: data corresponding to the fourth pixel on the left) every time the expansion of the original data for four pixels is completed. ), the above data, soil and stone data,
Second data (also data corresponding to the previous three pixels)
The above data expanded from the above data, the earth and stone data, the third day, the above data expanded from Yu (also corresponding to the pixel two positions earlier), the earth and stone data, and the fourth data (also corresponding to the pixel one position earlier: This is because it is lined up with the above data, which is an expanded version of the data corresponding to the left-most pixel, and the rock and stone data.

The data of the upper line of extended data can be synthesized in the latch 13.

In S/P registers 9 and 10, the first bit (ml) output of register 9 is the first bit input k of latch 14, and the first bit (nl) output of register 10 is input to latch 1.
4 second bit input k, second bit of register 9 (m2
) output is the third bit input k of latch 14, register 10
The second bit (n2) output of the latch 14 is the fourth bit input k, .

They are alternately connected to the 8-bit latch 14 in this way. The latch 14 receives the first data (same as above) every time the expansion of the original data for 4 pixels is completed.
The lower table data, lower cloth data, the lower table data expanded from the second data (data corresponding to the three pixels in front), the lower cloth data, and the third data ( The table data below is an extension of the data corresponding to the pixel two pixels in front, the lower cloth data, and the fourth data (data corresponding to the pixel one pixel in front: data corresponding to the pixel on the left)
The data in the table below and the cloth data are expanded.

Therefore, the data of the lower line of the extended data can be synthesized in the latch 14.

Therefore, latches 13 and 14 are obtained by processing 4 bits (4 pixels of interest) of S/P registers 7, 8, 9, and 10. Data on the upper line of the extended data (4 pixels of interest x 4 pixels = 16 bits) that is latched and synthesized each time the extended data is input (contents of 13)
and the data on the lower line (the contents of 14) are output to the multiplexer 16.

S/P registers h and 12 were obtained by processing 8 bits (8 pixels of interest). Extended data (j+~J I
ll t m 1 to ms), the data on the upper line (contents of h) and the data on the lower line (1
2 contents) as parallel data to the multiplexer 16.
Output to.

In response to instructions from the CPU 18, the multiplexer 16 selects the original line data of the image pattern original data ODP from the data selector 15 in the original mode, and selects the upper line data of the extended data from the latch 13 in the horizontal double-angle mode. In the double-height mode, the parallel data in the S/P registers h and 12 are selected, and in the full-width mode, the data in the upper and lower lines of the magnification data from the latches 13 and 14 are selected.

The output buffer memory 400 consists of four 24x24 bit buffer memories I, n, III, mV (area).
, although it is not energized in the original mode.

In double-width mode, the upper line of the extended data from the latch 13 selected by the multiplexer 16 is sequentially buffered! and ■ to create horizontal double-width image pattern extension data, and in vertical double-width mode, the parallel data from the S/P register h selected by the multiplexer 16 is stored in the odd-numbered line k and from the S/P register 12. Parallel data is stored alternately with even numbered line k in buffers ■ and ■ to create double-height image pattern expansion data, and in full double-width mode, the upper line data of the expansion data from the latch 13 selected by the multiplexer 16 is stored. data of the lower line of the extended data from the latch 14 is alternately stored in the buffers I, n to the odd line k, and the data of the lower line of the extended data from the latch 14 to the even line k.

■, and ■ to create full double-width image pattern expansion data. Finally, the extended data is organized two-dimensionally in the output buffer memory 400.

Image pattern expansion data is being created.

In the following description, for convenience of explanation, it is assumed that the write area of the buffer memory 400 is specified byte by byte using a line number and a write byte address, similar to the ODP shown in FIG. 1j.

The CPU 18 of the read/write control circuit 500 is.

Each part is controlled as outlined above to create image pattern extension data from the image pattern original data ODP corresponding to the specified character. Note that the system controller 9 is a decoder that transfers read commands, data select commands, write commands, shift commands, etc. of the CPU 18 to each component, and the signal lines are not shown. The pulse generator 20 generates shift pulses and intermittently applies the shift pulses to each of the above registers in response to shift commands from the CPU via the system controller 19, but illustration of these signal lines is also omitted.

Counter 1 (21) is a 25-ary counter that counts shift pulses applied to shift registers 3, 4, and 5. Counter 2 (22) is S/P register 7.8,
9,10,h. It is an octal counter that counts the shift pulses applied to 1 and 12. It can also output a signal every 4 counts, and also serves as a quaternary counter.

The details of the control executed by the CPU 18 will be described below with reference to the flowcharts shown in FIGS. 1C, 1D, 1E, and IF. Note that the following explanation is based on the input device (
This subroutine is executed after a character is specified by the host processor (not shown).

In S1 (first step, S is omitted in the flowchart; see below), each register, counter, register, etc. is cleared (reset), and in S2, the character address corresponding to the designated character is sent to the image pattern generator. Set to 100.

If it is the original mode, the process proceeds from S3 to 84, where the image pattern original data ODP is read out as usual and transferred to the output device side.

Other than original mode (double height mode, double width mode,
In the full double-angle mode), the process proceeds to S5, where the parameter ■ corresponding to the line address mentioned above is set to 0k, the parameter K corresponding to the number of times the output buffer memory is heated is set to 0k, and the number of write lines (output buffer 7 memory 4) is set to 0k.
The parameter L corresponding to the write-in number (00) is set to 1, respectively.

In S6, the counter 21 is cleared (0), and in S7, the parameter I is incremented by 1 (■: 0→1).

Since the value of ■ is 1 (I<25), proceed from S8 to 89,
Here, set the parameter O indicating the byte number of the line to be read (designated line) to 1.

SIO issues a predetermined instruction to the image pattern generator 100 and data selector 15 to generate image pattern original data OD.
The h-th byte of P is stored in 21 of the P/S register 2.

After that, go to S12 from Sh, increase 20 by 1, and S1
Returning to 0, the 12th byte of ODP is stored in 22, and in the same loop, the 13th byte of ODP is stored in 23.

When the writing of the first ODP line to P/S register 2 is completed, the value of parameter θ is 3, so Sl
This loop is exited from l, but since the value of I is still 1 (I<2), the process advances to S14.

S14 is P/S register 2 and shift registers 3 and 4
．． In this step, 514-815-814-, 514-815-814-,
. . . The green return is executed in a loop of -815 until the value of the counter 21 reaches 25. In this loop, when the value of the counter 21 becomes 24, all the data of the first line of ODP written in the P/S register 2 is transferred to the shift register 5 (2nd bit to 25th bit), By running the ODP
The data on the first line of dummy data (0:
In other words, white pixels) are stored.

During this time, the information distribution pattern detection circuit 6 sequentially pays attention to the dummy data ("O") when cleared by Sl and outputs extended data, but since S/P registers 7 to 12 and below are not energized, the It is unrelated to the generation of pattern extension data.

Return to 86 from S15, clear counter 21, and proceed to S7
Increment the parameter ■ by 1.

As a result, the value of I becomes 2, but since I is less than 25,
In S9, set the parameter θ to 1 again and get 510-5l.
In a loop of 1-512-, . . . , -812, the second line of ODP is written to the P/S register 2 in the same manner as above.

Since I=2, again, 514-815-314-2
In a loop of -815, the data of the first line of ODP stored in the shift register 5 is transferred to the shift register 4k, and the data of the second line of ODP stored in the P/S register 2 is transferred. Shift register 5k data
, are transferred sequentially.

In this loop, when the value of the counter 21 reaches 24, the OD is applied to the 2nd to 25th bits of the shift register 4.
The data of the first line of P is stored in the first bit of the shift register 5, and the dummy data of the first line is stored in the first bit of the shift register 5.
The data of the second line of ODP is stored in the second bit to the twenty-fifth bit, respectively. In other words, the data (h) of the first bit of the first line of ODP is the data of interest. At this time, the first to twenty-fifth bits of shift register 3 and the second bit of shift register 4 are as follows.

Dummy data when cleared in Sl ("O
”) is stored, the reference pattern data PPM
First, it becomes as shown in the figure. It can be seen that the dummy data corresponds to background pixels (white pixels: therefore, the following dummy data are all 'O') outside the original image pattern.

Extended data obtained by focusing on ODP bit data h (
J, k, m, n) are input to the delay circuit DLY (see FIG. 2C).

After this, execute S14 and shift registers 2 to 5.
By shifting h by 1 bit, the data of the first line of ODP is changed to the 1st bit to the 24th bit k of the shift register 4, and the dummy data of the first line is changed to the 25th bit k, O.
The data of the second line of DP is stored in the 1st bit to the 24th bit k of the shift register 5, and the dummy data of the 2nd line is stored in the 25th bit k (the data of interest is 1□
become).

Returning to S6, the counter 21 is cleared (0), the number is incremented by 1 (2→3) in S7, and O is set to 1 in S9, 510-3l 1-512-.

..., -312, the data of the third line of k and ODP is written to the P/S register 2 in the same way as above.

This time, the value of parameter E is 3, so S1
3, proceed to S16. Output buffer memory 40 at S16
After setting the value of the write byte address φ of 0 to the value l indicating the start address, the counter 22 is cleared (to 0) in S17 (FIG. 1c).

The noteworthy data at this point is 12 (○DP 1st line 1st
bit data h), and the information distribution pattern detection circuit 6 corrects the extended data when paying attention to the bit data h (data immediately before: j +, 1, m).
-, n-: Hereinafter, this will be referred to as "extended data of r-bit data h"), so 81
At step 8, the S/P registers 7 to 12 are synchronously activated by one bit to take in the extended data of bit data h. At this point, the counter 22 is incremented by 1, so its value becomes 1.

S19 is the same step as step 814 described above, and when this is executed, the data of interest becomes 13, and the 1st bit data (31) of the 3rd line of the ODP is written to the 25th bit of the shift register 5. .

Here, the counter 21 is incremented by one count.

Its value will be 1.

The double height mode will be described later.

Since the value of the counter 22 is 1, the process returns to 318 from S21.

At 318, the S/P registers 7 to 12 are activated in 1-bit synchronization, and the information distribution pattern detection circuit 6 outputs the same. Take in the extension data of bit data 12. counter 22
has a value of 2.

When S19 is executed, the data of interest becomes 14h, and the 2nd bit data (32) of the 3rd line of ODP is written into the 25th bit of the shift register 5.

The value of the counter 21 becomes 2.

Return from S21 to 318h, set S/P registers 7 to 12 to 1
The information distribution pattern detection circuit 6 outputs the bit synchronized energization. Import the extended data of bit data 13.

The value of the counter 22 becomes 3.

When executing 319, the data of interest becomes 15.

The third line third bit data (33) of the ODP is written into the twenty-fifth bit of the shift register 5.

The value of the counter 21 becomes 3.

Return from S21 to 318h, set S/P registers 7 to 12 to 1
Extended data of the bit data 14 outputted by the information distribution pattern detection circuit 6 is loaded in bit synchronization.

As a result, the upper extended data obtained by extending the bit data h to 14 is placed in the latch 13, and the lower extended data obtained by extending the bit data h to 14 is prepared in the latch 14 (7
The connections between &8 and 13.9 &10 and 14 are as described above). Here, the counter 22 is incremented by 1, so its value becomes 4.

When 319 is executed, the data of interest becomes 16h, and the 4th bit data (34) of the 3rd line of ODP is written to the 25th bit of the shift register 5.

The value of the counter 21 becomes 4.

Since the value of the counter 22 has become 4, 322 is sent from S21.
Proceed to. Bit data h in latch 13 and latch 14
Since the extended data that expanded ~14 is available, S22
latches and energizes them.

In the full double-width mode, in S24, the upper 8 bits of parallel data of the extended data from the latch 13 are transferred to the first byte (of the first line ((2L-1) line: L=1) of the output buffer memory 400. φ=1), and the lower 8-bit parallel data from the latch 14 is written to the second line (second L line: L
=1) in the first byte (φ=1).

In case of double-width mode, in step 325, the upper 8-bit parallel data of the extended data from the latch 13 is transferred to the first line of the output buffer memory 400 (first line: L=
1) write to the first byte (φ=1).

Since the write pytos φ is incremented by 1 in S24 or S25, its value becomes 2.

In S26, when the parameter Ktl indicating the number of writes to the output sofa memory 400 is increased, its value becomes 1.
Therefore, the process returns from S27 to 317 (K≠6).

Thereafter, one or more repetitions will continue for a while, but since data import and write are complicated, a brief explanation will be provided.

Clear counter 22 in S17 and return 518-819-3
This becomes a loop of 20-S21-...-821.

Extension data of bit data 15 to 7-10.

Load 35 into the 25th bit of register 5. The noteworthy data is 17. The counter 21 is 5. The counter 22 becomes 1.

The extended data of bit data 16 is taken into bits 7 to 10, and 36 is taken into the 25th bit of register 5. The noteworthy data is 18
．． The counter 21 is 6. The counter 22 becomes 2.

The extended data of bit data 17 is taken into bits 7 to 10, and 37 is taken into the 25th bit of register 5. Featured data is 19
．． The counter 21 is 7. Counter 22 becomes 3.

The extended data of bit data 18 is taken into bits 7 to 10, and 38 is taken into the 25th bit of register 5. Featured data is ho
, the counter 21 is 8. The counter 22 becomes 4.

S l 8-319-520-821-...-82
Exit the loop of 1.

In the full double-width mode, upper extended data of bit data 15 to 18 is written to the second byte of the first line of the output buffer memory 400, and lower extended data is written to the second byte of the second line.

In the horizontal double-angle mode, the upper extended data of bit data 15 to 18 is transferred to the second line of the first line of the output sofa memory 400.
Write to byte.

The write byte address φ is 3k, and the parameter is 2.

Clear counter 22 and 518-319-320-8
This results in a loop of 21--...-821.

7 to 10 with 1g of bit data extension data.

Load 3g into the 25th bit of register 5. The noteworthy data is h1. The counter 21 is 9. The counter 22 becomes 1.

Extended data of bit data h0 from 7 to 10.

Load 310 into the 25th bit of register 5.

The data of interest is h□, and the counter 21 is 10. counter 22
becomes 2.

Extended data of bit data h1 from 7 to 10.

Load 3h into the 25th bit of register 5.

The noteworthy data is h3. The counter 21 is h. Counter 22 becomes 3.

Extended data of bit data h2 from 7 to 10.

Load 312 into the 25th bit of register 5.

The noteworthy data is h4. The counter 21 is 12. counter 22
becomes 4.

Exit the loop of 518-3I9-820-821-...-821.

In the full double-width mode, the upper extended data of bit data 19 to h2 is written to the third byte of the first line of the output sofa memory 400, and the lower extended data is written to the third byte of the second line.

In the horizontal double-angle mode, the upper extended data of bit data 1g to h2 is transferred to the first line 3 of the output sofa memory 400.
Write to byte.

The write byte address φ is 4k, and the parameter is 3.

Clear counter 22 and S l 8-319-320
This becomes a loop of -921-...-321.

The extended data of bit data h3 is taken into bits 7 to 10, and 313 is taken into the 25th bit of register 5.

The noteworthy data is h5. The counter 21 is 13. counter 22
becomes 1.

The extended data of bit data h4 is taken into bits 7 to 10, and 314 is taken into the 25th bit of register 5.

Featured data is 1 Sen6. The counter 21 is 14. counter 2
2 becomes 2.

Extended data of bit data h5 from 7 to 10.

Load 315 into the 25th bit of register 5.

The noteworthy data is h7. The counter 21 is 15. counter 22
becomes 3.

Extended data of bit data h6 from 7 to 10.

Load 316 into the 25th bit of register 5.

The noteworthy data is h8. The counter 21 is 16. counter 22
becomes 4.

S l 8-319-520-321-...-82
Exit the loop of 1.

In the full double-width mode, upper extended data of bit data h3 to h6 is written to the fourth byte of the first line of the output buffer memory 400, and lower extended data is written to the fourth byte of the second line.

In the horizontal double-angle mode, upper extended data of bit data h3 to h6 is written to the fourth byte of the first line of the output buffer memory 400.

The write byte address φ is 5k, and the parameter is 4.

Clear counter 22 and 518-819-920-3
This results in a loop of 21--321.

The extended data of bit data h7 is taken into bits 7 to 10, and 317 is taken into the 25th bit of register 5.

The noteworthy data is h9. The counter 21 is 17. Counter 2'2 becomes 1.

The extended data of bit data h8 is taken into bits 7 to 10, and 318 is taken into the 25th bit of register 5.

The data of interest is 12o, and the counter 21 is 18. counter 2
2 becomes 2.

The extended data of bit data h9 is taken into bits 7 to 10, and 319 is taken into the 25th bit of register 5.

The noteworthy data is 121. The counter 21 is 19. counter 2
2 becomes 3.

The extended data of bit data 120 is taken into bits 7 to 10, and 320 is taken into the 25th bit of register 5.

The noteworthy data is 122. The counter 21 is 20. counter 2
2 becomes 4.

Exit the loop of 518-319-320-321--821.

In the full double-width mode, the upper extended data of bit data h6 to h120 is written to the fifth byte of the first line of the output buffer memory 400, and the lower extended data is written to the fifth byte of the second line.

In the horizontal double-angle mode, the upper extended data of bit data h6 to h12G is transferred to the first line 5 of the output buffer memory 400.
Write to byte.

The write byte address φ is 6k, and the parameter is 5.

Clear counter 22 and 518-819-320-3
This results in a loop of 21--821.

The extended data of bit data 121 is taken into bits 7 to 10, and 321 is taken into the 25th bit of register 5.

The noteworthy data is 123. The counter 21 is 21. counter 2
2 becomes 1.

The extended data of bit data 122 is taken into 7-IO, and 322 is taken into the 25th bit 1- of register 5.

The noteworthy data is 124. The counter 21 is 22. counter 2
2 becomes 2.

Reference pattern data PPM when the target data is 124 (that is, the rightward pixel of the original image pattern is the target pixel)
is shown in Figure 1Q. In this case, bit data a, b, and C are dummy data initialized in Sl, and f is the first
Line dummy data.

j becomes dummy data of the second line.

The extended data of bit data 123 is taken into bits 7 to 10, and 323 is taken into the 25th bit of register 5.

The data of interest is the dummy data of the first line, counter 21
is 23. Counter 22 becomes 3.

The extended data of bit data 124 is taken into 7-IO. In this case, the extended data of the bit data 124 has been corrected by the dummy data of the first line as described above, but since the dummy data is uO#l, referring to FIG. As explained above, the AND gate AN31 of the selection delay circuit 63 is off, so there is actually no influence of the dummy data (it is not corrected).

Load 324 into the 25th bit of register 5.

The data of interest is 2++ counter 21 is 24. counter 22
becomes 4.

Reference pattern data PP when the data of interest is 21
M is shown in Figure 1m. In this case, bit data a is 8
1, b is the dummy data of the first line, and g is the dummy data of the second line.

S 18-319-820-521-...-821
exit the loop.

In the full double-width mode, the upper extended data of bit data 121 to 124 is output to the 6th line of the first line of the buffer memory 400.
byte and write the lower extension data to the 6th byte of the second line.

In the horizontal double-angle mode, upper extended data of bit data 121 to 124 is written to the 6th byte of the first line of the output sofa memory 400.

The write byte address φ is 7k and the parameter is 6.

Since the value of the parameter is 6, the process exits the loop from 817 to S27 and proceeds to 328 in FIG. 1f.

At this point, the data of interest is 21, and the information distribution pattern detection circuit 6 outputs extended data of the dummy data of the first line, but since this extended data is meaningless, it is sent to the register 7. ~12 k, 328
At this point, registers 2 to 5 are synchronously shifted by 1 bit. As a result, the dummy data of the third line is written to the 25th pin 1- of the register 5, and the data of interest becomes 22.

In S29, the value of the parameter is set to O, and in S30, the parameter L is increased by 1. Due to this.

The value of L is 2, h, and the process returns to 86 from S31.

In S7, increment the parameter by 1 and set the value to 4.
and S8. Proceed to S9, 5IO-8ll-812-・
...-3ll loop, ODP to P/S register 2
Write the fourth line of

After that, S13. S16. The process advances to S17, and in 818, the extended data of bit data 21 is taken into registers 7-12.

Below, in the same way as above, sequential bit data 2□~2
24 extension data is created and written in the third and fourth lines k of the output buffer memory 400 in the full double-angle mode, and in the second line in the horizontal double-angle mode (L=2).

FIG. 1n shows reference pattern data PPM focusing on bit data 224, where C is dummy data on the first line and f is dummy data on the second line.

i becomes dummy data of the first line.

The above process is repeated, and when the value of parameter E becomes 25 in S7, the process directly advances from S8 to S16. Tsume h,
Since no data is written to the P/S register 2, its contents are all 0's. At this time,
The data of interest is 232h, and the value of the parameter L is 23.

After this, in the loop from 317 to S27, the data 231
-2324 extension data are created and written in the 45th and 46th lines k of the output sofa memory 400 in the full double-angle mode, and in the 23rd line in the horizontal double-angle mode (L=23). During this time.

The dummy data is sequentially written into the register 5 as the 25th line data. Therefore, data 2
When 41 is the data of interest (counter 21 = 24. counter 22 = 4), k and a are the 22nd data as shown in Figure 1P.
Line dummy data.

d is the dummy data of the 23rd line, g is the dummy data of the 24th line, and h and i are the dummy data written as the data of the 25th line.

Next, when it comes to 87, the value of ■ becomes 26, and the process goes directly from S8 to S16.The data of interest at this time is 242,
The value of parameter L is 24.

After this, in the loop of S17 to S27 above, the data 241
-2524 extension data is created and written in the 47th line and 48th line k of the output buffer memory 400 in the full double-angle mode, and in the 24th line in the horizontal double-angle mode (L=24). During this time.

The dummy data is sequentially written into the register 5 as the 26th line data. Therefore, data 2
424 becomes the data of interest (counter 21=22.
Counter 22=2), as shown in FIG. 1Q, where C is dummy data written on the 23rd line, f is dummy data on the 24th line, and g is dummy data written as data on the 25th line.

h and i are written as data on the 26th line and become dummy data.

526-327-328-329-83
When proceeding with 0, the value of parameter L becomes 25, so S3
1 to S32.

In full-width mode, the area of the sofa memory 400
Image pattern extension data is stored in area (2), so it must be transferred to the output device (533). Forwarding 53
3) Return to the main routine (not shown).

Next, the double height mode will be explained. In double height mode, there is no horizontal expansion, so S/P registers h and 12
In order to collect the extension data, 8 bits of ODP data are required. In other words.

Replace the aforementioned 321 with 835 (Fig. 1e), 518-
519-320-335-318-...-835 is constructed, and every time the value of the counter 22 reaches 8, the contents (upper side) of the register h are output to the buffer memory 4.
00th (2L-1) line φth byte k, register 1
2 content (lower side) is output from the 2nd L of the cover sofa memory 400.
Line φth byte k is written respectively.

One line of ODP is 24 bits, and data is written to the memory 400 every 8 bits of ○DI' data, so when the parameter K becomes 3, the vertical doubling process for one line is completed, and from S38 to 539-340. -541-3
Proceed to 42.

S39. S40. Regarding S41 and S42, the above-mentioned S28. This is completely synonymous with S29, 330, and S31, and the explanation here will be omitted.

In the double-height mode, the image pattern extension data is stored in areas (2) and (2) of the output sofa memory 400, so it is transferred to the output device (543), and the process returns to the main routine (not shown).

The above is the data expansion processing operation of the image pattern data expansion device shown in FIG. 1a.

FIG. 5c is an expanded image pattern of FIG. 5a (full double-angle mode) produced by this device. The image pattern expansion data created by expanding the original image pattern data of the character "ei" used for drawing Figure 5a in full double-width mode.
, which was created by making the dots the same size,
The diagonal lines are very smooth, and there is no deterioration in image resolution due to the occurrence of unnecessary dots at the intersections of vertical lines and horizontal lines. Probably, the character "ei" is 48X from the beginning.
Even if quantized using 48 pixels, it is expected that the pattern will be almost the same as that shown in FIG. 5C, indicating that the effect of the device of the present invention is remarkable.

FIG. 6c is an extended image pattern of FIG. 6a (full double-angle mode) obtained by this apparatus, and FIG. 7C is an extended image pattern of FIG. 7a (full double-angle mode) obtained by this apparatus. In any of the examples, the quantization noise is improved without degrading the degree of decomposition.

By the way, in the above embodiment, the information distribution pattern detection circuit 6
is configured with a logic circuit, but as shown in Figure 3b, the ROM
It can also be used as a table. In this case, bit data a =
The extended data EPM is read out using i as a 9-bit address.

Next, another embodiment of the present invention will be described. In FIG. 1a, reference pattern cutting circuit 200. Extension data generation circuit 300. The output buffer memory 400 and the read/write control circuit 500 can be replaced with one microcomputer, personal computer, or the like. k, image pattern generator 3 as shown in FIG.
A computer 31 is connected between the computer 0 and the output device 32. In this case, the image pattern generator 30 is configured to generate 2 patterns for k and a predetermined number of characters as shown in FIG.
It is assumed that the pattern memory stores 4×24 bit image pattern original data. An outline of the processing executed by the computer 31 in this case will be described below. Although various computers such as a microcomputer, a personal computer, and a minicomputer can be used as the computer 31, the following explanation will be continued assuming that a microcomputer is used.

First, let's clarify the conditions for the front seats.

In this process, black pixels are indicated by it, and OH99 pixels are indicated by LL I II. In other words, 1. The case where the output device 32 is a CRT display unit is targeted.

2nd = Image pattern original data in this process is read out from the 1 image pattern generator 30 corresponding to the specified character, and dummy data of the 0th line, 25th line, 0th column, and 25th column are added. , that is, the first
After performing the process of adding a 1-bit dummy data edge around the image pattern original data ○DP in figure j,
It is assumed that the data is stored in the RAM within the microcomputer 31.

3rd = Each bit data of the image pattern original data stored in the RAM is denoted by A(,). In this regard, please refer to Figure 3C. FIG. 3C shows the same reference pattern data PPM as shown in FIG. 1H described above.

The hatched area is the data of interest (■ above). If this data of interest is A (1, J), then (
I=1.2,3. ..., 23, 24; J=1,
2, 3. ..., 23.24), the upper left corresponding data of the pixel of interest is A(I-1, J-1).

The data directly above the pixel of interest is A(I-1,, J).

The upper right corresponding data of the pixel of interest is A(T-],,J+1).

The data corresponding to the left neighbor of the pixel of interest is A(r, J-1).

The data corresponding to the right neighbor of the pixel of interest is A(I, J+1).

The lower left corresponding data of the pixel of interest is A (II1.J-1).

The corresponding data directly below the pixel of interest is A(T+l, J)
.

The lower right corresponding data of the pixel of interest is A(II1.J+1).

becomes.

42 The following describes the process of creating image pattern expansion data that expands the image pattern original data twice in the vertical and horizontal directions (corresponding to the above-mentioned full-width mode), and describes the control for transferring the image pattern expansion data to the output device. Not particularly indicated.

52. The created image pattern expansion data is stored in the RAM (corresponding to writing to the output sofa memory 400 described above).

62 Each bit data of image pattern expansion data is
It shall be indicated in (,). Tsume h, attention data A (1,
J), the bit data of the jounin (data j in Figure 1h) is converted to B (I2. I2), and the bit data of Jofu (data k in Figure 1h) is converted to B (I2.
I2+1), and the bit data in the lower row (data m in FIG. 16) as B(I2+1.I2).

The bit data of the lower cloth (data n in Figure 1h) is expressed as B (I
2+1. I2+1) (no delay). Also.

The upper table data (j- mentioned above) of the extended data of the previous data of interest [i.e. A (I, J-1)) is B (:[2
, I2-2), upper cloth data is B (I2. I2-1
).

First, FIG. 17 shows a program list (in Basic language) of the processing executed by the microcomputer 31.

In this case, in the 360th step and the 370th step, l2=2*I (the meaning of 2XI is the same as below) and J2=2*J, so the image pattern expansion data storage area in the RAM is at address (2,2). It seems that the extended image pattern to be output is shifted from the original image pattern, but this indicates the relative address of each bit data within the image pattern extended data. There's no need to worry.

However, if it is desired to match the first read address of the original image pattern data and the first write address of the expanded image pattern data, then in the 360th step and the 370th step, l2=2*I-1
, J2=2*J-1.

Figures 18a, 18b, 18c, and 18d are flowcharts in which the processing in the program list in Figure 17 is developed in an easy-to-understand manner. AP 1-
AP l 9: b is black data, W is white data, blank is arbitrary data), and the content of the extended data is also drawn out with a broken leader line and indicated by a double "opening" (B
PI to BP17: b is data, W is white data).

In addition, in the following explanation, FIG. 1.8a and FIG. 18b will be used.

The step number to flowchart 1 shown in Figures 18c and 18d is indicated by rr S n (S is omitted in the flowchart), and the corresponding step number of the program chart shown in Figure 17 is required. Indicated by "(---3") according to the

First, the process will be explained with reference to the flowchart shown in FIG. 18a.

In lot 5, the line address of the data of interest (OD
The parameter I (synonymous with the above-mentioned I) indicating the line number of P is set to 1, and the value of ■ is examined in 5102, but in this case it is 1, so the process proceeds to 3103. In step 5103, the value doubled is set as parameter E2 indicating the line address of the extended data (corresponding to the write line address described above).

At 5104, a parameter J indicating the bit address of the data of interest (number of bits from the left end of ODP: corresponds to the subscript shown in Figure h) is set to 1.

In 5105, the value of J is examined, and in this case it is 1, so the process goes to 51.07. In 5107, the value of J doubled is set as parameter J2 indicating the bit address of the extended data (360, 370).

In 5108, if the data of interest A (1, J) is black data (that is, data "O": APl corresponding to a white pixel) (380), the process proceeds to S109, and each bit data of the extended data, that is, B (I2 .J2).

B (I2.J2+1), B (I2+1, J2
) and B (I2+1. J2+1) are all set to black data (BPI) (390).

In 5ILO, bit data A (I-1, J-1).

A (1-1, J+1), A (I+1. J-1
).

The product of and A (r+t, J+1) is h, and the value is assigned to parameter C. When the value of parameter C is positive (that is, 1), all four corners of the reference pattern are determined to be white data, as shown in Ar2, and bit data A (I-
1, J) is ``0'', the data directly above (data corresponding to the pixel directly above the pixel of interest) becomes black data, as shown in Ar1.
, in these cases.

The reference pattern data PPM are shown in FIGS. 12a, 12b, 12d, 12f, and 13a.

Since it does not correspond to any of the patterns shown in Figures 13b, 13d, 1', and 3f, proceed from sii+ or 5h2 to 8161 in Figure 18d, increment the parameter J by 1, and update the data of interest. . In these cases, all of the extended data is black data since it passes through 5109 (corresponding to the case of other black pixels described above) (400).

If the data of interest is black data and does not correspond to Ar2 and Ar1, then the reference pattern data PI'''M is 4.
If there is black data in at least one corner and the data directly above is white data, from Sl 12 to 5h in Figure 18b
Proceed to step 3.

In 5h3, take the product of bit data A (1-], J-1) and A (I, J-1) and use the value as parameter DI.
and A (I-1, J+1) and A (r-z
, J-1) and assign the value to parameter D2.

Check the value of Dl in 5h4, and if Dl is positive (that is, 1), at least the upper left data (data corresponding to the upper left pixel of the pixel of interest) and the left neighboring data (data corresponding to the left neighboring pixel of the pixel of interest), as shown in Ar4. is determined to be white data. In 5h5, check the value of D2.

If D2 is O, at least one of the upper right data (data corresponding to the upper right pixel of the pixel of interest) or the lower left data (data corresponding to the lower left pixel of the pixel of interest) of the reference pattern data is determined to be black data. Therefore, if the value of DI is positive and the value of D2 is 0, this reference pattern data PPM corresponds to at least the pattern shown in FIG. 12a and/or FIG. 12b. In BF
As shown in 2, the extended data B (I2.J2), that is, the needle thread data, is updated to white data (1), and the process proceeds to 5h7.

DI is 0. In other words, when the upper left data and/or the adjacent left data are black data, and/or when D2 is positive, that is, when the upper right data and the lower left data are white data, the reference pattern data PPM is
Since it does not correspond to any of the patterns shown in Figure d and Figure 12F, 81 described later from 5h4 or 5h5
Proceed to 23 and below (410).

In 5h7, check bit data A (I-1, 'J+1), and if this is 1, that is, the upper right data is white data,
Since D2=0, bit data A (I+1.J-1
)=0, that is, the lower left data is determined to be black data. Then, proceed from 5h7 to 5h8, where bit data A (r
, J+1). A (I, J+1) = O1 or h
, if the right neighboring data (data corresponding to the right neighboring pixel of the pixel of interest) is black data, the reference pattern data PPM is determined as shown in Ar5h, and corresponds to the pattern shown in FIG. 12d, so BF2 is set in 5h9. As shown in the figure, the extended data B (12, I2+1), that is, the top cloth data, is updated to white data (1) (the top cloth data has already been set as white data in Sl 16). After this, 8 in Figure 18d
Proceeding to 161, the parameter J is incremented by 1 to update the data of interest (420).

In the reference pattern data PPM, D+>0 and D2
If =0 and it does not match A p 5, check bit data A (I+1.J-1) at 5I20.

Bit data A (T+1.J-1)=1. That is, if the lower left data is white data, since D2=0, bit data A (I-1, J+1)=O, that is, the upper right data is determined to be black data. The process then proceeds from 5120 to 5121, where bit data A(I+1.J) is examined. A
(I+I,J)=0, thumb h, if the data directly below (data corresponding to the pixel directly below the pixel of interest) is black data, the reference pattern data PPM is determined as shown in Ar6, h, 12th f
Since it corresponds to the pattern shown in the figure, at 5122, B(T2+I) of the extended data as shown in BF2.

I2), that is, the maidservant data is updated to white data (1) (the Jojo data has already been set as white data in 5h6) (430).

After this, proceed to 3161 in Fig. 18d, and increment the parameter J by 1 to update the data of interest (431).
.

In the reference pattern data PPM, D2>0 and D1
Even if = 0, if it does not match Al) 5 and Ar6 (that is, it corresponds only to the pattern shown in Figure 12a and/or Figure 12b), 81 in Figure 18d
Proceed to step 61 and increment the parameter J by 1 to update the data of interest (in this case, since it has passed through 8h6, only the top data of the extended data will be white data) (/
131).

5123, the product of bit data A (I-1, J+1) and A (T, J+1) is taken and the value is set as parameter D.
3 and A (I-1, J-1) and A (I+
1. J+1) and assign that value to parameter D4.

In step 5124, the value of D3 is checked, and if D3 is positive (that is, 1), at least the upper right data and the right adjacent data are determined to be white data, as shown in Ar1. In 5125, the value of D4 is checked, and if D4 is 0, at least one of the upper left data or the lower right data (data corresponding to the lower right pixel of the pixel of interest) of the reference pattern data is determined to be black data. Tsume h, D3
If the value of is positive and the value of D4 is 0, this reference pattern data PPM corresponds to at least the pattern shown in FIG. 13a and/or FIG. 13b.
5126, the extended data B (
I2. I2+1), that is, the upper cloth data is converted into white data (1
) and proceed to 5127.

When D3 is 0, that is, the upper right data and/or the adjacent right data are black data, and/or when D4 is positive, that is, the upper left data and the lower right data are white data, the reference pattern data PPM is as shown in FIG. Figure 13b, 13th
It does not correspond to any of the patterns shown in Figures d and 13f (of course, it does not correspond to any of the patterns shown in Figures 12a, 1.2b, 12b).
(does not correspond to any of the patterns shown in Figures d and 12f), so the 18th pattern from 5124 or 5125
Proceeding to 8161 in Figure d, the parameter J is incremented by 1 and the data of interest is updated [440].

5127 checks bit data A (T+I, J+1), and if this is 1, that is, the lower right data is white data,
Since D4=0, bit data A (I-1, J-1
)=0, that is, the upper left data is determined to be black data. Then, proceed from 5127 to 5128, where bit data A
Examine (I+1.J). A (1+1.J)=O, tip h, if the data directly below is black data, the reference pattern data PPM is determined as shown in AP8h, and it corresponds to the pattern shown in Figure 13d, so BF in 5L29
As shown in Figure 2, the extended data B (I2+l.

I2+1), that is, the lower center data is updated to white data (1) (the upper cloth data has already been set as white data in 5126). After this, proceed to 5161 in Figure 18d,
Increment the parameter J by 1 to update the data of interest (h503° In the reference pattern data PPM,
If D3>0 and D4=0 and AP8 does not match, 51
At step 30, bit data A (I-1, J-1) is examined.

Bit data A (I-1, J-1)=1. In other words, if the upper left data is white data, it is automatically determined that bit data A (I+1.J+1)=O1, that is, the lower right data is black data since D4=0. The process then proceeds from 5130 to 5131, where bit data A(I, J-1) is examined. A
(T, J-1)=O1h, if the left adjacent data is black data, the reference pattern data PPM is determined as shown in AP9, and corresponds to the pattern shown in FIG. 13f. The case where the reference pattern data PPM corresponds to the pattern shown in Fig. 13f has been described above, but in this case, k, one Front (left side data)
Correct the upper right and upper cloth data of the expanded bow length data based on the data of interest to black data. Therefore, in 8132,
As shown in BF2, the extended data B (I2.I2), that is, the princess data, is converted into white data (1)k, B (I2.
J 2-2) and B (I2.I2-1), toe h
, update the princess data and Jofu data of the previous expansion data with thought data (0)k (Jofu data has already been set as white data in 5h6) (4
60).

After this, proceed to 8161 in Fig. 18d, and increment the parameter J by 1 to update the data of interest (461).
.

In the reference pattern data PPM, D3>0 and D4
Even if = 0, if it does not match AP8 and AP9 (
In other words, if the pattern corresponds only to the patterns shown in FIG. 13a and/or FIG. 13b), proceed to 8161 in FIG. Therefore, only the cloth data of the extended data is white data) (461
).

At 5108, if the data of interest A (I, J) is white data (APII), proceed to 81.33.

Each bit data of extension data as shown in BPI 1,
That is, B (I2. I2), B (I2. I
2+1).

B (I2+ 1, I2) and B (I2+1
．． I2+1) to all white data) (47
0).

In 5134, bit data A (I-1, J-1,)
.

A (I-1, J+1), A (1+l, J-1).

The sum of and A (I+1.J+1) is h, and that value is assigned to parameter E. When the value of this parameter E is 0, all four corners of the reference pattern are determined to be black data, as shown in API2, and bit data A(r-1, J)
When is h1'', the data directly above becomes white data as shown in AP3. In these cases, the reference pattern data PP
M is shown in Figures 14a, 14b, 14c, and 14e.
14g, 15a, 15b, 15c.

Since it does not correspond to any of the patterns shown in FIGS. 15e and 15g, the process proceeds from 5135 or 8136 to 8161 shown in FIG. 18d, where the parameter J is incremented by 1 and the data of interest is updated. In these cases 8
133, all of the extended data becomes white data (471).

If the data of interest is white data and does not correspond to API2 and AP13, then 4 of the reference pattern data PPM
If at least one of the corners has white data and the data directly above is black data, from 5136 to 813 in Figure 18c.
Proceed to step 7.

At 5137, bit data A (r, J-1) is examined. A (r, J-1)I0, that is, when the left adjacent data is not black data, Fig. 14a, Section 1.4. Figure b,
Since this does not correspond to any of the patterns shown in FIGS. 14c, 14e, and 14g, the process proceeds to 8149 in FIG. 18d, which will be described later (472). A(I, J-
1) If =O, bit data A in 813g
(I-1, J+1) and A (I, J+1) and bit data A (I+1.J-1) and A (I
+1. J) and the sum are substituted as the value of parameter F1.

The value of Fl is checked in 5139, and if the value of this parameter F1 is positive, k as shown in A P l 4 a or AP14b, at least the upper right data and the right adjacent data of the reference pattern data PPM are white data, or the lower left data It is determined that the data and the data immediately below are white data. In other words, when the values of h and Fl are positive, this reference pattern data PP
M corresponds to at least the pattern shown in FIG. 14a or 14b, and at 5140, B
As shown in P12a, extended data B (I2.J2),
Update the above table data to black data (0) and get 5153
Proceed to. If Fl is 0, proceed to 5147 described later (4
80).

5141 checks bit data A (I-1, J+]), and if this is Ol, that is, the upper right data is black data, then F
Since l〉0, it follows that A(1+1.J-1)=1 and A(I
+l, J)=1, that is, the lower left data and the data directly below are determined to be white data. Therefore, bit data A (I, J+1) is examined at 8142.

A (I, J+1)=1. In other words, if the data on the right is white data, the reference pattern data PPM at this time is AP
As shown in FIG. 15, it corresponds to the pattern shown in FIG. The data in the table above is already 51
40 as black data). After this, part ]-
Proceeding to 8161 in Figure 8d, the parameter J is incremented by 1 to update the data of interest (490).

In reference pattern PPM, if Fl>O does not match AP15, bit data A (I+1.J
-1), and if this is 0, that is, the lower left data is black data, then since Fl>0, A(1-1, J+1) =
1 k A (I, J + 1) = 1.

In other words, the upper right data and the data adjacent to the right are determined to be white data. Therefore, at 8145, bit data A (I+1.
J) Examine. If A(I+L,J)=1, that is, the data directly below is white data, the reference pattern data PPM at this time is determined as shown in AP16h, and it corresponds to the pattern shown in FIG. 14g, so in 5146 B.P.
As shown in 14, the extended data B (I2+1.J2),
In other words, update the following data to black data (0) (the data in the table above is already considered black data in 5140)
[500]. Thereafter, the process proceeds to 8161 in FIG. 18d, and the parameter J is incremented by 1 to update the data of interest (501).

In the reference pattern data PPM, even if Fl>0, if it does not match AP15 and AP16 (that is, if it corresponds only to the pattern shown in FIG. 14a and/or FIG. 14b), proceed to 8161 in FIG. 18d. ,
The parameter J is incremented by 1 to update the data of interest (in this case, since 5140 has been passed, only the upper table data of the extended data becomes black data) (501).

By the way, when proceeding to 5147 at 5139 with F1=O, if A (I-1, J-1)=1, thumb h, and the upper left data is white data, the reference pattern data PPM at this time is like AP14c. h, corresponding to the pattern shown in FIG. 14c. Therefore, in 8148, B
As shown in P12b, extended data B (I2.J2),
In other words, the above table data is updated to black data (0). After this, the process proceeds to 8161 in FIG. 18d, and the parameter J is incremented by 1 to update the data of interest (510).

A (1, J-1)=0. Therefore, even if the left adjacent data is black data, F1=0, that is, the upper right data and/or the right adjacent data are thought data, the lower left data and/or the data directly below are thought data, and A (T-1, J-1)
=O1, that is, when the upper left data is black data, the reference pattern data PPM are as shown in Fig. 14a, Fig. 14b1g,
Since it does not correspond to any of the patterns shown in Figures 14c, 14a, and 14g,
Proceed to 8149 in the figure (510).

At 5149, bit data A(I,, J+1) is checked. A (J, J+1)y! O, sfth, When the data on the right is not black data, Figure 15a, Figure 15b,
Since it does not correspond to any of the patterns shown in Figures 15c, 15e, and 15g (of course, Figure 14a,
Figures 14b and 14c.

does not correspond to any of the patterns shown in Figures 14e and 14g), proceed to 5161 and set parameter J to 1.
The data of interest is updated by incrementing it (5h). A
If (I, J+1)=O, at 5150 bit data A (I-1, J-1) and A (I, J
-1) and the product of bit data A (1+1.J) and A (■+i, J+1) with parameter F2.
Assign it as the value of

5I51 checks the value of F2, and if the value of this parameter F2 is positive, it is determined whether at least the upper left data and the left adjacent data of the reference pattern data PPM are white data, as shown in API7a or API7b.

Alternatively, it is determined that the data directly below and the data at the bottom right are white data. In other words, when the values of h and F2 are positive, this reference pattern data PPM is at least as shown in FIG.
This corresponds to the pattern shown in Figure 5b, 515
2, the extended data B (
F2. J2+1), that is, upper cloth data is black data (0)
Update to 5153. If Fl is 0, the process proceeds to S159, which will be described later (512).

-3153 examines bit data A (I+1.J+1), and if this is Ol, that is, the lower right data is black data,
Since F2〉0, naturally A(I-1, J-1)I1 and A(
1, J-1) I1, that is, the upper left data and the left adjacent data are determined to be white data. Therefore, with 8154 bit data A
Examine (I+1.J).

p, (I+1.J)I1, that is, if the data directly below is white data, the reference pattern data PPM at this time is AP
As shown in FIG. 18, it corresponds to the pattern shown in FIG. (The upper cloth data has already been set as black data in 5152.) After this,
Proceed to 5161 and increment the parameter J by 1 to update the data of interest (5203° If F2>O does not match AP18 in reference pattern PPM, bit data A (T-1, J
-1), and this is 0. In other words, if the upper left data is black data, since F2>O, A(I + 1.J) =
1A(I+1, J+1)='l, that is, the data directly below and the data at the bottom right are determined to be white data. Therefore, in 8157, bit data A (I, J-1)
Find out. A(I, J-1)I1, that is, if the left adjacent data is white data, the reference pattern data PP at this time
Since M is determined as shown in API9 and corresponds to the pattern shown in Figure 15g, in 8158, B (I 2. J 2) of the extended data, which is the jounin data, is black as shown in BP]7. Update the data to (0) (the upper cloth data has already been set as black data in 5152) (53
0).

After this, proceed to 5I61, and increment the parameter J by 1 to update the data of interest (5313° Even if Fl>0 in the reference pattern data PPM, AP1
5 and AP16 (that is, the pattern corresponds only to the pattern shown in FIG. 14a and/or FIG. 14b), the process proceeds to 5161, and the parameter J is incremented by 1 to update the data of interest (in this case, 514
Since it passes through 0, only the Jonin data in the extended data is black data) (53],).

By the way, when proceeding to 3159 at 5151 with F2=0, if A (I-1, J+1)I1, the upper right data is white data, the reference pattern data PPM at this time is determined as AP17c. , corresponds to the pattern shown in FIG. 15c. Therefore, in S]60, B
As shown in P15b, the extended data B (I2.J2+1
), that is, the upper cloth data is updated to black data (0). Thereafter, in S161, the parameter J is incremented by 1 to update the data of interest (532).

A (I, J+1) = O1 or h, even if the data on the right is black data, F2 = 0, that is, the upper left data and/or the data on the left are black data, and the data directly below and/or the lower right data is black data. , and A (1-1, J+1)
= 0, that is, when the upper right data is black data, the reference pattern data PPM does not correspond to any of the patterns shown in Figures 15a, 15b, 15c, 15e, and 15g. Therefore, the parameter J is incremented by 1 at 5161 to update the data of interest (5
40).

When the above process is repeated and the expansion process of the 24th bit data of the first line is completed, the parameter J becomes 25.
The process proceeds from step 5105 to step 5106 (FIG. 18a), where the parameter ■ is incremented by 1 and applied to the bit data of the next line. Execute the above process. This is repeated further, and when the expansion process of the data of the 24th bit of the 24th line is completed, and the generation of image pattern expansion data from the specified image pattern original data is completed, 8161 (first
8ci figure), 5105.5106 (Figure 18a), and at this time, the value of parameter E becomes 25, so 5
The process returns to the main routine from step 102.

Also in the embodiment apparatus shown in FIG. 4 in which the microcomputer 31 described above generates image pattern extended data from image pattern original data, the above-mentioned 1a
Image pattern extension data can be obtained that is exactly the same as that obtained with the embodiment shown in the figure.

(2) Effects of the Invention As described above, according to the present invention, one image pattern original data can be converted into image pattern extended data in which diagonal line quantization noise has been modified without deteriorating image resolution. Therefore, in addition to enlarging an original image pattern, it is also possible to convert original image pattern data based on a quantized pattern with a low pixel density into expanded image pattern data with a high pixel density. , laser printers, CRT display devices.

Facsimiles, plotters, and other information processing equipment
Since the original drawing pattern data (or low-density facsimile reception data) of the low-density character generator can be converted into high-density data and provided, it is possible to downsize the character generator and improve the quality of printing or display.

A specific example of the effect of the present invention is shown in FIG. 5c.

As shown in FIGS. 6c and 7c.

[Brief explanation of drawings]

FIG. 1a is a block diagram showing the configuration of the image pattern data expansion device according to the first embodiment of the present invention, and FIG. 1b is a logic circuit showing the configuration of the information distribution pattern detection circuit 6 of the device shown in FIG. 1a. Figures 1c, 1d, 1e and 1h are flowcharts illustrating the general operation of the microprocessor 18 of the device shown in Figure 1a. Figure 1g shows the shift registers 3 and 4 of the device shown in Figure 1a.
FIG.
Figure j is a plan view showing the original image pattern data ODP. First, FIG. 1Q, FIG. 1m, FIG. 1n, FIG. 1p, and FIG. 1q are plan views showing reference pattern data PPM including dummy data. FIG. 2a is a logic circuit diagram showing details of the black data expansion circuit 61 of the information pattern detection circuit 6 shown in FIG. 1b;
The figure is a logic circuit diagram showing details of the white data expansion circuit 62 of the information pattern detection circuit 6 shown in Fig. 1b, and Fig. 2c shows details of the selection delay circuit 63 of the information pattern detection circuit 6 shown in Fig. 1b. FIGS. 2d and 2e are plan views showing a truth table showing the operation of the black data expansion circuit 61 shown in FIG. 2a, and FIGS.
FIG. 6 is a plan view showing a truth table showing the operation of the white data expansion circuit 62 shown in the figure. FIG. 3a is a block diagram showing an outline of the structure of the image pattern data expansion device shown in FIG. 1a, and FIG. 3b is a block diagram showing an outline of the structure of a modified example. FIG. 3C shows reference pattern data P of the second embodiment of the present invention.
FIG. 3 is a plan view showing addresses of each bit data of PM. FIG. 4 is a block diagram showing a general configuration of an image pattern data expansion device according to a second embodiment of the present invention. Fig. 5a shows the original image pattern of the character "ei", Fig. 5b shows its simple double enlarged image, and Fig. 5C shows the first embodiment shown in Fig. 1a and the second embodiment shown in Fig. 4. FIG. 7 is a plan view showing enlarged painter's patterns, respectively, according to an example; Figure 6a shows the original image pattern of horizontal, vertical, and diagonal lines.
FIG. 6C is a plan view showing an enlarged image pattern according to the first embodiment shown in FIG. 1A and the second embodiment shown in FIG. 4, respectively. Fig. 7a shows the original image pattern of the symbol "O", Fig. 7b shows its simple double enlarged image, and Fig. 7C shows the first embodiment shown in Fig. 1a or the second embodiment shown in Fig. 4. FIGS. 3A and 3B are plan views each showing enlarged image patterns, according to an example; FIGS. FIG. 8 is a plan view for explaining the directions of image components. Figures 9a, 9b, 9c, 9d, 9e,
Figure 9f, Figure 9g, Figure 9h, Figure 91, Figure 9j,
Figure 9 and Figure 9Q are plan views showing patterns obtained by quantizing the directions shown in Figure 8. Figures 10a, 10b, 10c, 1Od, 10e, 10f, 13g, 14d, 1
Figure 0i, Figure 10j, Figure 10. Figures 10f1, ha, hb, hc, 1i
Figure d, Figure 1ie, Figure IIF, Figure HG, Figure hh,
Figures h4, hj, hj and hf1 are plan views showing the original image and bit expansion plane in the expansion process of the apparatus of the present invention. Ru. Figures 12a, 12b, 12d, 12f, 13a, 13b, 13d, 13f, 1
Figure 4a, Figure 14b, Figure 14c. Figure 14e, 14. Figure 15g, Figure 15a, Figure 15b, Figure 15c, Figure 15e, and Figure 15g are plan views showing the bit data arrangement in the reference pattern PPM;
Figure c, Figure 12e, Figure 12g. Figure 13c, Figure 13g, Figure 13g, Figure 14d,
FIGS. 14f, 14h, 15d, 15f, and 15h are plan views showing the bit data arrangement within the extended pattern EPM. FIGS. 16a, 16b, and 16c are plan views showing decorative parts of characters. FIG. 17 is a plan view showing the operation program list 1 of the microcomputer 31 shown in FIG. 4. 18a, 18b, 18c, and 18d are flowcharts showing operations based on the program shown in FIG. 17. 100: Image pattern generator (image pattern data memory means) 200: Reference pattern extraction circuit (image pattern data reading means) 300: Extension data generation circuit (extension data generation means) 400: Output cover sofa memory (extension data memory means) ) SOO: Read/write control circuit (image pattern data reading means) 2: Parallel in/serial out register 3.4, 5
: Shift register 6: Information distribution pattern detection circuit 7.8, 9, 10, h, 12 serial in/parallel out register 13.14: Latch 15: Data selector 16: Multiplexer 18: Microprocessor 19 System controller 20: Pulse generation 21, 22: Counter 30: Image pattern generator (image pattern data memory means) 31: Microcomputer (image pattern data reading means, extension data generation means, extension data memory means) 32: Output device 61: Black data extension circuit 62: White data expansion circuit 63: Selection delay circuit DLY: Delay circuit

Claims (10)

[Claims] (1) From the image pattern data memory means storing image pattern data representing image patterns such as figures, characters, symbols, etc., bit data corresponding to the pixel of interest to be converted and at least 8 pixels adjacent to the pixel of interest in the image pattern are extracted. An image pattern data reading means that sequentially updates the pixel of interest and sequentially reads out the bit data corresponding to each pixel of interest as a reference pattern; Extended data generation means for expanding bit data corresponding to an extended pattern having a total of 4 pixels, 2 pixels x 2 pixels perpendicular to the reference line, the bit data corresponding to a pixel with an image component in the reference pattern. The two-dimensional arrangement with respect to the set reference line is at least a row corresponding to a declination angle of 45 degrees, a row corresponding to a declination angle of 135 degrees, a declination angle of 0 degrees and a declination angle of 4 degrees.
A sequence corresponding to an intermediate declination angle between 5 degrees, a sequence corresponding to an intermediate declination angle between 45 degrees and 90 degrees, and a sequence corresponding to an intermediate declination angle between 90 degrees and 135 degrees. 7 types of arrangements: a sequence corresponding to an intermediate declination angle between 135 degrees and 180 degrees, and a sequence corresponding to other declination angles. and extracting at least one column of extended data of the bit data corresponding to the extended pattern of the pixel array with and without image components according to the discriminated arrangement;
An image pattern data expansion device comprising: expansion data generation means; and expansion data memory means for storing the expansion data. (2) The expansion data generation means expands the bit data corresponding to the pixel of interest into bit data corresponding to an expansion pattern having a total of 4 pixels, 2 pixels parallel to the set reference line x 2 pixels perpendicular to the reference line. An image pattern expansion device according to claim (1). (3) The extended data generation means: When the bit data corresponding to the pixel of interest is bit data corresponding to a pixel with an image component included in a row corresponding to the declination angle of 45 degrees, the bit data corresponds to a corner protruding outside of the row. Expand the bit data corresponding to an expanded pattern in which one pixel is a pixel without an image component and the other three pixels are pixels with an image component. When the bit data corresponds to a pixel with an image component, it is expanded to bit data corresponding to an extended pattern in which one pixel corresponding to a corner protruding to the outside of the row is a pixel without an image component, and the other three pixels are pixels with an image component. ; The bit data corresponding to the pixel of interest is the declination angle 0 degrees and the declination angle 45 degrees.
If the bit data corresponds to a pixel with an image component that corresponds to an intermediate deviation angle between degrees, one pixel corresponds to an angle that protrudes to the outside of the row, and the pixel is parallel to the reference line. The bit data corresponding to the pixel of interest is expanded to the bit data corresponding to the expansion pattern in which one pixel lined up with is a pixel without an image component and the other two pixels are pixels with an image component;
When the bit data corresponds to a pixel with an image component that corresponds to an intermediate deviation angle between 0 degrees, one pixel corresponds to an angle that protrudes to the outside of the row, and the pixel is connected to the reference line. The bit data corresponding to the pixel of interest is expanded to the bit data corresponding to the expansion pattern in which one vertically aligned pixel is a pixel without an image component and the other two pixels are pixels with an image component;
When the bit data corresponds to a pixel with an image component corresponding to and included in an intermediate declination angle between 35 degrees,
Bit data corresponding to an expanded pattern in which one pixel corresponding to a corner protruding to the outside of the row and one pixel aligned perpendicularly to the reference line to the pixel are pixels without an image component, and the other two pixels are pixels with an image component. Expanding to Extended to bit data corresponding to an expanded pattern in which one pixel corresponding to an outwardly projecting corner and one pixel aligned parallel to the reference line are pixels without an image component, and the other two pixels are pixels with an image component. When the bit data corresponding to the pixel of interest is the bit data corresponding to the pixels with image components included in the other declination angles, it is expanded to the bit data corresponding to the extended pattern in which all four pixels are pixels with image components. When the bit data corresponding to the pixel of interest is bit data corresponding to a pixel without an image component corresponding to and adjacent to the 45-degree declination angle, one pixel corresponding to an angle that cuts into the inside of the row is regarded as a pixel with an image component. , expand the other three pixels to bit data corresponding to an extended pattern in which the pixels have no image component; When the bit data corresponding to the pixel of interest is the bit data corresponding to the pixel having no image component corresponding to and adjacent to the declination angle of 135 degrees, , 1 corresponding to the angle that cuts into the inside of the sequence
The bit data corresponding to the pixel of interest is expanded to correspond to the expansion pattern in which the pixel is a pixel with an image component and the other three pixels are pixels without an image component;
When the bit data corresponds to a pixel without an image component corresponding to or adjacent to an intermediate deviation angle between degrees, one pixel corresponds to an angle that cuts into the inside of the array, and the pixel is parallel to the reference line. The bit data corresponding to the pixel of interest is expanded to the bit data corresponding to the expansion pattern in which one pixel in the row is a pixel with an image component and the other two pixels are pixels without an image component;
When the bit data corresponds to a pixel without an image component that corresponds to or is adjacent to an intermediate deviation angle between 0 degrees, one pixel corresponding to an angle that cuts into the inside of the array, and a bit perpendicular to the reference line to the pixel. One pixel lined up with is a pixel with an image component,
The other two pixels are expanded to bit data corresponding to an expansion pattern in which the pixels have no image component;
When the bit data corresponds to a pixel without an image component corresponding to or adjacent to an intermediate deviation angle between 35 degrees, one pixel corresponding to an angle that cuts into the inside of the array, and the pixel perpendicular to the reference line. The bit data corresponding to the pixel of interest is expanded to the bit data corresponding to the expansion pattern in which one pixel lined up with is a pixel with an image component and the other two pixels are pixels without an image component; When the bit data corresponds to pixels without adjacent image components that correspond to an intermediate deviation angle between
Bit data corresponding to an extended pattern in which one pixel corresponding to a corner that cuts into the inside of the row and one pixel aligned parallel to the reference line are pixels with an image component, and the other two pixels are pixels without an image component. Expanding to Expand; The image pattern expansion device according to claim (2). (4) The extended data generation means is configured such that the bit data corresponding to the pixel of interest is bit data corresponding to a pixel that corresponds to an intermediate declination angle between the declination angle of 135 degrees and the declination angle of 180 degrees and includes an image component. In some cases, two adjacent pixels of an extended pattern corresponding to the previous readout reference pattern, which are aligned parallel to the reference line at one pixel corresponding to an outwardly projecting corner of the array, are set as pixels with an image component. An image pattern expansion device according to claim 3, which corrects bit data corresponding to the expansion pattern. (5) The image pattern data reading means consists of a pixel of interest and eight pixels two-dimensionally surrounding the pixel of interest.
Bit data corresponding to each pixel x 3 pixel matrix is read out as a reference pattern; the extended data generating means defines rows parallel to the set reference line and columns perpendicular to the set reference line in the matrix, and The bit data corresponding to the pixel in the 1st column is a, the bit data corresponding to the pixel in the 1st row and 2nd column is b, and the bit data corresponding to the pixel in the 1st row and 3rd column is c.
, d is the bit data corresponding to the pixel in the 2nd row, 1st column, e is the bit data corresponding to the pixel on the 2nd row, 2nd side, f is the bit data corresponding to the pixel in the 2nd row, 3rd column, pixel in the 3rd row, 1st column. The corresponding bit data is g, and the bit data corresponding to the pixel in the 3rd row and 2nd column is h.
, let i be the bit data corresponding to the pixel in the third row and third column: At least a, b, c, and d are bit data corresponding to pixels without an image component, and e, f, and g are bit data corresponding to pixels with an image component. In some cases, the bit data corresponding to the pixel of interest is bit data corresponding to a pixel that corresponds to an intermediate polar angle between the polar angle 0 degrees and the polar angle 45 degrees and includes an image component, and at least a, b and d are bit data corresponding to pixels without image components, e and g are bit data corresponding to pixels with image components, c is bit data corresponding to pixels without image components, and f is bit data corresponding to pixels with image components. Except when it is bit data; or when at least a, b and d are bit data corresponding to pixels without an image component, c and e are bit data corresponding to pixels with an image component, and g is an image component Except when the bit data corresponds to a pixel with no image component and h is the bit data corresponding to a pixel with an image component; If at least a, b, d, and g are bit data corresponding to pixels without an image component, and c, e, and h are bit data corresponding to pixels with an image component, then the bit data corresponding to the pixel of interest is the deviation angle 45. It is assumed that the bit data corresponds to a pixel with an image component that corresponds to an intermediate declination angle between degrees and a declination angle of 90 degrees, and at least b, c, f, and i are bit data corresponding to pixels without an image component. If a, e, and h are bit data corresponding to pixels with image components, the bit data corresponding to the pixel of interest corresponds to and includes an intermediate argument between the argument angle of 90 degrees and the argument angle of 135 degrees. At least b, c and f are bit data corresponding to pixels with no image component, e and i are bit data corresponding to pixels with an image component, and a is bit data corresponding to pixels with an image component. Except when pixel-corresponding bit data has no image component and d is pixel-corresponding bit data with image component; or, at least b, c, and f are pixel-corresponding bit data without image component, and a and e have image component. In the case where the bit data corresponds to a pixel, except when i is the bit data corresponding to a pixel without an image component and h is the bit data corresponding to a pixel with an image component; the bit data corresponding to the pixel of interest is the argument 135 At least a, b, c, and f are bit data corresponding to pixels with no image component, and d, e, and i are bit data corresponding to pixels with an image component. In the case of data, the bit data corresponding to the pixel of interest is bit data corresponding to a pixel that corresponds to an intermediate declination angle between the declination angle of 135 degrees and the declination angle of 180 degrees, and includes an image component, and at least If b, c, and d are bit data corresponding to pixels with an image component, and e, f, g, and h are bit data corresponding to pixels without an image component, the bit data corresponding to the pixel of interest are the above-mentioned argument angle 0 degrees and argument angle. It is assumed that the bit data corresponds to pixels without an image component corresponding to and adjacent to an intermediate declination angle between 45 degrees, and at least b and d are bit data corresponding to pixels with an image component, and e, g, and h are image components. In the case of bit data corresponding to pixels without an image component, except when c is bit data corresponding to a pixel with an image component and f is bit data corresponding to a pixel without an image component; or, at least b and d are pixels corresponding to a pixel with an image component In the corresponding bit data, c, e, and f are bit data corresponding to pixels without image components, g is bit data corresponding to pixels with image components, and h is bit data corresponding to pixels without image components. Or, at least b and d are bit data corresponding to pixels with an image component, a and e are bit data corresponding to pixels without an image component, and c is bit data corresponding to pixels with an image component, and f , g and h are pixel-corresponding bit data without an image component, g is pixel-corresponding bit data with an image component, and c, f, and h are pixel-corresponding bit data without an image component; It is assumed that the bit data corresponds to the pixel without an image component corresponding to and adjacent to the declination angle of 45 degrees, and at least b, d, and g are bit data corresponding to pixels with an image component, and c, e, f, and h are bit data corresponding to pixels with an image component. If the bit data corresponds to a pixel without an image component, the bit data corresponding to the pixel of interest is the bit corresponding to a pixel without an image component corresponding to and adjacent to an intermediate declination angle between the declination angle of 45 degrees and the declination angle of 90 degrees. data, and at least b, f, and i are bit data corresponding to pixels with an image component, and a, d, e, and h are bit data corresponding to pixels without an image component, then the bit data corresponding to the pixel of interest is the biased It is assumed that the bit data corresponds to a pixel without an image component that corresponds to and is adjacent to an intermediate declination angle between an angle of 90 degrees and a declination angle of 135 degrees, and at least b and f are bit data corresponding to pixels with an image component, e, h and i are bit data corresponding to pixels without image components, except when a is bit data corresponding to pixels with image components and d is bit data corresponding to pixels without image components; or at least b and f is bit data corresponding to a pixel with an image component, a, d, and e are bit data corresponding to a pixel without an image component, i is bit data corresponding to a pixel with an image component, and h is corresponding to a pixel without an image component. Except when it is bit data; or, at least b and f are bit data corresponding to pixels with an image component, c and e are bit data corresponding to pixels without an image component, and a is a pixel with an image component. corresponding bit data and d, h, and i are pixel corresponding bit data without image component, and i is pixel corresponding bit data with image component, and a, d, and h are pixel corresponding bit data without image component. In the case of excluding; Bit data corresponding to the pixel of interest is bit data corresponding to a pixel without an image component corresponding to and adjacent to the declination angle of 135 degrees, and at least a, b, and f are bit data corresponding to a pixel with an image component, and d, When e, h, and i are bit data corresponding to a pixel without an image component, the bit data corresponding to the pixel of interest corresponds to an intermediate deviation angle between the deviation angle of 135 degrees and the deviation angle of 180 degrees, and is an adjacent image. The image pattern expansion device according to claim 3, wherein the image pattern expansion device is bit data corresponding to a pixel without a component. (6) The extended data generating means defines rows parallel to the set reference line and columns perpendicular to the set reference line in the extended pattern, and bit data corresponding to the pixel of the first row and first column is j, Let k be the bit data corresponding to the pixel in the 2nd column, m be the bit data corresponding to the pixel in the 2nd row and 1st column, and n be the bit data corresponding to the pixel in the 2nd row and 2nd column: The bit data corresponding to the pixel of interest is the deflection angle. 0 degrees and declination 45
When the bit data corresponds to a pixel with an image component that corresponds to an intermediate argument between degrees, let j and k be bit data corresponding to a pixel without an image component, and m
Let and n be bit data corresponding to a pixel with an image component; When the bit data corresponding to the pixel of interest is bit data corresponding to a pixel with an included image component that corresponds to the 45-degree declination angle, j is the bit data corresponding to a pixel with no image component. Let k, m, and n be the bit data corresponding to pixels with image components; The bit data corresponding to the pixel of interest are the declination angle 45 degrees and the declination angle 9.
j
and m are bit data corresponding to pixels without image components,
Let k and n be bit data corresponding to a pixel with an image component; bit data corresponding to a pixel of interest are the declination angle 90 degrees and the declination angle 1.
When the bit data corresponds to a pixel with an image component corresponding to and included in an intermediate declination angle between 35 degrees,
Let k and n be bit data corresponding to a pixel without an image component, and let j and m be bit data corresponding to a pixel with an image component; The bit data corresponding to the pixel of interest corresponds to the declination angle of 135 degrees and the included pixel with an image component. When the bit data corresponds to the pixel without an image component, let k be the bit data corresponding to a pixel with no image component, and let j, m, and n be the bit data corresponding to a pixel with an image component; When the bit data corresponds to a pixel with an image component that corresponds to an intermediate deviation angle between the angle 180 degrees, j and k are bit data corresponding to a pixel without an image component, and m and n are image components. The bit data corresponding to the pixel of interest is the declination angle 0 degrees and the declination angle 45 degrees.
When the bit data corresponds to a pixel without an image component and is adjacent to and corresponds to an intermediate deviation angle between degrees, let j and k be the bit data corresponding to a pixel with an image component, and m and n be the bit data corresponding to a pixel without an image component. When the bit data corresponding to the pixel of interest is the bit data corresponding to a pixel without an image component that corresponds to and is in contact with the above-mentioned declination angle of 45 degrees, let j be the bit data corresponding to a pixel with an image component, and k, m, and Let n be bit data corresponding to a pixel with no image component; Bit data corresponding to the pixel of interest is the declination angle 45 degrees and the declination angle 9.
When the bit data corresponds to a pixel without an image component and is adjacent to and corresponds to an intermediate declination angle between 0 degrees, let j and m be bit data corresponding to a pixel with an image component, and k
Let n be the bit data corresponding to a pixel with no image component; The bit data corresponding to the pixel of interest is the declination angle 90 degrees and the declination angle 1.
When the bit data corresponds to a pixel without an image component corresponding to and adjacent to an intermediate declination angle between 35 degrees, k
and n are bit data corresponding to pixels with image components,
Let j and m be bit data corresponding to a pixel without an image component; When the bit data corresponding to the pixel of interest is corresponding to a pixel without an image component that corresponds to and is adjacent to the deflection angle of 135 degrees, let k be the bit data corresponding to a pixel with an image component. Let j, m, and n be bit data corresponding to a pixel with no image component; The bit data corresponding to the pixel of interest corresponds to an intermediate argument between the argument angle 135 degrees and the argument angle 180 degrees. And when it is bit data corresponding to pixels without adjacent image components,
The image pattern expansion device according to claim 5, wherein j and k are bit data corresponding to pixels with image components, and m and n are bit data corresponding to pixels without image components. (7) The extended data generation means is configured such that the bit data corresponding to the pixel of interest is bit data corresponding to a pixel that corresponds to an intermediate declination angle between the declination angle of 135 degrees and the declination angle of 180 degrees and includes an image component. In some cases, the bit data j corresponding to the extended pattern corresponding to the previous read reference pattern
and k to bit data corresponding to a pixel with an image component. (8) The extended data generating means extracts extended data corresponding to the entire extended pattern, and the extended data memory means stores the extracted extended data.
) or (7). (9) The extended data generating means extracts extended data corresponding to a line parallel to the reference line of the extended pattern, and the extended data memory means stores the extracted extended data. Or the image pattern data expansion device according to item (7). (10) The extended data generating means extracts extended data corresponding to a line perpendicular to the reference line of the extended pattern, and the extended data memory means stores the extracted extended data. Or the image pattern data expansion device according to item (7).