JPS62184546A - Control system for execution of test program - Google Patents
Control system for execution of test programInfo
- Publication number
- JPS62184546A JPS62184546A JP61026315A JP2631586A JPS62184546A JP S62184546 A JPS62184546 A JP S62184546A JP 61026315 A JP61026315 A JP 61026315A JP 2631586 A JP2631586 A JP 2631586A JP S62184546 A JPS62184546 A JP S62184546A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- test
- execution
- error
- administration part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 10
- 238000012545 processing Methods 0.000 claims description 7
- 238000010998 test method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、データ処理装置を総合的に試験する命令組合
せ試験と前記データ処理装置が有する命令毎に詳細に試
験する詳細試験により命令機能の正常性を試験する試験
プログラムの実行制御方式〔従来の技術〕
従来、この種の試験プログラムの実行制御方式はスター
トスモール方式であり、各命令毎の詳細試験を順次、実
行するようになっていた。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides an instruction function test that comprehensively tests a data processing device and a detailed test that tests each instruction of the data processing device in detail. Execution control method for a test program for testing normality [Prior art] Conventionally, the execution control method for this type of test program was a start-small method, in which detailed tests were executed for each instruction in sequence. .
上述した従来の試験プログラムの実行制御方式は、各命
令毎の詳細試験をスタートスモール方式に順次実行する
ようになっているので、規模が大きなデータ処理装置に
おいては、試験プログラムも規模が大きくなり、実行時
間が長くなるという欠点がある。The conventional test program execution control method described above sequentially executes detailed tests for each instruction in a start-small method, so in a large-scale data processing device, the test program also becomes large. The disadvantage is that the execution time is long.
本発明の試験プログラムの実行制御方式は、総合試験(
命令組合せ試験)の実行結果を格納する手段と、該手段
の実行結果がエラーの場合、該エラーに相当する命令の
詳細試験を実行する手段を有している。The test program execution control method of the present invention is a comprehensive test (
The method includes means for storing the execution result of an instruction combination test), and means for executing a detailed test of the instruction corresponding to the error when the execution result of the means is an error.
したがって、規模が大きな他の正常な命令の詳細試験の
実行はしなくてもよく、実行時間が短縮できる。Therefore, there is no need to perform a large-scale detailed test of other normal instructions, and the execution time can be shortened.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の試験プログラムの実行制御方式の一実
施例の説明図である。FIG. 1 is an explanatory diagram of an embodiment of a test program execution control method according to the present invention.
OPi (i=1〜n)はコンピュータで定義された命
令コード、Tiは命令組立ルーチンで、命令コードOP
i (i=1〜n)をランダムに選択して組立てられた
命令シーケンス、ST(opi )は各命令コードOP
i に対応する詳細試験サブテスト、Mはこれらのルー
チンを制御する実行管理部である。OPi (i=1~n) is an instruction code defined by the computer, Ti is an instruction assembly routine, and the instruction code OP
The instruction sequence assembled by randomly selecting i (i=1 to n), ST(opi) is each instruction code OP
i is the detailed test subtest corresponding to M, and M is the execution manager that controls these routines.
第2図は、本実施例の処理フローを示す図である。FIG. 2 is a diagram showing the processing flow of this embodiment.
まず、実行管理部Mは命令組立ルーチンをコールし、命
令テーブルOPの中からランダムに選択し、命令シーケ
ンスTiを組立てる(ステップ10)。この後実行管理
部Mはステップ20へ制御を移し、命令シーケンスTi
を実行する。試験が終了すると、命令シーケンスTiの
実行結果であるリターンコードを生成して、それを主記
憶装置内のリターンコード格納領域Rに格納する(ステ
ップ30)と共に制御を実行管理部Mへ戻す。実行管理
部Mは、リターンコード格納領域Hの内容(リターンコ
ード)を調べ(ステップ40.50) 、その結果、エ
ラー発生の命令が格納されていれば、該命令に相当する
詳細試験サブテス)ST+opi+ をコールし実行
しくステップ60)、正常であれば、iを1だけインク
リメントしくステップ70)、試験をくりかえす。First, the execution management unit M calls an instruction assembly routine, randomly selects an instruction from the instruction table OP, and assembles an instruction sequence Ti (step 10). After this, the execution management unit M transfers control to step 20, and executes the instruction sequence Ti.
Execute. When the test is completed, a return code that is the execution result of the instruction sequence Ti is generated and stored in the return code storage area R in the main memory (step 30), and control is returned to the execution management section M. The execution management unit M checks the contents (return code) of the return code storage area H (step 40.50), and if the instruction in which the error occurred is stored, the detailed test subtest (ST+opi+) corresponding to the instruction is executed. Call and execute step 60). If normal, increment i by 1 step 70) and repeat the test.
以上説明したように本発明は、ランダム試験で検出した
エラーの命令のみを詳細試験することにより、規模が大
きな他の正常な命令の詳細試験の実行はしなくてもよく
、保守時間の短縮化ができる効果がある。As explained above, the present invention performs a detailed test of only the instruction with an error detected in a random test, thereby eliminating the need to perform a large-scale detailed test of other normal instructions, thereby reducing maintenance time. It has the effect of
第1図は本発明の試験プログラムの実行制御方式の一実
施例の説明図、第2図は本実施例の処理フローを示す図
である。
OP 1+ OP 21 ・・’ 10PTl ・・’
命令コード、Ti・・・命令シーケンス、
ST(op 11 、ST(OP 2) 、川、 ST
T 0PII)・・・詳細試験サブテスト、
N・・・実行管理部、
R・・・リターンコード格納領域。FIG. 1 is an explanatory diagram of an embodiment of the test program execution control method of the present invention, and FIG. 2 is a diagram showing the processing flow of this embodiment. OP 1+ OP 21...'10PTl...'
Instruction code, Ti...Instruction sequence, ST (op 11, ST (OP 2), river, ST
T0PII)...Detailed test subtest, N...Execution management section, R...Return code storage area.
Claims (1)
記データ処理装置が有する命令毎に詳細に試験する詳細
試験により命令機能の正常性を試験する試験方式におい
て、 前記命令組合せ試験の実行結果を格納する手段と、該手
段の実行結果がエラーの場合、該エラーに相当する命令
の詳細試験を実行する手段を有する試験プログラムの実
行制御方式。[Scope of Claims] A test method for testing the normality of an instruction function through an instruction combination test that comprehensively tests a data processing device and a detailed test that tests in detail each instruction possessed by the data processing device, comprising: An execution control method for a test program, comprising means for storing a test execution result, and means for executing a detailed test of an instruction corresponding to the error when the execution result of the means is an error.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61026315A JPS62184546A (en) | 1986-02-07 | 1986-02-07 | Control system for execution of test program |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61026315A JPS62184546A (en) | 1986-02-07 | 1986-02-07 | Control system for execution of test program |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62184546A true JPS62184546A (en) | 1987-08-12 |
Family
ID=12189946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61026315A Pending JPS62184546A (en) | 1986-02-07 | 1986-02-07 | Control system for execution of test program |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62184546A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02115947A (en) * | 1988-10-25 | 1990-04-27 | Nec Corp | Information processor |
-
1986
- 1986-02-07 JP JP61026315A patent/JPS62184546A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02115947A (en) * | 1988-10-25 | 1990-04-27 | Nec Corp | Information processor |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6134690A (en) | Computerized automation system and method | |
US20130326486A1 (en) | Keyword based software testing system and method | |
US6928378B2 (en) | Stress testing at low cost through parallel execution of unit tests | |
US6735774B1 (en) | Method and apparatus for system call management | |
JP3349057B2 (en) | Multitask processing device, multitask processing method, and multitask processing display method | |
JPS62184546A (en) | Control system for execution of test program | |
US5533195A (en) | Testing tool for diagnosing defective computer system devices | |
EP0801348A1 (en) | Method of monitoring the operation of a computer | |
US20070150866A1 (en) | Displaying parameters associated with call statements | |
JPH0581070A (en) | Programmable controller and user program execution method in programmable controller | |
JP3207564B2 (en) | Event recording method and device | |
JP3339708B2 (en) | Event recording method | |
JPH05298204A (en) | Test circut for input/output processor | |
JP2772999B2 (en) | Experimental system | |
JPS62184545A (en) | Control system for execution of test program | |
JPH04307636A (en) | Program test system | |
CN115292076A (en) | Linux system kernel debugging device and method | |
JP2726998B2 (en) | Computer testing method | |
JPH03242736A (en) | Abnormality processing system | |
JPS61184647A (en) | Performance test system of computer equipment | |
JPH01181135A (en) | Method for testing operating system | |
JPH03130839A (en) | On-line simulation system | |
JPH08147196A (en) | System call emulator | |
JPS63317839A (en) | Program debug method | |
Al-Sharif et al. | UDB: An Agent-Oriented Source-Level Debugger |