JPS62179765A - Manufacture of mis type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an MIS type semiconductor device by forming an electrode pattern through an insulating film on a semiconductor, and selectively forming a junction region of superlattice structure due to ion implanting on a semiconductor portion except the portion directly under the pattern. CONSTITUTION:A P-type or N-type epitaxial layer 2 is grown on a substrate 1 made, for example, of gallium arsenide or the like, coated with a thin insulator film 3 thereon, and coated, for example, with a polycrystalline silicon electrode layer 4 to which an impurity is implanted. Then it is coated with a resist film 5, exposed in a fine pattern by an interference of an electrode beam or a laser light, and a pattern of an electrode layer 4 is formed by etching. With the eventually remaining layer 4 as a mask silicon ions are, for example, implanted to form a doping superlattice region 6 on the epitaxial layer.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a superlattice structure by impurity diffusion.

BACKGROUND OF THE INVENTION Semiconductor devices having a heterojunction with a superlattice structure are usually manufactured by doping epitaxial growth using manufacturing processes such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).

Problems to be Solved by the Invention The fabrication of the conventional superlattice structure 2-benzo formed by a heterojunction is complicated, and the superlattice structure heterojunction formed by the doping epitaxial growth method is difficult to manufacture. Since the characteristics are determined by the voltage, the degree of freedom in design is limited.

Means to Solve the Problems The present invention forms an electrode pattern on the surface of a semiconductor through an insulating film, and selects a superlattice structure junction region by ion implantation into the semiconductor portion except for the area directly under the electrode pattern. This is a method of manufacturing an MIS type semiconductor device, which includes a step of manufacturing a semiconductor device.

By controlling the potential of the gate electrode of the MIS structure,
A periodic potential other than the built-in voltage is applied to control the properties of the superlattice.

Furthermore, since the superlattice is produced two-dimensionally, the current characteristics can be changed depending on the pattern shape of the superlattice.

Embodiment FIG. 1 is a perspective view showing an external view of a semiconductor device manufactured according to the present invention. In the figure, 11 is a substrate;
2 is a semiconductor layer including a superlattice structure, on which an electrode 14 is formed with an insulating film 13 interposed therebetween.

Next, the manufacturing method of the present invention will be explained using FIGS. 2 and 3.

Instead, as shown in FIG. 2(a), a P-type or N-type epitaxial layer 2 is grown on a substrate 1 made of, for example, gallium arsenide. Next, as in the second step), an insulating thin film 3 is deposited thereon. This insulator 3 is made of silicon oxide, for example. Then, an electrode layer 4 made of, for example, polycrystalline silicon doped with impurities is deposited thereon.

Next, as shown in FIG. 2(C), a resist film 6 is further coated on this, and after exposure to a fine pattern by electron beam or laser beam interference, etching is performed to form a resist film 6 as shown in FIG. 2(d).
), the pattern of the electrode layer 4 is formed.

Finally, as shown in FIG. 2(e), ions of silicon, for example, are implanted as a mask for the remaining electrode layer 4 to form a doped superlattice region 6 in the epitaxial layer.

Another method is to form an epitaxial layer 2 and an insulating film 3 on a substrate 1, and then apply a resist film 5, as shown in the cross-sectional views of FIGS. 3(a) to 3(e). A superlattice structure is formed by ion implantation using the resist film 5 as a mask, and the electrode layer 4 is deposited on the resist film 6. May be removed.

Note that the substrate 1 may be made of sapphire or the like. The insulator 3 may be silicon nitride, tantalum oxide, or the like.

Metal 4 includes aluminum, molybdenum, tungsten,
It may be a metal such as tantalum or platinum, a high melting point metal, a noble metal silicide, or tin oxide.

Effects of the Invention According to the method for manufacturing a semiconductor device according to the present invention, a superlattice structure can be created by a planar process, and its characteristics can be controlled by a gate voltage.

Further, the characteristics can also be controlled by the pattern shape.

6 Beige

[Brief explanation of drawings]

FIG. 1 is a perspective view of a semiconductor device according to the present invention, and FIGS. 2 and 3 are step-by-step cross-sectional views showing the manufacturing steps of the semiconductor device according to each embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Epitaxial layer, 3... Insulating film, 4... Electrode layer, 6...
...Resist film, 6...Superlattice region. Name of agent: Patent attorney Toshio Nakao and 1 other person14
-11 magic distance Jims (s---Resist n slimming 5---Regimatato

Claims (1)

[Claims] Forming an electrode pattern on the surface of a semiconductor via an insulating film,
A method for manufacturing an MIS type semiconductor device, comprising a step of selectively forming a superlattice region by ion implantation in the semiconductor portion except for a portion directly under the electrode pattern.