JPS60136264A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a GaAs MES FET of good controllability of threshold voltage, good uniformity in a wafer, and good controllability of electrode voltages by a method wherein a high carrier concentration layer for source and drain contact is formed to epitaxial growth after a gate electrode is formed on an active layer. CONSTITUTION:The part except the gate part and source and drain regions where a high carrier concentration contact layer is to be formed is covered with an SiO2 film 5. At this time, the size of the SiO2 in the periphery of the gate is adjusted so that desired withstand voltages can be obtained between the gate and source and between the gate and drain. Thereafter, the selective epitaxial growth of contact layers 6 is carried out. A method of the selective epitaxial growth is the use of thermal decomposition of an organic metal and arsine. However, hydrogen chloride is introduced at the time of growth in order to epitaxially grow selectively only at the GaAs exposure part. Then, high carrier concentration epitaxial layers can be obtained selectively only at the regions of forming source and drain electrodes by adjusting the amount of introduction of the organic metal and the hydrogen chloride. Finally, ohmic electrodes 7 are formed at the source and drain regions by Au-Ge evaporation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, particularly a Schottky gate field effect transistor (FET) using a compound semiconductor.

[Background of the invention]

Conventionally, the manufacturing method of GaAs MES FET is as follows:
Carrier concentration 1×1017crfL− on a semi-insulating substrate
3 active layer is made using epitaxial growth method, A[# is evaporated on this active layer to form a Schottky metal gate, and then an ohmic metal such as Au-Ge is evaporated to form source 1 drain. It forms a region. In this method, the threshold voltage of the FET is determined by the carrier concentration and thickness of the active layer, so the desired threshold voltage can be obtained by adjusting the active layer thickness before forming the gate electrode. Uniformity within the wafer can also be easily achieved. However, the acidity of the source/drain regions forming the ohmic contact is low, which is disadvantageous for forming a good ohmic contact, and is not preferable as a FET characteristic.

As a method of obtaining good ohmic contact, a high carrier linearity (1 to 3XIO"cm) is added on the active layer.
- There is a method of epitaxially growing additional layers. In this case, the high carrier concentration contact layer is removed only in the source-drain region until the active I- appears, a Schottky gate is formed on the active layer, and the source - An ohmic electrode is formed in the drain region. in this way,
Since the contact 1- has a high resistance, a very good ohmic contact can be made. Shigashi, FET
From the point of view of the threshold voltage, the contact layer and part of the active layer must be etched away with good controllability. Furthermore, in view of the uniformity of the threshold voltage within the wafer, in addition to the uniformity of the etching amount, the thickness of the contact layer, the thickness of the active layer, and the uniformity of the carrier concentration are required. Furthermore, since the gate is formed on all four parts except for the contact layer, processing such as alignment is difficult, and it is difficult to reduce the distance between the gate and the drain by /J's.

Furthermore, there is also a method of forming an active layer and a contact layer using an ion implantation method in a semi-insulating substrate. In particular, a method in which ion implantation during formation of the contact layer is performed using the gate metal as a mask is convenient. However, it is necessary to consider the lateral spread of implanted ions, which may lead to a decrease in breakdown voltage between the gate and source/drain.

[Purpose of the invention]

The present invention uses GaAs, which can form good ohmic contacts at the source and drain, has good controllability of threshold voltage and uniformity within the wafer, and has good controllability of interelectrode voltage.
The present invention provides a method for manufacturing an MB2 FET.

[Structure of the invention]

In the present invention, a gate electrode is formed on the active layer, and then a gate electrode is formed on the active layer. A high carrier concentration layer for a drain contact is formed by epitaxial growth, and it is preferable to use a selective epitaxial method for this epitaxial growth.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. First, as shown in Fig. 1, the carrier concentration is 1 x
10'? An active layer 3 of approximately clrL-1 is formed by epitaxial growth on a semi-insulating substrate l having a high resistance buffer layer 2t-. Then, adjustment is made by etching away the active layer 3 to obtain a new threshold voltage, and a sit key metal gate 4 is formed. Gate metal 4 is Ti-W.

A heat-resistant metal such as W-8t, which does not cause deterioration of the Schottky junction even when subjected to heat treatment at 700° C. for about 60 minutes, is used. Next, there is a north region where a high carrier concentration contact layer such as a gate region is formed. 5i01 excluding drain region
Cover with membrane 5. At this time, the size of 8i02 (horizontal direction in FIG. 1, FIG. 5) around the gate is adjusted between the gate and the drain and between the gate and the drain so that a desired breakdown voltage can be obtained.

After that, carrier concentration 2~4 x 101'ff1-3
, a contact layer 6 having a thickness of approximately 0.2 to 0.3 μm is selectively epitaxially grown. The method of selective epitaxial growth is the thermal decomposition of organic metals (trimethylpotassium or triethylgallium) and arsine (usually MO-C
VD method) is used. However, hydrogen chloride (HCl) is introduced during the growth in order to selectively perform epitaxial growth only on the protruding portion of GaAs. source by adjusting the amount of organic metal and hydrogen chloride introduced. A high carrier concentration epitaxial layer is selectively obtained only in the drain electrode formation region.

Finally, as shown in Figure 2, Au is applied to the source and drain regions.
The ohmic electrode 7 is formed by vapor deposition of Ge. In addition, the 8302 film 5t in the gate area is removed, and the gate metal 4
Form electrodes such as upper 1c A u.

By using the MO-CVD method, selective epitaxial growth is possible at a relatively low temperature of about 650 to 700°C. Therefore, there is no significant difference in the Schottky characteristics before and after forming the contact layer.

Although the present invention has shown a method using the active layer 3 formed by epitaxial growth as an example, it can also be applied to a case where the active layer 3 is formed by ion implantation, and furthermore, application to ICs etc. is also considered. It will be done.

[Brief explanation of the drawing]

FIGS. 1 and 2 are cross-sectional views showing manufacturing steps according to an embodiment of the present invention. 1...Semi-insulating GaAs substrate, 2...
...High resistance buffer epitaxial layer, 3...
・Active layer, 4...Heat-resistant gate metal, 5...
group・510g1l (,6・・mark・selective contact evita 1,000-shall layer, 7・・river・metal for ohmic contact, 8・・・・gate electrode metal.

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device, which comprises forming a Schottky electrode on an active layer, then forming an epitaxial layer with a high carrier concentration, and forming source/drain ohmic electrodes. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the high carrier concentration layer is formed by a selective epitaxial growth technique.