JPS6217863B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming an insulating separation band for a semiconductor integrated circuit, and more particularly to a method for forming a separation band for the purpose of improving the degree of integration, device characteristics, and yield rate.

BACKGROUND ART Currently, a method of selectively oxidizing a silicon (hereinafter abbreviated as Si) substrate is used as a method for forming an insulating separation band for a semiconductor integrated circuit (hereinafter abbreviated as IC). However, this method causes a large amount of silicon dioxide (hereinafter abbreviated as SiO ₂ ) to penetrate into the device region, and as a result, a wide separation band is required, which hinders the improvement of the degree of integration of semiconductor devices. In addition, the interface between Si and SiO ₂ that occurs during biting is at an angle of 30° to 45° with respect to the substrate surface.
As a result, the parasitic junction capacitance between the substrate and the collector, between the collector and the base, and between the base and the emitter is large, which hinders the improvement of characteristics such as switching speed. These two problems can be improved by selectively oxidizing the interface between Si and SiO ₂ under conditions such that the angle of inclination is close to 90°. However, under such conditions, a high density of crystal defects is induced in the device region,
This results in a decrease in the non-defective product rate.

The present invention aims to provide a novel method for forming an insulating separation band that overcomes these drawbacks.

The present invention is characterized by forming a thick first silicon dioxide film on the surface of a semiconductor substrate, and forming a vapor phase grown silicon dioxide film containing phosphorus on the first silicon dioxide film in a method for insulating and separating a semiconductor integrated circuit. (hereinafter referred to as phosphorus glass); and selectively removing the film having a low etching speed and the first silicon dioxide film, thereby exposing a separation zone. a step of forming a trench in a region of the semiconductor substrate where the semiconductor substrate is to be formed; a step of forming a thin second silicon dioxide film on the bottom and side surfaces of the trench of the semiconductor substrate;
a step of ion-implanting impurities through the silicon dioxide film to form a channel stopper region only on the bottom surface of the trench and its vicinity, and then depositing phosphorus glass on the entire surface, and then fluidizing the phosphorus glass. a step of filling the groove; and a step of etching the phosphor glass on the semiconductor substrate from its upper surface until reaching the film having a low etching rate;
Next, there is a step of etching away the film having a low etching rate, and then, at the same time as etching away the first silicon dioxide, a portion of the phosphor glass having a height corresponding to the first silicon dioxide is etched away, thereby removing the semiconductor substrate. The method of manufacturing a semiconductor device includes the steps of exposing the surface of the substrate and simultaneously making the upper surface of the phosphor glass in the groove substantially coincide with the surface of the substrate.

The advantages of the present invention are that since the interface between the element region and the insulating strip is perpendicular to the substrate surface, each junction capacitance is small and therefore good element characteristics can be obtained; is applied to the element area.
The degree of integration can be improved because the SiO ₂ film is not dug in, and the fluidization of phosphorus glass does not essentially induce crystal defects, so there is no reduction in the yield rate.

Furthermore, since the channel stopper region is provided, the isolation function is further enhanced, and at the same time, since ions are implanted through the second silicon dioxide film at the bottom of the trench, no crystal defects occur in this region. Furthermore, since the second silicon dioxide film is also formed on the side surfaces of the trench, and the phosphor glass is not in direct contact with the element forming portion, the element region can be kept clean. moreover,
Since a film such as the Si ₃ N ₄ film has an etching speed slower than that of phosphor glass, the end point of etching of the upper phosphor glass becomes clear. If this film does not exist, the first step is required when etching the upper phosphor glass.
In addition, there is a risk that the phosphorus glass inside the groove may be etched undesirably.
In this regard, in the present invention, the process is divided into three steps: first, the upper phosphorus glass is etched, then the Si ₃ N ₄ film is etched, and then the phosphor glass of the same level as the first silicon dioxide film is etched at the same time. If you do this, the above inconvenience will not occur.

Next, the present invention will be specifically explained with reference to Examples. First, a silicon (Si) substrate 1 is oxidized over the entire surface to grow a silicon dioxide (SiO ₂ ) film 2 with a thickness of about 5000 Å, and a vapor phase grown silicon nitride film 3 is deposited on top of it.
(hereinafter abbreviated as Si ₃ N ₄ film) is deposited to a thickness of approximately 1000 Å over the entire surface. Next, using a selective etching method, the Si ₃ N ₄ film, the SiO ₂ film, and the Si in the region to be used as the insulating isolation band are sequentially etched to form the groove 4 . The etching of Si is carried out by a reactive ion etching method (hereinafter abbreviated as RIE method) using carbon tetrachloride as an etching gas, so that the side walls of the grooves are made almost perpendicular to the surface of the substrate 1. The angle of inclination of the sidewall to the substrate surface that is actually obtained is 70° to 80°.
It is ゜. This groove width is preferably a narrow groove of about 1 μm. This is because if the groove width is wide, the groove 4 cannot be completely filled by the fluidization of the phosphor glass that will be performed later. The reason for depositing the Si ₃ N ₄ film 3 is to clarify the etching end point when removing the phosphorus glass after it has been made into a fluid. Therefore, it is not limited to Si ₃ N ₄ films, but other films such as vapor-grown polycrystalline silicon films can be used as long as the etching rate of phosphorus glass is lower than that of phosphorus glass. good. Figure 1 shows a thickness of 1.5
The depth is 1 μm for the n-type epitaxial layer 5 of μm.
This figure shows the cross-sectional shape when a trench of m length is dug.

Next, the substrate 1 is oxidized again and a SiO ₂ film 6 with a thickness of 500 Å is grown. This SiO ₂ film 6 is used to keep the side walls of the trench 4 clean and to create a good PN junction in the element region 7. After this oxidation, boron ions for channel stopper are ion-implanted 9. At this time, the sidewall SiO ₂ film 6 acts as a barrier to prevent boron from being implanted into the element region 7. Note that since there is thick SiO ₂ 2 above the element region 7, boron is not implanted. The cross-sectional shape up to this point is shown in FIG.

Next, add phosphorus glass 8 with a phosphorus concentration of 12 mol% to 1.5
It is deposited to a thickness of μm and heat treated for 10 minutes at 1000° C. in an N ₂ or O ₂ atmosphere to turn the phosphor glass 8 into a fluid and completely fill the narrow grooves 4 . A laser annealing method can also be used for this fluidization. FIG. 3 shows the cross-sectional shape after phosphorus glass was applied and the material was made into a fluid.

After that, phosphorus glass was converted into Si ₃ N ₄ film 3 using aqueous hydrofluoric acid solution.
Then, only the Si ₃ N ₄ film 3 is etched using CF ₄ plasma (cylindrical type) (FIG. 4). Finally, the RIE method using _CF4 containing hydrogen as the etching gas was used.
By etching the SiO ₂ film 2 and the phosphor glass, the device region 7 is etched.
(Figure 4). The reason why the RIE method is used here is that the etching rates of the oxide film 2 and the phosphor glass are approximately equal.

In this way, the interface between the element region 7 and the insulating strip is substantially perpendicular to the substrate surface, and these surfaces can be made substantially flat.

As another embodiment of the present invention, it can be applied to an isolation band of a field effect IC to improve the degree of integration and reduce the junction capacitance between the source, drain and substrate.

[Brief explanation of the drawing]

1 to 4 are cross-sectional views showing a method of forming an insulating separation band according to an embodiment of the present invention in order of steps. In the figure, 1... Si substrate, 2... SiO ₂ film (5000 Å), 3... Si ₃ N ₄ film, 4... Groove, 5... Epitaxial layer, 6... SiO ₂ film (500 Å) )7...
Element region, 8... Phosphorus glass layer, 9... Boron.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit insulation separation method, a thick first silicon dioxide film is formed on the surface of a semiconductor substrate, and the etching rate is higher than that of a vapor-phase grown silicon dioxide film containing phosphorus on the first silicon dioxide film. forming a film with a low etching rate; and selectively removing the film with a low etching rate and the first silicon dioxide film, thereby forming a trench in an exposed region of the semiconductor substrate to be an isolation zone. process and
A thin second layer is formed on the bottom and side surfaces of the groove of the semiconductor substrate.
forming a channel stopper region only on the bottom surface of the trench and its vicinity by implanting impurity ions through the second silicon dioxide film on the bottom surface; a step of depositing a vapor-phase grown silicon dioxide film over the entire surface and then fluidizing the deposited film to fill the groove; and converting the deposited film on the semiconductor substrate into a film having a lower etching rate than the upper surface thereof. a step of etching the first silicon dioxide film until the etching rate is reached, a step of etching away the film with a low etching rate, and then etching away the first silicon dioxide film and at the same time etching the silicon dioxide film containing phosphorus to a corresponding height. A semiconductor device comprising the step of etching away a portion of the semiconductor substrate, thereby exposing the surface of the semiconductor substrate, and simultaneously bringing the upper surface of the phosphorus-containing silicon dioxide film in the groove substantially coincident with the surface of the substrate. manufacturing method.