JP4901300B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  The mesa type semiconductor device is known as a high breakdown voltage semiconductor device, and is manufactured by dividing a semiconductor wafer at a groove portion. As a method for manufacturing such a mesa type semiconductor device, a method for manufacturing a semiconductor device including a step of providing a channel stopper on the bottom surface of a groove is known (for example, see Patent Documents 1 and 2). According to such a method for manufacturing a semiconductor device, it is possible to further increase the breakdown voltage of the mesa semiconductor device.

  FIG. 6 is a diagram for explaining the method of manufacturing the semiconductor device described in Patent Document 1. In FIG. FIG. 6A to FIG. 6E are diagrams showing each step.

As shown in FIG. 6, the method for manufacturing a semiconductor device described in Patent Document 1 includes an n-type semiconductor layer preparation step (see FIG. 6A) for preparing an n-type semiconductor layer 801, and an n-type semiconductor layer. A channel stopper forming step (see FIG. 6B) for forming an n ⁺ -type channel stopper 806 around an element formation region (not shown) on the first main surface 801, and an n-type semiconductor layer 801 A p-type epitaxial layer forming step (see FIG. 6C) for forming a p-type epitaxial layer 802 on the first main surface side, and etching the p-type epitaxial 802 layer from the first main surface side to form a channel stopper 806. A groove forming step for forming the reaching groove 811 (see FIG. 6D), a passivation film forming step for forming a passivation film 805a inside the groove 811 (not shown), and a portion of the groove 811 And cutting the body unit and a dividing step of chips (see FIG. 6 (e).) In this order.

  FIG. 7 is a diagram for explaining the method of manufacturing the semiconductor device described in Patent Document 2. In FIG. Fig.7 (a)-FIG.7 (f) are figures which show each process.

As shown in FIG. 7, the method for manufacturing a semiconductor device described in Patent Document 2 includes an n-type semiconductor layer preparation step (not shown) for preparing an n-type semiconductor layer 911, and an n-type semiconductor layer 911 first process. element forming region in one major surface (not shown.) n ⁺ type forming the n ⁺ -type diffusion layer 912 on the second main surface side of the n-type semiconductor layer 911 to form a n ⁺ -type diffusion layer 925 around the diffusion layer forming step (see FIG. 7 (a).) and, n-type semiconductor layer 911 p ⁺ -type diffusion layer forming step of the first main surface side to form a p ⁺ -type diffusion layer 913 (see FIG. 7 (b) And p ⁺ type diffusion layer 913 and n type semiconductor layer 911 are etched from the first main surface side to form groove 916 and channel stopper 918 forming step (FIG. 7C). And a passivation film 917 is formed inside the groove 916. That a passivation film forming step (see FIG. 7 (d).), P + -type diffusion layer 913 of the surface and the n ⁺ -type are formed respectively electrodes 915 and the electrode 914 on the surface of the diffusion layer 912 electrode forming step (FIG. 7 ( e), and a dividing step (see FIG. 7F) for dividing the semiconductor device into a chip at the groove 916 in this order.

  According to the manufacturing method of the semiconductor device described in Patent Document 1 or the manufacturing method of the semiconductor device described in Patent Document 2, it is possible to provide a channel stopper on the bottom surface of the groove in the mesa type semiconductor device. Even when the depletion layer of the pn junction spreads at a high voltage, the depletion layer is terminated by the channel stopper and is not exposed to the cross section of the chip. As a result, the withstand voltage of the mesa semiconductor device can be further increased. In addition, it is not necessary to form a deep groove so that the depletion layer is not exposed to the cross section of the chip, and it becomes possible to suppress the occurrence of chipping and cracking, and to improve the reliability of the semiconductor device. It becomes possible.

Japanese Patent Laid-Open No. 9-8274 (FIG. 2) JP 63-313859 A (Fig. 5)

However, in the method for manufacturing a semiconductor device described in Patent Document 1 or the method for manufacturing a semiconductor device described in Patent Document 2, a mask forming process for forming a channel stopper is separately required, and the process is complicated. There is a problem of becoming.
Further, in the method of manufacturing a semiconductor device described in Patent Document 1 or the method of manufacturing a semiconductor device described in Patent Document 2, when forming a groove, a channel stopper is appropriately exposed on the bottom surface of the groove. There is also a problem that a precise etching technique is required.

  Therefore, the present invention has been made to solve these problems, and is a method for manufacturing a semiconductor device for manufacturing a mesa type semiconductor device in which a channel stopper is provided on the bottom surface of a groove. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not require the mask forming step and does not require a precise etching technique when forming a groove.

(1) A method of manufacturing a semiconductor device according to the present invention includes a first semiconductor layer of a first conductivity type, and a conductivity type opposite to the first conductivity type, which is disposed on the first main surface side of the first semiconductor layer. A semiconductor substrate preparatory step for preparing a semiconductor substrate comprising a second semiconductor layer of a second conductivity type and having a pn junction formed at a junction between the first semiconductor layer and the second semiconductor layer; A groove forming step of forming a groove having a depth exceeding the pn junction from the first main surface side, an impurity supplying step of supplying at least a first conductivity type impurity to the bottom surface of the groove, and a laser on the bottom surface of the groove A channel stopper forming step of forming a channel stopper by diffusing the first conductivity type impurity into the first semiconductor layer by irradiating light, and a passivation layer forming step of forming a passivation layer in the trench And including And wherein the door.

Therefore, according to the method for manufacturing a semiconductor device of the present invention, since the channel stopper is formed on the bottom surface of the groove, it is possible to manufacture a mesa type semiconductor device having a channel stopper on the bottom surface of the groove. Become.
Further, according to the method for manufacturing a semiconductor device of the present invention, the first conductivity type impurity is irradiated to the first semiconductor by irradiating the bottom surface of the groove in a state where the first conductivity type impurity has been supplied in advance. Since the channel stopper is formed by diffusing inside the layer, the channel stopper can be formed by scanning the laser beam, and a mask formation step for forming the channel stopper is not necessary.
Further, according to the method for manufacturing a semiconductor device of the present invention, since the channel stopper is formed after the groove is formed, a precise etching technique is not required when the groove is formed.
As a result, the semiconductor device manufacturing method of the present invention is a semiconductor device manufacturing method for manufacturing a mesa-type semiconductor device in which a channel stopper is provided on the bottom surface of a groove, and includes a mask forming step for forming the channel stopper. This is a method for manufacturing a semiconductor device which does not require a precise etching technique when forming a groove.

  In the method for manufacturing a semiconductor device of the present invention, a visible laser (for example, a green laser) or a near infrared laser (for example, an Nd-YAG laser) can be used as the laser. It is particularly preferable to use an optical laser.

Since the visible light laser has a low light transmittance and a high light absorption rate with respect to a semiconductor substrate made of Si, SiC, etc., the above method facilitates control when heating the first semiconductor layer. The channel stopper can be formed by diffusing impurities of the first conductivity type inside the first semiconductor layer without evaporating the one semiconductor layer itself.
The laser irradiation conditions such as the power of the laser beam to be irradiated, the beam diameter, the aperture angle, and the irradiation method (pulse or continuous) do not evaporate the first semiconductor layer itself, but the first conductivity type impurity is removed from the first semiconductor layer. The channel stopper is appropriately set so that the channel stopper can be formed by diffusing inside.

  In the method for manufacturing a semiconductor device of the present invention, it is preferable that an etching process for removing the remaining first conductivity type impurities is further included between the channel stopper forming process and the passivation layer forming process.

By adopting such a method, the inner surface of the groove can be cleaned, and the mesa semiconductor device can be further increased in breakdown voltage and highly reliable.
As the etching solution, a mixed solution of hydrofluoric acid, nitric acid, and water (for example, HF: HNO ₃ : H ₂ O = 3: 2: 60) can be preferably used.

The amount of the first conductivity type impurity supplied to the bottom surface of the groove is adjusted so that the impurity concentration in the channel stopper formed on the bottom surface of the groove becomes an optimum concentration (for example, 1 × 10 ¹⁹ cm ⁻³ ).

  The impurity concentration, diffusion profile, and the like of the first conductivity type impurity in the channel stopper are such that even when the depletion layer of the pn junction spreads at a high voltage, the depletion layer does not terminate at the channel stopper and is exposed to the chip cross section. Adjust as follows.

  In the method for manufacturing a semiconductor device of the present invention, a third semiconductor layer containing a first conductivity type impurity at a higher concentration than the first semiconductor layer is further provided on the second main surface side of the first semiconductor layer as a semiconductor substrate. A semiconductor substrate provided can also be used.

  Semiconductor devices to which the method for manufacturing a semiconductor device of the present invention can be applied include diodes (for example, pn diodes, pin diodes, Schottky diodes, etc.), transistors (for example, bipolar transistors, MOSFETs, IGBTs, etc.), thyristors, triacs. Other power semiconductor devices can be exemplified.

  In this specification, the first main surface refers to the surface on the side where the groove is formed. In addition, the second main surface refers to a surface opposite to the first main surface.

(2) In the method for manufacturing a semiconductor device of the present invention, it is preferable that the impurity supplying step is a step of applying a liquid containing a first conductivity type impurity to at least a bottom surface of the groove.

By adopting such a method, it is possible to supply an appropriate amount of the first conductivity type impurity to the bottom surface of the groove.
As the liquid containing the first conductivity type impurities, for example, a liquid in which a phosphorus compound (for example, pyrophosphoric acid) is dissolved in an organic solvent (for example, ethanol) can be preferably used. As a coating method, a known method such as a dipping method, a spinner method, or a spray method can be used.

(3) In the method for manufacturing a semiconductor device of the present invention, the impurity supply step may be a step of supplying a gas containing a first conductivity type impurity at least on the bottom surface of the groove.
By adopting such a method, the first conductivity type impurity can be supplied to the bottom surface of the groove.
As the gas containing the first conductivity type impurity, for example, a mixed gas of phosphine and an inert gas can be preferably used. As a supply method, a method of exposing a semiconductor wafer to the atmosphere of the gas can be used.

(4) In the method for manufacturing a semiconductor device of the present invention, it is preferable that two channel stoppers extending along the groove are formed as the channel stopper in the channel stopper forming step.

By the way, it is generally known that chipping or cracking of chips is likely to occur when a portion where media having different hardnesses are joined by dicing. Accordingly, if the portion where the channel stopper and the first semiconductor layer are joined is divided by dicing, the hardness of the channel stopper and the hardness of the first semiconductor layer are different, and chipping and cracking are likely to occur. Is done.
On the other hand, by adopting the method as described above, if the portion between the two channel stoppers is divided in the subsequent semiconductor substrate dividing step, the portion where the channel stopper and the first semiconductor layer are joined. Therefore, chipping and cracking of the chip can be suppressed, and a highly reliable semiconductor device can be manufactured.

In the method for manufacturing a semiconductor device of the present invention, it is preferable to form two channel stoppers separated by 30 μm or more.
By adopting such a method, it is possible to easily divide the two channel stoppers in the subsequent semiconductor substrate dividing step.

(5) In the method for manufacturing a semiconductor device of the present invention, a semiconductor substrate dividing step of dividing the semiconductor substrate between two channel stoppers extending along the groove is further provided after the passivation layer forming step. It is preferable to include.

  By adopting such a method, it becomes possible to manufacture a mesa-type semiconductor device with high breakdown voltage and high reliability.

(6) In the method of manufacturing a semiconductor device of the present invention, in the channel stopper forming step, as the channel stopper, a channel stopper that surrounds the element forming region between the element forming region and the dicing line in the semiconductor device. It is also preferable to form

  Even by adopting such a method, the portion where the channel stopper and the first semiconductor layer are joined is not divided, so that chip chipping and cracking can be suppressed, and high reliability can be achieved. A semiconductor device can be manufactured.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the channel stopper is arranged at a distance of 15 μm or more from the dicing line.
By adopting such a method, it is possible to prevent the occurrence of a situation in which the channel stopper is exposed on the chip end face.

  A method for manufacturing a semiconductor device according to the present invention will be described below based on the embodiments shown in the drawings.

[Embodiment 1]
FIG. 1 is a view for explaining a semiconductor device 100 manufactured by the method of manufacturing a semiconductor device according to the first embodiment. 1A is a cross-sectional view of the semiconductor device 100, FIG. 1B is an enlarged view of a portion indicated by reference numeral A in FIG. 1A, and FIG. 1C is a cross-sectional view of FIG. FIG. 4 is an enlarged view of a portion indicated by reference sign B. 2 and 3 are views for explaining the method of manufacturing the semiconductor device according to the first embodiment. 2A to 2C and FIGS. 3A to 3C are cross-sectional views of the semiconductor device 100a in each step. FIG. 4 is a view for explaining the semiconductor substrate cutting step in the first embodiment. 4A is a plan view of the semiconductor device 100a before being divided, FIG. 4B is a cross-sectional view of the semiconductor device 100a before being divided, and FIG. 4C is a semiconductor device after being divided. FIG.

  A semiconductor device 100 manufactured by the method for manufacturing a semiconductor device according to the first embodiment is a semiconductor device in which a channel stopper 22 is provided on the bottom surface of the groove 18 as shown in FIG.

The semiconductor device 100 includes an n ⁻ type (first conductivity type) first semiconductor layer 10 and a p ⁺ type (second conductivity type) second semiconductor disposed on the first main surface side of the first semiconductor layer 10. A layer 12 and an n ⁺ -type (first conductivity type) third semiconductor layer 14 disposed on the second main surface side of the first semiconductor layer 10, and the first semiconductor layer 10, the second semiconductor layer 12, A semiconductor substrate in which a pn junction is formed at the junction is manufactured as a starting material (see FIG. 2A).

The semiconductor device 100 has a groove 18 having a depth exceeding the pn junction. Two channel stoppers 22 and 22 extending along the groove 18 are formed on the bottom surface of the groove 18 (see FIGS. 1 and 4A).
The width of the groove 18 is, for example, 300 μm, the width of the channel stopper 22 is, for example, 60 μm, and the distance d between the two channel stoppers 22 (see FIG. 1B) is, for example, 60 μm.

The channel stopper 22 is formed by diffusing the n-type impurity 20 into the first semiconductor layer 10 by irradiating the bottom surface of the groove 18 to which the n-type impurity 20 has been supplied in advance with laser light. (Refer to FIG. 2C for n-type impurities).
As shown in FIG. 1C, the channel stopper 22 includes a single crystal region 26 containing a high concentration n-type impurity and an amorphous region 24 containing a high concentration n-type impurity. Yes.

  As shown in FIGS. 1A and 1B, a passivation layer 28 is formed inside the groove 18.

  In FIG. 1, reference numeral 30 indicates an electrode formed on the surface of the second semiconductor layer, and reference numeral 32 indicates an electrode formed on the surface of the third semiconductor layer.

  The manufacturing method of the semiconductor device according to the first embodiment includes the following steps in this order as shown in FIGS. Hereinafter, each process is demonstrated one by one.

(1) Semiconductor substrate preparation step The semiconductor substrate preparation step includes an n ⁻ type first semiconductor layer 10, a p ⁺ type second semiconductor layer 12 disposed on the first main surface side of the first semiconductor layer 10, And an n ⁺ -type third semiconductor layer 14 disposed on the second main surface side of the first semiconductor layer 10, and a pn junction is formed at the junction between the first semiconductor layer 10 and the second semiconductor layer 12. This is a step of preparing a semiconductor substrate (see FIG. 2A). The impurity concentration of the first semiconductor layer 10 is, for example, 2 × 10 ¹⁴ cm ⁻³ , the impurity concentration of the second semiconductor layer 12 is, for example, 2 × 10 ¹⁹ cm ⁻³ , and the impurity concentration of the third semiconductor layer 14 is, for example, 2 × 10 ¹⁹ cm ⁻³ . Further, the thickness of the first semiconductor layer 10 is, for example, 150 μm, the thickness of the second semiconductor layer 12 is 60 μm, and the thickness of the third semiconductor layer 14 is 40 μm.

(2) Groove Forming Step The groove forming step is a step of forming the groove 18 having a depth exceeding the pn junction from the first main surface side in the semiconductor substrate (see FIG. 2B). The width of the groove 18 is, for example, 300 μm, and the depth of the groove 18 is, for example, 90 μm. The groove is formed by etching, for example. As an etchant, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid (for example, HF: HNO ₃ : CH ₃ COOH = 1: 4: 1) is used.

(3) Impurity supply step The impurity supply step is a step of applying a liquid containing the n-type impurity 20 to at least the bottom surface of the groove 18 (see FIG. 2C).
As the liquid containing the n-type impurity 20, for example, a liquid obtained by dissolving a phosphorus compound (for example, pyrophosphoric acid) in an organic solvent (for example, ethanol) can be preferably used. As a coating method, a known method such as a dipping method, a spinner method, or a spray method can be used.

The amount of the n-type impurity 20 supplied to the bottom surface of the groove 18 is adjusted so that the impurity concentration in the channel stopper 22 formed on the bottom surface of the groove 18 becomes an optimum concentration (for example, 1 × 10 ¹⁹ cm ⁻³ ). To do.

(4) Channel stopper forming step The channel stopper forming step is a step of forming the channel stopper 22 by diffusing the n-type impurity 20 into the first semiconductor layer 10 by irradiating the bottom surface of the groove 18 with laser light. Yes (see FIG. 3A).

  As the laser light, a visible light laser (for example, a green laser having a wavelength of 532 nm) is used. For example, pulse oscillation is performed at 30 KHz, and scanning along the x direction and the y direction is performed along the groove 18 at a speed of 300 mm / second.

  In this step, two channel stoppers 22 and 22 extending along the groove 18 are formed as the channel stopper 22 (see FIG. 4A). The two channel stoppers 22 are formed 60 μm apart from each other.

(5) Etching Step The etching step is a step of removing the remaining n-type impurity 20 (see FIG. 3B).

As an etchant, a mixed solution of hydrofluoric acid, nitric acid, and water (for example, HF: HNO ₃ : H ₂ O = 3: 2: 60) is used.

(6) Passivation layer formation process A passivation layer formation process is a process of forming the passivation layer 28 in the inside of the groove | channel 18 (refer FIG.3 (c)). This step is performed by printing and baking a glass material using a screen printing method.

(7) Electrode Formation Step The electrode formation step is a step of forming the electrode 30 and the electrode 32 on the first main surface side of the second semiconductor layer 12 and the second main surface side of the third semiconductor layer 14 (not shown). ). The oxide film 16 shown in FIG. 3C is removed by etching before the electrode formation step.

(8) Semiconductor substrate cutting step The semiconductor substrate cutting step is performed by dicing along a dicing line DL shown in FIG. 4A using a dicing saw. Dicing is performed between the two channel stoppers 22 and 22.

  According to the manufacturing method of the semiconductor device according to the first embodiment including the steps as described above, since the channel stopper 22 is formed on the bottom surface of the groove 18, the mesa type having the channel stopper provided on the bottom surface of the groove is used. The semiconductor device 100 can be manufactured.

  Further, according to the method of manufacturing a semiconductor device according to the first embodiment, the first n-type impurity 20 is removed by irradiating the bottom surface of the groove 18 in a state where the n-type impurity 20 has been supplied in advance with laser light. Since the channel stopper 22 is formed by diffusing inside the semiconductor layer 10, the channel stopper 22 can be formed by scanning with laser light, and a mask formation step for forming the channel stopper is not required. It becomes.

  In addition, according to the method for manufacturing a semiconductor device according to the first embodiment, the channel stopper 22 is formed after the groove 18 is formed, so that a precise etching technique is not required when the groove 18 is formed.

  As a result, the manufacturing method of the semiconductor device according to the first embodiment is a manufacturing method of a semiconductor device for manufacturing a mesa type semiconductor device in which a channel stopper is provided on the bottom surface of a groove, and a mask formation for forming the channel stopper is performed. This is a method for manufacturing a semiconductor device that does not require a process and does not require a precise etching technique when forming a groove.

  In the method for manufacturing the semiconductor device according to the first embodiment, since a visible light laser is used as the laser beam, the control when heating the first semiconductor layer 10 is facilitated, and the first semiconductor layer 10 itself. The channel stopper 22 can be formed by diffusing the n-type impurity 20 into the first semiconductor layer 10 without evaporating the substrate.

  Further, in the method of manufacturing the semiconductor device according to the first embodiment, an etching process for removing the remaining n-type impurity 20 is further included between the channel stopper forming process and the passivation layer forming process. The inner surface of 18 can be cleaned, and the mesa-type semiconductor device can be further increased in breakdown voltage and improved in reliability.

  In the method for manufacturing the semiconductor device according to the first embodiment, the impurity supply step is a step of applying a liquid containing n-type impurity 20 to at least the bottom surface of the groove 18, so that an appropriate amount of n is applied to the bottom surface of the groove 18. The type impurity 20 can be supplied.

  In the semiconductor device manufacturing method according to the first embodiment, in the channel stopper forming step, two channel stoppers 22 and 22 extending along the groove 18 are formed as channel stoppers. If the gap between the two channel stoppers 22 and 22 is divided in the semiconductor substrate dividing step, the portion where the channel stopper 22 and the first semiconductor layer 10 are joined is not divided. Generation of cracks and cracks can be further suppressed, and a highly reliable semiconductor device can be manufactured.

  In the method for manufacturing the semiconductor device according to the first embodiment, since the two channel stoppers 22 and 22 are formed separated by 60 μm, the two channel stoppers 22 and 22 are separated in the subsequent semiconductor substrate cutting step. 22 can be easily divided.

  In the method of manufacturing the semiconductor device according to the first embodiment, after the passivation layer forming step, a semiconductor substrate dividing step of dividing the semiconductor substrate between the two channel stoppers 22 and 22 extending along the groove 18 is further performed. Therefore, a mesa-type semiconductor device having a high withstand voltage and high reliability can be manufactured.

[Embodiment 2]
The semiconductor device manufacturing method according to the second embodiment basically includes the same steps as the semiconductor device manufacturing method according to the first embodiment, but the impurity supply step is the semiconductor device manufacturing method according to the first embodiment. Is different. In other words, in the method for manufacturing a semiconductor device according to the second embodiment, the impurity supply step is a step of supplying a gas containing n-type impurities at least on the bottom surface of the trench.

  As described above, the method for manufacturing the semiconductor device according to the second embodiment differs from the method for manufacturing the semiconductor device according to the first embodiment in the impurity supply process. As in the case of the method for manufacturing a semiconductor device according to the present invention, it is possible to supply n-type impurities to the bottom surface of the groove. For this reason, the semiconductor device manufacturing method according to the second embodiment also manufactures a mesa semiconductor device in which a channel stopper is provided on the bottom surface of the groove, as in the case of the semiconductor device manufacturing method according to the first embodiment. This is a method for manufacturing a semiconductor device that does not require a mask formation step for forming a channel stopper and does not require a precise etching technique when forming a groove.

  In the method for manufacturing the semiconductor device according to the second embodiment, as the gas containing n-type impurities, for example, a mixed gas of phosphine and an inert gas can be preferably used. As a supply method, a method of exposing a semiconductor wafer to the atmosphere of the gas can be used.

  Since the semiconductor device manufacturing method according to the second embodiment has the same steps as the semiconductor device manufacturing method according to the first embodiment except for the above points, the semiconductor device manufacturing method according to the first embodiment is the same as the semiconductor device manufacturing method according to the first embodiment. It has a corresponding effect among the effects it has.

[Embodiment 3]
FIG. 5 is a view for explaining the semiconductor substrate cutting step in the third embodiment. FIG. 5 shows a plan view of the semiconductor device 104a before dividing, as in the case of FIG.

  The manufacturing method of the semiconductor device according to the third embodiment basically includes the same steps as the manufacturing method of the semiconductor device according to the first embodiment, but the planar shape of the channel stopper is the manufacturing method of the semiconductor device according to the first embodiment. This is not the case. That is, in the semiconductor device manufacturing method according to the third embodiment, as shown in FIG. 5, the channel stopper 22 is formed between the element formation region 34 and the dicing line DL so as to surround the element formation region 34. ing.

  As described above, the semiconductor device manufacturing method according to the third embodiment differs from the semiconductor device manufacturing method according to the first embodiment in that the planar shape of the channel stopper is different from that of the semiconductor device manufacturing method according to the first embodiment. Similarly to the method, the channel stopper 22 is formed by diffusing the n-type impurity 20 into the first semiconductor layer 10 by irradiating the bottom surface of the groove 18 with laser light. As in the case of the semiconductor device manufacturing method according to the present invention, a semiconductor device manufacturing method for manufacturing a mesa type semiconductor device having a channel stopper on the bottom surface of a groove, comprising: a mask forming step for forming a channel stopper This is a method for manufacturing a semiconductor device which does not require a precise etching technique when forming a groove.

  Since the semiconductor device manufacturing method according to the third embodiment has the same steps as those of the semiconductor device manufacturing method according to the first embodiment in other points, the semiconductor device manufacturing method according to the first embodiment is the same as the semiconductor device manufacturing method according to the first embodiment. It has a corresponding effect among the effects it has.

  As mentioned above, although the manufacturing method of the semiconductor device of this invention was demonstrated based on said each embodiment, this invention is not limited to said each embodiment, In various aspects in the range which does not deviate from the summary. For example, the following modifications are possible.

(1) In each of the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, the present invention is not limited to this, and the first conductivity type is p-type. The second conductivity type may be n-type.

(2) In each of the above embodiments, a grain laser is used as the laser, but the present invention is not limited to this. As the laser, a visible light laser other than a green laser or a near-infrared light laser (for example, an Nd-YAG laser) can be preferably used.

(3) In Embodiment 1 described above, a liquid in which pyrophosphoric acid is dissolved in an organic solvent is used as the liquid containing n-type impurities, but the present invention is not limited to this. For example, a liquid in which a phosphorus compound other than pyrophosphate or an arsenic compound is dissolved in various organic solvents can be used.

(4) In each of the above embodiments, the present invention has been described by taking a pn diode as an example of a mesa semiconductor device, but the present invention is not limited to this. For example, the present invention can be applied to diodes other than pn diodes (eg, pin diodes, Schottky diodes, etc.), transistors (eg, bipolar transistors, MOSFETs, IGBTs, etc.), thyristors, triacs, and other power semiconductor devices. it can.

1 is a diagram for explaining a semiconductor device 100 according to a first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment. It is a figure shown in order to demonstrate the semiconductor substrate parting process in Embodiment 1. FIG. It is a figure shown in order to demonstrate the semiconductor substrate cutting process in Embodiment 3. FIG. 10 is a diagram shown for explaining the method for manufacturing the semiconductor device described in Patent Document 1. FIG. 10 is a view for explaining the method for manufacturing the semiconductor device described in Patent Document 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor layer, 12 ... 2nd semiconductor layer, 14 ... 3rd semiconductor layer, 16 ... Oxide film, 18 ... Groove, 20 ... N-type impurity, 22 ... Channel stopper, 24 ... Amorphous region, 26 ... single crystal region, 28 ... passivation layer, 30, 32 ... electrode, 34 ... element formation region, 100 ... semiconductor device (after chip formation), 100a, 104a ... semiconductor device (before chip formation), 801 ... n-type semiconductor layer (collector region), 801a... n ⁺ type semiconductor layer, 801b... n ⁻ type semiconductor layer, 802... p-type epitaxial layer (base region), 803... emitter region, 805. , 806, channel stopper, 807, collector electrode, 808, base electrode, 809, emitter electrode, 810, pn junction, 811, groove, 812, depletion layer, 813, acid. ,...,... Opening, 911... N-type semiconductor layer, 912 and 925... N ⁺ -type diffusion layer, 913... P ⁺ -type diffusion layer, 914 and 915. Channel stopper, 926, 928 ... oxide film, DL ... dicing line

Claims (6)

A first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer disposed on the first main surface side of the first semiconductor layer and having a conductivity type opposite to the first conductivity type, A semiconductor substrate preparation step of preparing a semiconductor substrate in which a pn junction is formed at a junction between the first semiconductor layer and the second semiconductor layer;
A groove forming step of forming a groove having a depth exceeding the pn junction from the first main surface side in the semiconductor substrate;
An impurity supply step of supplying an impurity of the first conductivity type to at least the bottom surface of the groove;
A channel stopper forming step of diffusing the first conductivity type impurities into the first semiconductor layer by irradiating the bottom surface of the groove with a laser beam to form a channel stopper;
And a passivation layer forming step of forming a passivation layer inside the groove. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the impurity supplying step is a step of applying a liquid containing a first conductivity type impurity at least on the bottom surface of the groove. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the impurity supply step is a step of supplying a gas containing a first conductivity type impurity to at least a bottom surface of the groove. In the manufacturing method of the semiconductor device in any one of Claims 1-3,
In the channel stopper forming step, as the channel stopper, two channel stoppers extending along the groove are formed. In the manufacturing method of the semiconductor device according to claim 4,
After the passivation layer forming step,
A method of manufacturing a semiconductor device, further comprising a semiconductor substrate dividing step of dividing the semiconductor substrate between two channel stoppers extending along the groove. In the manufacturing method of the semiconductor device in any one of Claims 1-3,
In the channel stopper forming step, a channel stopper is formed as the channel stopper so as to surround the element forming region between the element forming region and the dicing line in the semiconductor device. .

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