CN112133743A - Silicon controlled rectifier structure and manufacturing method thereof - Google Patents

Abstract

A silicon controlled structure and its manufacturing method, including mesa ditch groove and surrounding the protective layer located at mesa ditch groove bottom, surround the doping type of the protective layer for N type doping or P type doping corresponding to base region doping type, and surround the doping concentration of the protective layer and is greater than the doping concentration of the base region, because the too wide mesa width in the mesa type silicon controlled device has influenced the area of the silicon controlled device passthrough area of the area, through setting up surrounding the protective layer in the end that the corrosion removes, surround the protective layer for the diffusion layer of the high concentration, the diffusion layer of this high concentration can compress the electric field in the widening of the low doping area, thus can narrow the width of the mesa, thus improve the utilization factor of the effective area of the crystal circle, in order to achieve the purpose to reduce the device manufacturing cost.

Description

SCR structure and manufacturing method thereof

technical field

The invention relates to the field of power semiconductor devices, in particular to a thyristor structure and a manufacturing method thereof.

Background technique

SCRs are widely used in AC non-contact switches, household appliance control circuits, industrial control and other fields.

At present, the production of thyristor products mainly adopts the mesa process. The process flow is such as: growing a masked oxide layer on a wafer with a maximum size of 4 inches, and then performing isolation and penetration diffusion on it, and then performing diffusion in the base area and the emission area; emission; After the area is completed, a groove with a depth of more than 50 μm and a width of more than 150 μm needs to be etched between the front isolation and the base area. A layer of glass glue is manually coated in the groove, and a protective layer is formed after high temperature sintering. Finally, the aluminum layer is completed. And the back side process to form a 4-layer PNPN structure thyristor. Since the trenches that need to be etched in the mesa process generally have a depth of more than 50 μm and a width of more than 150 μm, the wider the width, the smaller the leakage current in the mesa, the purpose is to play a role in sufficient withstand voltage protection, but it will cause the surface width of the mesa to be too high. The width of the device affects the flow area of the device, which reduces the number of devices that can be fabricated on the same large wafer, that is, the utilization rate of the device is reduced, and the cost of device fabrication is increased.

Therefore, it is necessary to provide a thyristor device structure, which can improve the utilization rate of the wafer area and reduce the device manufacturing cost.

SUMMARY OF THE INVENTION

The invention provides a silicon controlled device structure, which can improve the utilization rate of the wafer area and reduce the width of the mesa, thereby improving the utilization rate of the wafer area, so as to achieve the purpose of reducing the manufacturing cost of the device.

According to a first aspect, an embodiment provides a thyristor structure, including:

a base region, the base region is N-type doped or P-type doped, the base region has a first surface and a second surface opposite to the first surface;

a first implantation region, located on the first surface of the base region, the first implantation region is corresponding to the doping type of the base region, and is P-type doping or N-type doping;

the second implantation region is located on the second surface of the base region, and the second implantation region corresponds to the doping type of the base region, and is P-type doping or N-type doping;

a third implantation region, located on a part of the surface of the second implantation region, the doping type of the third implantation region corresponds to the doping type of the second implantation region, and is N-type doping or P-type doping;

An anode electrode is arranged on the surface of the first injection area, a gate electrode is arranged on the surface of the remaining part of the second injection area, a cathode electrode is arranged on the surface of the third injection area, and the gate electrode is connected to the surface of the third injection area. insulation between the cathode electrodes;

a mesa trench, the mesa trench is arranged around the periphery of the gate electrode and the cathode electrode, or is arranged around the periphery of the anode electrode, and the depth of the mesa trench extends into the base area;

and a surrounding protective layer at the bottom of the mesa trench, the doping type of the surrounding protective layer is the same as the doping type of the base region, which is N-type doping or P-type doping, and the surrounding protective layer is The doping concentration of is greater than the doping concentration of the base region.

In some embodiments, the doping concentration and depth of the surrounding protective layer are the same as the concentration and depth of the third implantation region.

In some embodiments, the mesa trench further has a passivation layer.

In some embodiments, the third implanted region has multiple short-circuit points.

According to a second aspect, an embodiment provides a method for manufacturing a thyristor structure, including:

A suitable silicon wafer is selected, and a chip area and an isolation area are defined, the silicon wafer is of a first doping type, the first doping type is N-type doping or P-type doping, and the silicon wafer has the first doping type. a surface and a second surface opposite the first surface;

A diffusion process of a second doping type is performed on the first surface and the second surface of the silicon wafer, where the second doping type is P-type doping or N-type doping corresponding to the first doping type, to A first implantation region is formed in the first surface of the silicon wafer, a second implantation region is formed in the second surface of the silicon wafer, and a base region is formed between the first implantation region and the second implantation region ;

etching the defined isolation region to the bottom of the base region to form a mesa trench, and two adjacent chip regions share a mesa trench;

A patterned oxide layer is formed on part of the surface of the mesa trench, the surface of the first implantation region and the part of the surface of the second implantation region, and the patterned oxide layer exposes the window of the third implantation region and the surrounding protective layer a window; the third injection area window is located on a part of the surface of the second injection area, and the surrounding protective layer window is located at the bottom of the mesa trench;

Using the patterned oxide layer as a mask, a first doping type diffusion process is performed on the silicon wafer, and the diffusion concentration is greater than the doping concentration of the base region, so that a part of the surface of the second implantation region is forming a third implantation region, and forming a surrounding protective layer at the bottom of the mesa trench;

Electrode pins are respectively formed on the surface of the first injection region, the surface of the second injection region and the surface of the third injection region, and each electrode pin is insulated and isolated.

In some embodiments, forming a patterned oxide layer on the surface of the mesa trench, the surface of the first implantation region and the surface of the second implantation region includes:

covering the surface of the mesa trench, the surface of the first implantation region and the surface of the second implantation region with an oxide layer;

A patterned photoresist layer is formed on the surface of the oxide layer, and the patterned photoresist layer exposes the third injection area window and the surrounding protective layer window; the third injection area window is located on a part of the surface of the second injection area , the surrounding protective layer window is located at the bottom of the mesa groove;

Using the patterned photoresist layer as a mask, the oxide layer is etched to transfer the pattern of the patterned photoresist into the oxide layer to form a patterned oxide layer.

In some embodiments, using the patterned oxide layer as a mask, after performing the diffusion process of the first doping type on the silicon wafer, the method further includes the step of removing the patterned oxide layer with hydrofluoric acid.

In some embodiments, after using hydrofluoric acid to remove the patterned oxide layer, the method further includes the step of: performing a passivation treatment process on the surface of the mesa trench to form a passivation layer.

In some embodiments, the method further includes: performing an enhanced diffusion process on the surface of the first implanted region, and the enhanced diffusion treatment has a diffusion type that is the same as the doping type of the first implanted region, so that the doping concentration is greater than that of the first implanted region. An enhanced region of concentration of the first implanted region.

In some embodiments, the method further includes: controlling the doping concentration of the surrounding protective layer; controlling the doping concentration of the surrounding protective layer includes: controlling the sheet resistance of the diffusion co-plate to be less than 10.

The thyristor structure and the manufacturing method thereof according to the above-mentioned embodiments include a surrounding protective layer at the bottom of the mesa trench, and the doping type of the surrounding protective layer is N-type doping or P-type doping corresponding to the doping type of the base region. and the doping concentration of the surrounding protective layer is greater than that of the base region. Since the excessively wide mesa width in the mesa-type thyristor device affects the area of the flow area of the thyristor device, it is necessary to set it at the bottom of the mesa In order to surround the protective layer, the surrounding protective layer is a high-concentration diffusion layer, which can compress the expansion of the electric field in the low-doped region, because the withstand voltage is expanded in the base region, which can narrow the width of the mesa, thereby Improve the utilization of wafer area to achieve the purpose of reducing device manufacturing costs.

Description of drawings

FIG. 1 is a schematic structural diagram of a thyristor device provided in an embodiment of the present invention;

FIG. 2 is a top view of the structure of the thyristor device provided in an embodiment of the present invention;

3 is a flowchart of a method for manufacturing a thyristor provided in an embodiment of the present invention;

4 is a schematic diagram of a part of a structure in a manufacturing process provided by an embodiment of the present invention;

5 is a schematic diagram of a partial structure in a manufacturing process provided by an embodiment of the present invention;

6 is a schematic diagram of a partial structure in a manufacturing process provided by an embodiment of the present invention;

7 is a schematic diagram of a part of a structure in a manufacturing process provided in an embodiment of the present invention;

8 is a schematic diagram of a partial structure in a manufacturing process provided in an embodiment of the present invention;

FIG. 9 is a schematic diagram of a partial structure in a manufacturing process provided in an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a part of a manufacturing process provided in an embodiment of the present invention.

Detailed ways

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments have used associated similar element numbers. In the following embodiments, many details are described so that the present application can be better understood. However, those skilled in the art will readily recognize that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application from being overwhelmed by excessive description, and for those skilled in the art, these are described in detail. The relevant operations are not necessary, and they can fully understand the relevant operations according to the descriptions in the specification and general technical knowledge in the field.

Additionally, the features, acts, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in order in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary order unless otherwise stated, a certain order must be followed.

The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "connection" mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).

It can be seen from the analysis that a part of the PN junction depletion layer is generally removed by etching to reduce the surface electric field, so that the voltage resistance of the device is good. However, the mesa trench formed by removing a part will be affected by the excessively wide surface width. The use area of the device pass-through area.

In the thyristor device structure in the embodiment of the present invention, a surrounding protective layer at the bottom of the mesa trench is included, and the doping type of the surrounding protective layer is N-type doping or P-type doping corresponding to the doping type of the base region The doping concentration of the surrounding protective layer is greater than that of the base region. Because the excessively wide mesa width in the mesa-type thyristor device affects the area of the flow area of the thyristor device, it is removed by etching at the end of the device. A surrounding protective layer is provided, and the surrounding protective layer is a high-concentration diffusion layer. The high-concentration diffusion layer can compress the expansion of the electric field in the low-doped region, thereby narrowing the width of the mesa, thereby improving the utilization rate of the effective area of the wafer. , in order to achieve the purpose of reducing device manufacturing cost.

Referring to FIG. 1 and FIG. 2 , an embodiment of the present invention provides a thyristor structure, including a base region 100 , a first implantation region 101 , a second implantation region 102 , a third implantation region 103 , and the first implantation region 102 The anode electrode 210 on the surface, the gate electrode 230 on a part of the surface of the second implantation region 102 and the cathode electrode 220 on the surface of the third implantation region 103 also include: a mesa trench 300 and a bottom portion of the mesa trench 300 the surrounding protective layer 310.

The base region 100 is P-type doped or N-type doped, and the base region 100 has a first surface and a second surface opposite to the first surface.

In this embodiment, the base region is an N-type doped silicon substrate.

The first implantation region 101 is located on the first surface of the base region 100 , and the first implantation region 101 is N-type doped or P-type doped corresponding to the doping type of the base region 100 . For example, since the base region in this embodiment is N-type doped, the first implantation region 101 is P-type doped.

In some embodiments, the doping of the first implantation region 101 may be heavy doping, which can be understood as the concentration of the heavy doping is that the doping concentration is greater than the concentration of the P-type doping in the base region 100 . For example, in this embodiment, the first implantation region 101 is an expanded P ⁺ region, that is, a high-concentration P-type doped region.

The second implantation region 102 is located on the second surface of the base region 100 , and the second implantation region 102 is N-type doped or P-type doped corresponding to the doping type of the base region 100 . For example, since the base region in this embodiment is N-type doped, the second implantation region 102 is the same as the first implantation region 101, and both are P-type doped.

The third implantation region 103 is located on a part of the surface of the second implantation region 102 , and the third implantation region 103 is P-type or N-type doped corresponding to the doping type of the second implantation region 102 . For example, in this embodiment, the base region 100 is N-type doped, and the third implantation region 103 is correspondingly N-type doped.

In some embodiments, the N-type doping of the third implantation region 103 is heavy doping, and it can be understood that the concentration of heavy doping is that the doping concentration is greater than the doping concentration in the base region 100 . For example, in this embodiment, the third injection region is a high-concentration expanded N ⁺ region.

The anode electrode 210, the gate electrode 230 and the cathode electrode 220 are insulated from each other.

It should be noted that the surface of the first injection area 101, the surface of the second injection area 102 and the surface of the third injection area 103 have electrode pins 200, and each electrode pin is insulated and isolated, the anode electrode 210 , the gate electrode 230 and the cathode electrode 220 are respectively formed on the electrode pins 200 .

In this embodiment, the mesa trench 300 is disposed around the periphery of the gate electrode 230 and the cathode electrode 220 , or is disposed around the periphery of the anode electrode 210 , and the depth of the mesa trench 300 extends into in the base region 100 .

It should be noted that, in the wafer, there is a mesa between two defined adjacent chip regions 10 , and it can be understood that two adjacent chip regions 10 share one mesa trench 300 .

The doping type of the surrounding protective layer 310 is N-type doping or P-type doping corresponding to the doping type of the base region 100 , and the doping concentration of the surrounding protective layer 310 is greater than that of the base region 100 . doping concentration.

In this embodiment, since the doping type of the base region 100 is N-type, the doping type of the surrounding protection layer 310 is N-type. Moreover, the surrounding protection layer 310 is an expanded N ⁺ region, that is, a high-concentration N-type doping region.

In this embodiment, by adding a surrounding protective layer 310 at the bottom of the mesa trench (that is, the mesa) at the interface of the PN junction, that is, a high-concentration N ⁺ diffusion layer, the N ⁺ diffusion layer can shorten the electric field in the low-doped region. At the same time, the high-concentration N ⁺ diffusion layer can neutralize and absorb surface charges, so that the mesa leakage current of the device can be reduced, and the withstand voltage characteristics of the device can be further improved.

In some embodiments, the sheet resistance of the doping concentration N+ diffusion surrounding the protective layer is preferably less than 10 Å.

In this embodiment, the surface of the mesa trench 300 further has a passivation layer, and the passivation layer is silicon dioxide.

In some embodiments, the third injection region 103 has a plurality of short-circuit points 500, and the short-circuit points 500 are a component of the third injection region, and its function is to directly short-circuit the third injection region 103 when testing the blocking voltage. , to improve the high temperature characteristics of the product.

In this embodiment, an insulating protective layer 400 is also provided on the periphery of the thyristor chip. The insulating protective layer 400 wraps the thyristor device and exposes the anode electrode 210, the gate electrode 230 and the cathode electrode 220. To protect the internal structure of the thyristor chip and improve the reliability and stability of the device.

Referring to FIG. 2 to FIG. 10 , in this embodiment, there is also a method for manufacturing a thyristor structure. The method is used to manufacture the thyristor structure described in the above embodiments. The steps of the method include:

Step 1, select a suitable silicon wafer, and define the chip region 10 and the isolation region, the silicon wafer is of a first doping type, the first doping type is N-type doping or P-type doping, the The silicon wafer has a first surface and a second surface opposite the first surface.

In this embodiment, a suitable N-type silicon wafer can be selected according to different withstand voltage requirements, and different resistivities can be selected; its thickness can be selected from 220 μm to 460 μm according to the design value of the withstand voltage of the wafer.

Step 2, performing a second doping type diffusion process on the first surface and the second surface of the silicon wafer.

The second doping type is P-type doping or N-type doping corresponding to the first doping type, so as to form a first implantation region 101 in the first surface of the silicon wafer, and in the silicon wafer A second implantation region 102 is formed in the second surface, and a base region is formed between the first implantation region 101 and the second implantation region 102 .

The front surface and the back surface of the silicon wafer are the first surface and the second surface respectively. In this embodiment, since the silicon wafer is N-type doped, the first implantation region 101 and the second implantation region 102 are both P-type doped miscellaneous.

In some embodiments, the doping of the second implantation region 102 can be further controlled to be heavily doped, and it can be understood that the concentration of the heavy doping is that the doping concentration is greater than the concentration of the P-type doping in the base region 100 . For example, in this embodiment, the second implantation region 102 is an expanded P ⁺ region, that is, a high-concentration P-type doped region.

In some embodiments, diffusion may be further performed on the surface of the first implantation region 101 to form an enhancement region, the enhancement region is a high-concentration expanded P ⁺ region, and the doping concentration of the high-concentration expanded P ⁺ region is heavy doping.

In some embodiments, the first implant region 101 can be directly controlled to be heavily doped. It can be understood that the concentration of the heavy doping is that the doping concentration is greater than the concentration of the P-type doping in the base region 100 . For example, in this embodiment, the first implantation region 101 is an expanded P ⁺ region, that is, a high-concentration P-type doped region.

In step 3, the defined isolation region is etched to the bottom of the base region 100 to form a mesa trench 300, and two adjacent chip regions share one mesa trench 300.

Please refer to FIG. 4 , which is a schematic diagram of the structure of the etched mesa trench 300 . The etching method may be dry etching or wet etching.

Step 4, a patterned oxide layer 320 is formed.

Please refer to FIG. 5 , a patterned oxide layer 320 is formed on part of the surface of the mesa trench 300 , the surface of the first implantation region 101 and the part of the surface of the second implantation region 102 . The patterned oxide layer 320 exposes the third injection region window and the surrounding protective layer window; wherein the third injection region window is located on a partial surface of the second injection region, and the surrounding protective layer window is located at the bottom of the mesa trench 300 .

In this embodiment, the patterned oxide layer 320 is silicon dioxide, and the thickness is 0.5um-2um.

In step 5, a third implantation region 103 is formed on a part of the surface of the second implantation region 102, and a surrounding protective layer 310 is formed on the bottom of the mesa trench 300. As shown in FIG.

Referring to FIG. 6 , using the patterned oxide layer 320 as a mask, a diffusion process of the first doping type is performed on the silicon wafer, and the diffusion concentration is greater than the doping concentration of the base region 100 , so that the first doping concentration is higher than that of the base region 100 . A third implantation region 103 is formed inside a part of the surface of the second implantation region 102 , and a surrounding protective layer 310 is formed at the bottom of the mesa trench 300 .

In this embodiment, the third implantation region 103 and the surrounding protective layer 310 are correspondingly N-type doped.

In this embodiment, the N-type doping of the third implantation region 103 is heavy doping, which can be understood as the concentration of the heavy doping is that the doping concentration is greater than the doping concentration in the base region 100 . For example, in this embodiment, the third injection region is a high-concentration expanded N ⁺ region.

It should be noted that in the manufacturing process, it is often necessary to control the diffusion concentration. In this embodiment, the method for controlling the diffusion concentration includes: controlling the diffusion of the silicon wafer by measuring the surface resistance of the companion wafer that is diffused into the furnace together with the silicon wafer. concentration. Correspondingly, in this embodiment, controlling the doping concentration of the ring protection layer includes: controlling the sheet resistance of the diffusion co-chip that is fed into the furnace together with the silicon wafer to be less than 10.

Please refer to FIG. 7 , in this embodiment, after forming the third implantation region 103 and the surrounding protective layer 310 , the method further includes removing the patterned oxide layer 320 .

In this embodiment, the patterned oxide layer 320 is removed by using hydrofluoric acid.

In this embodiment, after the patterned oxide layer 320 is removed with hydrofluoric acid, a passivation treatment process is performed on the surface of the mesa trench 300 to form a passivation layer (not shown). The passivation layer may be silicon oxide.

In this embodiment, the steps of forming the patterned oxide layer 320 include:

First, an oxide layer is covered on the surface of the mesa trench 300 , the surface of the first implantation region 101 and the surface of the second implantation region 102 , and the oxide layer material may be silicon dioxide.

Then, a patterned photoresist layer is formed on the surface of the oxide layer, and the patterned photoresist layer exposes the third injection area window and the surrounding protective layer window; the third injection area window is located in the second injection area. Part of the surface, the surrounding protective layer window is located at the bottom of the mesa trench.

Finally, using the patterned photoresist layer as a mask, the oxide layer is etched to transfer the pattern of the patterned photoresist into the oxide layer, thereby forming a patterned oxide layer 320 .

Step 6, forming electrode pins 200 . Referring to FIG. 8 , electrode pins 200 are formed on the surface of the first injection region 101 , the surface of the second injection region 102 and the surface of the third injection region 103 respectively, and each electrode pin is insulated and isolated.

Referring to FIG. 9 , in this embodiment, metal electrodes are welded on the surface of the first injection area 101 , the surface of the second injection area 102 and the electrode pins 200 of the third injection area 103 , respectively. The anode electrode 210 on the surface of the first implantation region 102 , the gate electrode 230 on a part of the surface of the second implantation region 102 , and the cathode electrode 220 on the surface of the third implantation region 103 .

Please refer to FIG. 10 , after the electrodes are formed, the thyristor device is fabricated. In this embodiment, an insulating protective layer 400 is provided around the thyristor chip through injection molding or encapsulation process. The insulating protective layer 400 wraps the thyristor device, and exposes the anode electrode 210, the gate electrode 230 and the cathode electrode 220 to protect the internal structure of the thyristor chip and improve the reliability and stability of the device.

In this embodiment, by adding a surrounding protective layer 310, ie a high-concentration N ⁺ diffusion layer, at the bottom of the mesa trench (ie, the mesa), the structure of the mesa can be regarded as a PNN+ structure. During the test process, with the voltage After the expansion of the space charge region reaches the N+ layer, due to the high impurity concentration of the N+ layer, the expansion of the space charge region becomes very small, and the size of the mesa junction can be shortened accordingly. The introduction of the concentration layer, the N ⁺ diffusion layer can shorten the broadening width of the electric field in the low-doped region, and the high concentration N ⁺ diffusion layer can neutralize and absorb surface charges, thereby reducing the mesa leakage current of the device and further improving the device. At the same time, because the withstand voltage is widened in the base region, the width of the mesa trench can be narrowed, thereby improving the utilization rate of the wafer area.

The above specific examples are used to illustrate the present invention, which are only used to help understand the present invention, and are not intended to limit the present invention. For those skilled in the art to which the present invention pertains, according to the idea of the present invention, several simple deductions, modifications or substitutions can also be made.

Claims (10)

1. A thyristor structure, comprising:

the base region is doped in an N type or a P type mode and is provided with a first surface and a second surface opposite to the first surface;

the first injection region is positioned on the first surface of the base region, corresponds to the doping type of the base region and is doped in a P type or N type;

the second injection region is positioned on the second surface of the base region, corresponds to the doping type of the base region and is doped in a P type or N type;

the third injection region is positioned on the partial surface of the second injection region, the doping type of the third injection region corresponds to the doping type of the second injection region, and the third injection region is N-type doping or P-type doping;

an anode electrode is arranged on the surface of the first injection region, a gate electrode is arranged on the surface of the rest part of the second injection region, a cathode electrode is arranged on the surface of the third injection region, and the gate electrode and the cathode electrode are insulated;

the mesa groove is arranged around the peripheries of the gate electrode and the cathode electrode, or is arranged around the periphery of the anode electrode, and the depth of the mesa groove extends into the base region;

and the surrounding protective layer is positioned at the bottom of the groove of the table top, the doping type of the surrounding protective layer is the same as that of the base region, the surrounding protective layer is N-type doping or P-type doping, and the doping concentration of the surrounding protective layer is greater than that of the base region.

2. The silicon controlled structure of claim 1, wherein the doping concentration and depth of the surrounding protection layer are the same as the concentration and depth of the third implanted region.

3. The silicon controlled structure of claim 1, further comprising a passivation layer on the mesa trench.

4. The silicon controlled structure of claim 1, wherein the third implant region has a plurality of shorting dots therein.

5. A method for manufacturing a silicon controlled rectifier structure is characterized by comprising the following steps:

selecting a proper silicon wafer, and defining a chip region and an isolation region, wherein the silicon wafer is of a first doping type, the first doping type is N-type doping or P-type doping, and the silicon wafer is provided with a first surface and a second surface opposite to the first surface;

performing a diffusion process of a second doping type on the first surface and the second surface of the silicon wafer, wherein the second doping type is P-type doping or N-type doping corresponding to the first doping type, so as to form a first injection region in the first surface of the silicon wafer and a second injection region in the second surface of the silicon wafer, and a base region is arranged between the first injection region and the second injection region;

etching the defined isolation region to the bottom of the base region to form a mesa groove, wherein two adjacent chip regions share one mesa groove;

forming a patterned oxide layer on part of the surface of the mesa groove, the surface of the first injection region and the surface of the second injection region, wherein the patterned oxide layer exposes a third injection region window and a surrounding protective layer window; the third injection region window is positioned on the partial surface of the second injection region, and the surrounding protective layer window is positioned at the bottom of the mesa groove;

performing a first doping type diffusion process on the silicon wafer by taking the patterned oxide layer as a mask, wherein the diffusion concentration is greater than the doping concentration of the base region, so as to form a third injection region on part of the surface of the second injection region and form a surrounding protective layer at the bottom of the mesa groove;

and respectively forming electrode pins on the surface of the first injection region, the surface of the second injection region and the surface of the third injection region, wherein the electrode pins are insulated and isolated.

6. The method of claim 5, wherein forming a patterned oxide layer on a surface of the mesa trench, a surface of the first implant region, and a surface of the second implant region comprises:

covering oxide layers on the surface of the mesa groove, the surface of the first injection region and the surface of the second injection region;

forming a graphical photoresist layer on the surface of the oxide layer, wherein the graphical photoresist layer exposes the third injection region window and the surrounding protection layer window; the third injection region window is positioned on the partial surface of the second injection region, and the surrounding protective layer window is positioned at the bottom of the mesa groove;

and etching the oxide layer by taking the patterned photoresist layer as a mask so as to transfer the pattern of the patterned photoresist into the oxide layer to form a patterned oxide layer.

7. The method of claim 6, wherein after performing a first doping type diffusion process on the silicon wafer using the patterned oxide layer as a mask, further comprising: and removing the patterned oxide layer by using hydrofluoric acid.

8. The method of claim 7, wherein after removing the patterned oxide layer using hydrofluoric acid, further comprising: and carrying out a passivation treatment process on the surface of the mesa groove to form a passivation layer.

9. The method of claim 5, further comprising: and performing enhanced diffusion process treatment on the surface of the first injection region, wherein the diffusion type of the enhanced diffusion process is the same as the doping type of the first injection region, and an enhancement region with the doping concentration higher than that of the first injection region is formed.

10. The method of claim 5, further comprising: controlling the doping concentration of the surrounding protective layer;

controlling the doping concentration of the surrounding protective layer comprises: the square resistance of the control diffusion chip is less than 10.

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