JPS62174830A - Data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a data processing technology and a technology that is particularly effective when applied to a stop method of a data processing device. This article relates to effective techniques that can be used as a stopping method.

[Prior Art] In a microcomputer system, there are cases where it is desired to stop the operation of a microprocessor in response to a request from a peripheral controller LSI or the like. For example, in a system connected to a DMA controller that performs DMA (direct memory access) transfer, a microprocessor needs to release the bus in response to a DMA transfer request from the DMA controller. One method is to stop the internal processing of the microprocessor when a DMA transfer request is made.

Conventionally, in a microprocessor such as the new HD6809 manufactured by Hitachi, Ltd., when there is a DMA transfer request or a refresh request, the internal processing of the microprocessor is stopped by stopping the internal clock.

On the other hand, in microprocessors such as the HD6809E, the three-state control terminal T is used during DMA transfer, etc.
When a bus release request is made using the SC, the microprocessor suspends its internal operations by extending the clocks (Q, E). (Hitachi, Ltd.,
Published September 1982, rsEMIcONDUcTORD
ATA800K 8/16-bit Microcomputer'', pages 522-523).

[Problems to be Solved by the Invention] As mentioned above, microprocessors operate internally dynamically so that internal processing can be stopped in response to an external request. However, when stopping internal processing in a microprocessor that operates dynamically, if the clock is stopped or stretched as described above, if the stopping time or stretching time is long, the charge in the signal line will leak and the internal The situation may reverse and the system may malfunction. Therefore, in order to prevent system malfunctions, it is necessary to limit the clock extension time or provide an internal refresh circuit.

SUMMARY OF THE INVENTION An object of the present invention is to enable a dynamically operating microprocessor to stop internal processing without causing system malfunction or insertion of an internal refresh cycle.

Furthermore, another object of the present invention is to enable processing to be stopped at any execution cycle without being aware of the state of internal processing.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, the control section of the microprocessor is controlled by a microprogram, and the operation of the control section can be stopped by an appropriate control signal.

[Function] According to the above means, internal processing can be stopped without stopping or stretching the clock, so that there is no level change due to leakage of charges in the internal signal line, which makes it possible to operate dynamically in a microprocessor. , it is possible to achieve the above objective of being able to stop internal processing for a relatively long period of time without causing system malfunction.

[Embodiment] FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a microprocessor.

In this embodiment, a control section 1 that generates control signals for execution units and the like inside the processor is configured using a microprogram control system. That is, the control unit 1 has a microR in which a microprogram is stored.
An OM (read only memory) 2 is provided. The ROM 2 is accessed by the micro address decoder 5 and sequentially outputs micro instructions constituting a micro program.

The microaddress decoder 5 is supplied with an address generated by a microaddress generation circuit 4 that generates a microaddress based on the operation code of the macroinstruction fetched into the instruction register 3. By decoding this, the microaddress decoder 5 outputs the first instruction of a series of microinstructions for executing the macroinstruction. By decoding this micro-instruction code by the control decoder 8, control signals for the execution unit 10, etc., which includes various registers, arithmetic and logic units, etc., are formed.

The second and subsequent microinstructions in a series of microinstructions corresponding to a macroinstruction are read by supplying the code of the next address field of the microinstruction read immediately before to the microaddress generation circuit 4. In this way, the execution unit 10 is controlled by the control signal formed in response to the reading of a series of microinstructions, and the processing corresponding to the macroinstructions is executed.

In this embodiment, although not particularly limited, the micro ROM
A latch circuit 6 that holds the micro-instruction code read from the micro-ROM 2, and a register 7 that can hold the micro-instruction code read from the micro-ROM 2 immediately before are provided. The control decoder 8 simultaneously decodes the microinstruction code read out from the microROM 2 and the microinstruction code read out immediately before and held in the register 7. A control signal is formed. When such a method of decoding two microinstruction codes is adopted, the length of each microinstruction code can be shortened. Furthermore, the execution speed of the second and subsequent microinstructions is not reduced.

However, even in the configuration of the embodiment, by stopping the shift of the microinstruction from the latch circuit 6 to the register 7, it is also possible to decode only one microinstruction to form a control signal.

Furthermore, in this embodiment, the internal stop signal N○P generated based on a bus release request signal or MPU stop request signal such as a DMA request signal or three-state control signal input from the outside is transmitted to the microaddress generating circuit. 4 is supplied. That is, by stopping the operation of the microaddress generation circuit 4 using the internal stop signal NOP, the internal processing of the microprocessor can be stopped without stopping or stretching the internal clock.

Furthermore, while the internal processing of the microprocessor is stopped by the internal stop signal NOP, the microinstruction code taken into the latch circuit 6 is held forever by the latch signal LAT generated in response to the signal NOP. It has become.

This allows the microprocessor of this embodiment to stop internal processing at any execution cycle. In other words, if you simply want to stop the microprocessor, you can do so by simply inputting the internal stop signal NOP to the microaddress generation circuit 4 and control decoder 8.

Such a stopping method is sufficient for a microprocessor that does not have the register 7 shown in the above embodiment.

However, in a microprocessor that is provided with the register 7 to simultaneously decode the previous microinstruction code and the next microinstruction code to form an internal control signal, as in the above embodiment, the state of internal processing is If you ignore this and stop processing at an arbitrary execution cycle, the continuity of the microprogram will be disrupted when processing is restarted, and the system may malfunction.

In other words, when register 7 is provided.

If the latch circuit 6 is omitted and the micro instruction code read from the micro ROM 2 is directly sent to the control decoder 8, a correct control signal may not be generated.

FIG. 2 shows the timing when the latch circuit 6 is omitted and the microprocessor is stopped by the NOP signal. In this case, when the address generation circuit 4 is stopped by the NOP signal, the output of the micro ROM disappears. Therefore, in order to prevent erroneous decoding by the control decoder 8, the control decoder 8 is also stopped.

In that case, as shown in Figure 2, the micro RO is activated when the internal stop signal NOP is input in synchronization with the clock CK.
The output of M2 disappears, and the output of control decoder 8 also disappears. Therefore, the output C (see FIG. 2) of the decoder 8 that appears when the microprocessor is operated continuously without stopping is eliminated. Therefore, the latch circuit 6
If you omit , you will not be able to stop the microprocessor at any execution cycle.

On the other hand, in the above embodiment, the internal stop signal N is used.

While P is in, the latch circuit 6 holds the microinstruction code output from the micro ROM 2 immediately before. Therefore, as shown in FIG. 3, the same code (3) is held in the latch circuit 6 and the register 7 while the internal stop signal NOP is input and the operation is stopped.

Then, when the primary internal stop signal NOP disappears and the process is restarted, the latch circuit 6 latches the microinstruction code (4) newly read out from the microROM 2. Therefore, when the process is restarted, the control decoder 8 outputs the original decoded output C, and then outputs the next decoded output, E, . . . in sequence. As a result, the control decoder 8 can form and output control signals without impairing the continuity of the microprogram.

Therefore, according to this embodiment, the internal processing by the multi-decoding method that utilizes the continuity of the microprogram can be stopped at any execution cycle without stopping or extending the clock.

As explained above, in the above embodiment, the control section of the microprocessor is controlled by a microprogram, and the operation of this control section can be stopped by an appropriate control signal, so that it is possible to stop or extend the clock. In addition, because there is no level change due to leakage of charges in internal signal lines, internal processing can be stopped without causing system malfunction in microprocessors that operate dynamically. It has the effect of becoming like this.

In addition, the control section of the microprocessor is of a microprogram control type, and the operation of this control section can be stopped by an appropriate control signal, and the micro ROM is
The micro-instruction read from the micro-ROM is held by a multi-decoding control section that decodes two instructions, the previous micro-instruction and the next micro-instruction, to form an internal control signal. A latch circuit is provided to hold the microinstructions, and the microinstructions are latched in this latch circuit while the address generation circuit is stopped by an internal stop signal. Therefore, even if the internal processing of the microprocessor is stopped, a continuous decoded output can be obtained, which has the effect of being able to stop the internal processing at any execution cycle without being aware of the state of the internal processing. There is.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in the above embodiment, the code in the next address field of the microinstruction read from the microROM 2 is returned to the microaddress generation circuit 4 to read the next microinstruction. The code can also be input to the address decoder 5 instead of the microaddress generation circuit 4.

In the above explanation, the invention made by the present inventor was mainly applied to a microprocessor that operates dynamically, which is the field of application that formed the background of the invention. It can be used in general processing equipment.

[Effects of the Invention] A brief summary of typical inventions disclosed in this application is as follows.

That is, in a dynamically operating microprocessor, internal processing can be stopped without causing system malfunction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a microprocessor, FIG. 2 is a time chart showing the timing when the latch circuit in the control section is omitted, and FIG. 3 is a control 3 is a time chart showing the timing of a microprocessor according to an embodiment of the present invention, which is provided with a latch circuit inside. 1...Control unit, 2...Micro ROM, 3...
...Instruction register, 4...Micro address generation circuit, 5...Micro address decoder, 6...
Latch circuit, 7...Register, 8...Control decoder, 10...Execution unit. Figure 1

Claims (1)

[Claims] 1. In a data processing device that has a microprogram control type control unit and is configured to operate dynamically, an internal stop signal is formed based on a stop request signal supplied from the outside, A data processing device characterized in that the internal stop signal causes the operation of the control section to be stopped. 2. The control section includes a storage section in which a microprogram is stored, an address generation circuit that forms an address for reading a microinstruction from the storage section, an address decoder that decodes the address, and a memory section for reading a microinstruction from the storage section. and a control decoder that decodes an issued microinstruction to form an internal control signal, and the processing operation of the control section is stopped by stopping the operation of at least the address generation circuit by the internal stop signal. 2. The data processing device according to claim 1, wherein the data processing device is configured to be stopped. 3. The control section includes a latch circuit that latches the microinstruction read from the storage section, and the control decoder latches the microinstruction read out from the storage section;
The data according to claim 2 is configured to simultaneously decode microinstructions read out one microinstruction before this microinstruction and held in the latch circuit to form an internal control signal. Processing equipment.