JPS62166547A - Formation of multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To reduce the connecting electric resistance of a hole by removing by dry etching 1/2 or less of the thickness of first metal interconnection film of a portion formed with the hole to increase the connecting area between first and second metal interconnections. CONSTITUTION:First aluminum interconnections 103, 103' are formed through a phosphorus glass film 102 on a silicon substrate 101 formed with an element active portion, a silicon nitride film 104 is then formed, and holes 105, 105' are subsequently formed to electrically conduct between the first and second aluminum interconnections. Then, with the plasma chemical vapor growing silicon nitride film 104 as an etching mask the portion formed with the hole of the first interconnection is removed by dry etching. When the portion formed with the hole of the first interconnection is removed, it is to 1/2 of the thickness of the first interconnections. Aluminum metals 106, 106' are buried in the holes, and second aluminum interconnections 107, 107' are then formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a multilayer wiring structure for a semiconductor device.

[Conventional technology]

In high-density, highly integrated semiconductor devices, it is essential to employ a 'wiring structure'. Multilayer wiring structure uses wiring materials such as
Metals such as tungsten produced by chemical vapor deposition and aluminum produced by sputtering are used, and as the glabellar insulating film, a silicon nitride film produced by plasma chemical vapor deposition, or a silicon oxide film produced by chemical vapor deposition is used. Alternatively, a polyimide resin film formed by spin-on coating or heat treatment is used. A conventional method for forming a multilayer wiring structure using these wiring materials and an interlayer insulating film is as shown in FIG. 2(a). via the insulating film 202, the first
203 and 203' are formed, and then the metal wiring 203 and 203' of
As shown in b), after forming the interlayer insulating film 204, the first and second layers are etched by photolithography and dry etching.
Opening 205.2 for establishing electrical continuity between metal wiring
05' is formed. Next, as shown in FIG. 4C, a two-layer metal wiring structure is formed by forming second metal wirings 206 and 206'.

[Problem that the invention seeks to solve]

However, in highly integrated semiconductor devices having minute openings, the above-described conventional multilayer wiring formation method increases the electrical resistance of the connection between the first metal and the second metal at the opening.
A problem arises in that the operating speed of the semiconductor device is delayed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a multilayer wiring structure that eliminates the above-mentioned problems, that is, reduces the electrical resistance at the opening.

[Means for solving problems]

The method for forming a multilayer wiring structure of the present invention includes the steps of forming a first metal wiring on the entire surface of a semiconductor substrate, forming an insulating film on the first metal wiring, and opening an opening in the insulating film. a step of etching and removing a film thickness of 1 or less of the first metal wiring in the opening; and a step of embedding metal into the opening and the portion of the first metal wiring that has been removed by etching. The method is characterized in that a second metal wiring is formed on the embedded metal.

[Example] Next, one embodiment of the present invention will be explained based on an example using the drawings.

FIGS. 1(a) to 1(h) are cross-sectional views of steps in forming a two-layer aluminum wiring structure according to an embodiment of the present invention.

As shown in FIG. 1 (al), a phosphor glass film 10
2, the first aluminum wiring 1 with a film thickness of 1 μm
03.103', and then, as shown in FIG.
A silicon nitride film 104 of m thickness is formed, and then, as shown in the same figure (C
), openings 105 and 105' for establishing electrical continuity between the first and second aluminum wirings are formed by photolithography and dry etching.

Next, using the plasma enhanced chemical vapor deposition silicon nitride film 104 as an etching mask, dry etching is performed to remove the opening portion of the first aluminum wiring by approximately 0.0 mm, as shown in FIG. Only a thickness of 5 μm is removed. Subsequently, as shown in the figure (el), aluminum metal 106 and 106' is filled in the opening including the portion removed by dry etching of the first aluminum wiring by ear sputtering. Subsequently, as shown in FIG. 6(f), an aluminum film with a thickness of about 1 μm is formed by sputtering, and second aluminum wirings 107 and 107' are formed by photolithography and dry etching. , a two-layer aluminum wiring structure is completed.

Thereafter, the steps shown in FIGS. 1(b) to 1(f) described above are repeated as necessary to form a multilayer wiring structure having three or more layers.

When removing the portion of the first aluminum wiring where the opening is provided, if it is removed too thickly, the resistance of the first aluminum wiring will increase, and if it is removed too little, the contact area with the aluminum metal buried in the opening will be small. Since the multi-connection electrical resistance increases, the thickness of the first aluminum wiring is reduced by 1
up to is preferred.

〔Effect of the invention〕

As explained above, the present invention makes it possible to increase the connection area between the first and second metal wiring by removing the opening by dry etching. It has the effect of reducing resistance.

For example, in this example, a first aluminum wiring having a thickness of approximately 1 μm in the opening was removed by dry etching to a thickness of approximately 0.5 μm, and then a connection portion with the second aluminum wiring was formed.
For an aperture with a diameter of approximately 1 μm, the connection electrical resistance is 3
The electrical resistance of the connection between the first aluminum wiring and the second aluminum wiring was 5 mΩ, which was formed by a conventional method without etching the first aluminum wiring in the opening.
It was very small compared to 0 mΩ.

This means that the area of the connection between the first aluminum wiring and the second aluminum wiring in the opening is 3355 μm2 in this example, and the first aluminum wiring in the opening is not etched. If the connection area is 0.
This is because the connection area is three times larger than that of 785 μm2.

As described above, the present invention is not only effective in reducing the size of openings accompanying the increase in density and integration of semiconductor devices, but also has a significant effect in increasing the speed of integrated circuit devices. Furthermore, the present invention is also effective when the second metal wiring is formed using normal sputtering when there is no need to fill the opening with metal by bias sputtering, that is, when the opening is large. be.

[Brief explanation of drawings]

FIGS. 1(a) to (h) are process cross-sectional views when forming a two-layer aluminum wiring structure according to an embodiment of the present invention, and FIGS. It is a process sectional view when forming a two-layer metal wiring structure. 101...Silicon substrate, 102...
Ringarasu! , 103, 103'...first aluminum wiring, 104...silicon nitride film,
105, 105'. 205.205'...Open aperture, 106.106'°゛. ...Aluminum metal, 107,107'...
・Second aluminum wiring, 201... Semiconductor substrate, 202... Insulating film, 203, 203'.
...First metal wiring, 204... Interlayer insulating film, 206, 206'... Second metal wiring. '; Seven-hearted agent Patent attorney Susumu Uchihara ・Hasuji 1 diagram YoshiZ diagram

Claims (1)

[Claims] A step of forming a first metal wiring on one main surface of a semiconductor substrate, a step of forming an insulating film on the first metal wiring, a step of forming an opening in the insulating film, and a step of forming an opening in the opening. a step of etching away 1/2 or less of the film thickness of the first metal wiring; a step of embedding metal in the opening and the portion of the first metal wiring removed by etching; and a step of burying the buried metal. 1. A method for forming a multilayer wiring structure, comprising the step of forming a second metal wiring thereon.