JPS6215665A - Logic simulater - Google Patents

Abstract

PURPOSE:To detect a holding timing error by producing a holding timing error signal when the data input of an FF has a change and a gate circuit is connected to a time wheel. CONSTITUTION:A gate circuit is provided to an automatic converting device 1. The data input and the clock input of the FF are defined as A and B respectively. The delay times of inputs A and B equal to '0' and the holding time respectively. A control part 4 connects each element to a time wheel 2 when the element has an output change. A holding timing error detector 3 receives the information showing whether the data input has a change or not from the part 4 in case any gate circuit is connected to the wheel 2. Then the detector 3 informs a holding timing error to the part 4 when the data input has a change. In such a way, the holding timing error can be inspected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a logic simulator based on a standard delay model.

(Prior art and its problems) With the development of VLSI and the expansion of logic devices, the role of logic simulation has become increasingly important, and high-speed processing on workstations has become necessary. Various logic simulators have been developed to meet this demand (for example, an example of the development has been published in Information Processing Vol. 25, No. 10, CAD-dedicated processing equipment). However, conventional logic simulators are Because we are pursuing this, we have dropped some important functions that were verified with conventional software. One of these is the hold timing verification function.

Therefore, an object of the present invention is to provide a logic simulator having a hold timing verification function.

(Means for Solving the Problems) Means provided by the present invention to solve the above-mentioned problems is a standard delay model logic simulator, in which the data input and clock input of the flip-flops are performed manually by A and C, respectively. Let input B be the time it takes for this human power A to propagate the change in value to the output, and let the time it takes for the input B to propagate the change in value to the output be the an automatic circuit conversion device that automatically generates a gate circuit that is made the same as the hold time; a time wheel that allows the gate circuit to be evaluated after the hold time after a change in the input B; The present invention is characterized by comprising a hold timing error detection device that generates a hold timing error signal when there is a change in A and the gate circuit is connected to the time wheel.

(Concept of the Invention) The present invention relates to a logic simulation of a standard delay model having a flip-flop timing error detection function.In the standard delay model, when a change occurs in the input of an element, as shown in FIG. , the element is
Connected to the time wheel. The time wheel is divided by time, and the locations where the elements are connected are separated by a delay time from the current time. Delay time refers to the time it takes for a change in input to be transmitted to the output.

In the standard delay model, new outputs are determined for elements connected at the current time. Then, find the element connected to this output and perform the processing described above. When all the processing for the element connected to the current time is completed, the clock is advanced and the processing is performed for the next time. Perform a simulation.

Flip-flop simulation is also simulated by the process described above, but flip-flops have timing commitments. A flip-flop has a data input and a clock input, and when there is a change in the clock input, the output is determined based on the signal at the data input. However, in order to guarantee the output, the data input must remain stable for a predetermined period of time after the change in the clock input that occurs at time 1 in the timing diagram of FIG. This time Tk is called a hold time. If the data input changes after the clock input changes within a time shorter than the hold time, the output is not guaranteed. Therefore, detecting whether this timing is correct increases the functionality of the logic simulator.

The basic function of detecting hold timing is as follows. One gate circuit is provided for each flip-flop. The data input of the flip-flop is one input of the gate circuit. This is input A. Further, the clock input of the flip-flop is used as the other input of the gate circuit. This is input B. Let the delay for input A be 0 and the delay for input B be the hold time Th.

In this way, a hold timing error occurs when a change occurs in the data input, ie, input A, while this gate circuit is connected to the time wheel. Therefore, in such a situation, an error in the hold timing can be detected by detecting it as an error.

(Embodiment) FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. The automatic conversion device 1 is a device that converts the circuit of a flip-flop as shown in FIG. That is, one gate circuit is prepared for each flip-flop. This gate circuit uses input A as the data input of the flip-flop, and input B as the clock input of the flip-flop.

The delay time of input A is O1 and the delay time of input B is hold time. The control unit 4 performs overall control of the logic simulator. Based on the circuit created by the automatic conversion device 1, the control unit 4 connects each element to the time wheel 2.
and use the time wheel to find the new output of each element, if there is a change in the output,
The element connected to this output is connected to the time wheel 2. At that time, the connection location is after the delay time for the input of this element. The hold timing error detection device 3 checks whether the gate circuit created for the flip-flop is connected to the time wheel 2. If there is such a gate circuit, the control unit 4 will notify you whether there is a change in the data input. If there is a change, the control unit 4 will notify you as a hold timing error. Let me know.

(Effects of the Invention) As described above, according to the logic simulator of the present invention, hold timing can be verified.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of an embodiment of the present invention, Fig. 2 is an explanatory diagram of a time wheel, Fig. 3 is a timing diagram of a flip-flop input signal, and Fig. 4 is a circuit conversion by an automatic conversion device. FIG. In the figure, 1 is an automatic conversion device, 2 is a time wheel, 3 is a hold timing error detection device, and 4 is a control section. Representative Patent Attorney Shinsuke Honjo Figure 1 Figure 2 Figure 3 =

Claims (1)

[Claims] In a standard delay model logic simulator, the data input and clock input of a flip-flop are input A and input B, respectively, the time it takes for input A to propagate a change in its value to the output is 0, and input B is the output. an automatic circuit conversion device that automatically generates a gate circuit that makes the time until a change in value is propagated equal to the hold time of the flip-flop; a time wheel that allows evaluation of a gate circuit; and a hold timing error detection device that generates a hold timing error signal when there is a change in the input A and the gate circuit is connected to the time wheel. A logic simulator characterized by: