JPS6214909B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to digital data processing technology, and more particularly to new and improved apparatus and methods for encoding and decoding binary digital data. The present invention is particularly applicable to digital data communication systems and magnetic storage restoration systems, although the latter will be described here.

In the development of binary data magnetic storage and retrieval systems, the main interest is to increase the data capacity of the system by recording more data in a given time interval or length on a storage medium such as a disk or tape. It was hot. This objective is achieved by encoding the binary data in such a way that the signal changes or transitions representing the binary data zeros and ones, respectively, are placed or stored as closely together as possible. However, various constraints inherent in such systems
With regard to accurate recording and reproduction of data, as far as data recording density is concerned, this imposes limits on what can actually be put to practical use. Such a constraint is a phenomenon generally referred to as bit shift that occurs when binary data is reproduced from an encoded signal stored in a storage medium. This is characterized by a shift of the reproduced signal transitions from their nominal position and is caused by adjacent transitions recorded on the storage medium being very close together or tightly packed together. More specifically, bit shift occurs as a result of interference or interaction between transitions of adjacent reproduction signals and transitions of each reproduction signal when reading recorded signals from a storage medium. The amount of shift that occurs for each reproduced signal transition is determined by the degree of asymmetrical arrangement of transitions adjacent to both sides of each reproduced signal transition and the recording density thereof. The amount of shift increases proportionally as the recording density and asymmetry of each signal increases.

Bit shifting is of considerable importance as it is directly related to the ability to accurately reproduce binary data, as will become clear from the following description. If the data is to be recorded, it is encoded as previously described and in further detail below, such that each signal transition is recorded on a clock-based basis, such that each signal transition is recorded in a defined interval or segment of the storage medium. is applied to the recording medium. Recording on a predetermined time basis is essential in order to be able to detect each 1 or 0 data bit when reading from the storage medium to reproduce the binary data stream. A gated oscillator, preferably a phase-locked oscillator, is utilized to create a time-oriented window for recovering binary data from the regenerated signal transitions. For example, phase-locked oscillators function conventionally in a manner well known to those skilled in the art, operating at a nominal frequency that is a selected harmonic of a frequency that corresponds to the fundamental period of the encoded data signal, thereby allowing the encoded data to A gating window signal is generated associated with each recovered signal transition to recover binary data from the signal. It should be understood at this point that the restoration window has a characteristic commonly referred to as timing tolerance associated with it. It will be appreciated that if signal transitions are recorded more closely, the reconstruction window must be determined so as not to detect reproduced signal transitions in non-relevant windows. As the restoration window is narrowed, the amount of bit shift allowed decreases proportionally. A phase comparator included in the phase-locked oscillator compares the phase of the reproduced signal transition read from the storage medium with the signal provided by the phase-locked oscillator;
A signal is generated that controls the oscillator to cause the signal to track the reproduced signal transitions. The filter circuit of the phase-locked oscillator operates to enable the oscillator to track the average time position of the reproduced signal transitions while remaining insensitive to their instantaneous variations. In this way, the restoration window is generally kept substantially in line with the playback signal transitions. However, in the case of a sudden bit shift exceeding a predetermined amount, the reproduced signal transition will be located outside the restoration window, and failure to detect it will result in erroneous data restoration.

It will be seen from the foregoing description that the bit shift needs to be reduced to improve data recovery, and that the reduction in bit shift is determined by avoiding abnormal packing of adjacent transitions of the encoded data signal. Various encoding techniques have been devised in the development of technology to meet these criteria and those described below. Some desirable features of suitable encoding techniques are briefly described herein and will be explained in more detail below in connection with the detailed description of the inventive and prior art codes illustrated in the accompanying figures. One desirable feature, of course, is that the encoding avoid inappropriate bit shifting. This is achieved by providing sufficient spacing between transitions of successive signals recorded on the storage medium, but without reducing the recording density.
Another desired feature of all encoding techniques is
The goal is not to provide such large intervals between transitions of the recorded signal that it becomes impossible to achieve automatic clocking during data recovery. Self-clocking is characterized by the fact that the encoded signal recorded on the storage medium and the associated read or reproduced signal have such qualities that they provide the necessary control over the phase-locked oscillator for data recovery as described above. This is one feature that makes it possible. If the self-clocking function is lost, it is necessary to provide a separate clock channel in the recording medium, which inter alia makes the read/write head of the clock channel in line with the heads associated with the data channel. This is not desirable because it requires alignment. On the one hand, the requirement to provide sufficient minimum spacing between successive signal transitions to eliminate excessive bit shifting, and on the other hand, the requirement to require a limited maximum spacing between successive signal transitions to achieve self-clocking. has essentially the same meaning as the criterion of minimizing the number of signal transitions recorded per data bit, or conversely maximizing the number of data bits represented by each recorded signal transition. .

The various encoding techniques commonly used in the state of the art are generally deficient in some aspect of the above characteristics. For example, so-called NRZ or NRZI codes are characterized by long intervals between recording signal transitions when followed by a number of 1 or 0 bits, thereby preventing self-clocking.
Frequency modulation (FM) and phase modulation (PM) codes, on the other hand, provide self-clocking but are characterized by close spacing between transitions in the recorded signal, thus avoiding excessive bit shifts and ensuring accurate data recovery. limited by the data storage density and timing tolerance required for The narrow spacing between transitions in FM and PM encoding techniques is due to the deliberate insertion of clock transitions into the data transition stream to achieve self-clocking, so these codes This is worse with respect to the desired criterion of minimizing the number of recording transitions per bit.

A more recently developed code known as Modified Frequency Modulation (MFM) overcomes the limitations of FM, PM and NRZ types to some extent, in fact it is capable of self-clocking and makes the bit-shifting problem worse or reduces timing tolerance. It has become widely used over the past few years because it provides almost twice the recording density of FM and PM codes. Because this MFM encoding technique does not use additional clock transitions, but instead uses data transitions for clocking purposes, it provides an improvement with respect to the criterion of minimizing the number of recorded transitions per data bit. Nevertheless, the binary data recording density that can be achieved with MFM codes is limited by the minimum interval allowed between successive signal transitions recorded on a storage medium. This limitation of the MFM code to the present invention will be more fully understood from the following detailed description of a preferred embodiment of the present invention.

The main object of the present invention is therefore to develop a novel encoding system capable of providing self-clocking functionality and at the same time increasing data storage density by about 50% or more over the current state of the art without incurring a reduction in timing tolerance. The purpose is to provide restoration technology associated with this.

Still another object of the present invention is to encode binary signals in which the number of data bits represented by each transition of the encoded data signal is significantly greater than that obtained with state-of-the-art encoding techniques. The aim is to provide new technology to

The above and other desired objectives are to divide a binary data stream, each consisting of a series of 1 and 0 bits occurring at an interval T, into respective data groups or words each containing three data bits. This is achieved by a preferred method for storing on a magnetic storage medium by. Each data word is represented by sequentially representing each data word, referred to herein as the current data word, by one code signal or a combination of two code signals that uniquely represent the data word. recorded continuously. One code signal or a combination of two code signals is transmitted P1, P2, P3, P4, P in a designated segment of the magnetic storage medium, called a data cell, with a length corresponding to an interval of 3T.
5 and P6, respectively, at a selected signal transition position or a plurality of signal transition positions among only the first five of six equally spaced predetermined signal transition positions occurring sequentially in the order P5 and P6. corresponds to a signal transition or a combination of signal transitions recorded as a flux transition or a combination of flux transitions. This recording is such that the transition combinations are recorded at positions with a defined minimum spacing of spacing equal to 1.5T.

Simultaneously with the encoding of the current data word being recorded, look ahead to the next data word to be recorded, so that when the next data word is encoded for recording, the boundary of the current data cell is Determine whether the next data word contains a bit pattern that creates a code signal corresponding to the transition at position P1 in the nearest next data cell. Under such circumstances, if the current binary data word generates a code signal representing a signal transition located at position P5, one signal transition is not recorded at position P5 of the current data cell, but instead is It will be recorded at position P6, which corresponds to the boundary between the current data cell and the next data cell.

Also, at the same time as the current data word is encoded, a previously recorded data word is looked back so that when encoded for recording, the signal transition at position P5 is replaced by the signal transition at P6. It is determined whether the previously recorded data word contained the bit pattern that generated the code signal corresponding to the bit pattern.

Under these circumstances, the current data word is P1
, such signal transitions are not recorded. Therefore, if adjacent data words are associated with code signals representing a signal transition at position P5 for one data word and a signal transition at position P1 for the immediately following data word, then
Neither signal transition is recorded, but is effectively combined into or replaced by a single signal transition at the boundary between the data cells associated with each word.

The apparatus implementing the preferred encoding method consists of the following: That is, binary digital data consisting of a series of data bits occurring at predetermined time intervals T, each corresponding to a signal transition at a selected one of a plurality of signal transition positions on the magnetic storage medium; An apparatus for encoding binary digital data by converting it into a series of code signals in which each selected signal transition position is separated from each other by at least a predefined minimum interval T. a first shift register for receiving and storing bits as a preceding data word, a current data word and a following data word of three bits each in discrete storage locations; a first encoder and associated logic circuitry connected to an output of the encoder for providing a code signal or a combination of two code signals representative of the current data word; Each code signal provided by Corresponding to a signal transition at a signal transition position, said data cell has a time interval length of 3T, corresponding to one data word, and two signal transitions corresponding to a combination of two code signals are at least 1.5 are placed at signal transition locations having a predefined interval equal to T; a second shift register for storing two; connected to the output for the subsequent data word of the current data word in the first shift register; and a signal transition position that is the first of the six signal transition positions within the data cell; a second encoder and associated logic circuitry having only an output corresponding to a data word having a corresponding code signal; said subsequent data word being a data cell of a current data word and a data cell of a subsequent data word; signal transition position in a data cell of the current data word adjacent to the boundary between the data cell of the current data word and the data cell of the subsequent data word The code signal corresponding to the code signal is prohibited from being stored in the second shift register, and the code signal corresponding to the code signal is stored in the second shift register at the signal transition position at the boundary between the data cell of the current data word and the data cell of the subsequent data word in place of the prohibited code signal. Assign one code signal to the corresponding storage location of the second shift register; also connected to the output for the data word preceding the current data word in the first shift register, and six signal transitions in the data cell; a third encoder and associated logic circuitry having an output only corresponding to a data word having a code signal corresponding to a fifth of the signal transition positions; said previous data word being the data of the current data word; When the current data cell adjacent to the boundary between the data cell of the current data word and the data cell of the previous data word has a code signal corresponding to a signal transition position adjacent to the boundary between the cell and the data cell of the previous data word. Prohibiting the storage of the code signal corresponding to the signal transition position in the data cell of the data word in the second shift register; and means for generating a signal transition corresponding to the code signal in response to the code signal.

Signal transition position P1 adjacent to the current data cell
a code signal corresponding to a signal transition at position P5 in the current data cell adjacent to the next data cell if the subsequent data word is associated with a code signal corresponding to a signal transition in the data cell of the subsequent data word; The second encoder and logic circuit act to inhibit the previous data word from occurring at a signal transition position P5 where the previous data word is adjacent to the current data cell. When associated with a code signal corresponding to a signal transition inhibited in a data cell of a word, the code signal corresponding to a signal transition at a signal transition position P1 in a current data cell adjacent to the preceding data cell is inhibited. It will be appreciated that the second and third encoders and associated logic circuitry can be modified to generate a signal at the signal transition location P6' which is simultaneously at the boundary between the current data cell and the previous data cell. Dew. Two signal transitions spaced apart by less than a specified minimum amount may be replaced or merged with one such signal transition at its first signal transition location, and It will also be appreciated that signal transitions do not necessarily need to be placed on both sides of a single data cell boundary.

The invention further relates to a method and apparatus for restoring data encoded as described above. Simply put, this restoration device records in the current data cell,
a read shift register for storing signals representative of the signals to be read together with the signals recorded at the boundaries of the current data cell and the previous data cell; It includes combinations with logic circuit means for forming the combinations of bits of the current data word represented by certain signals.

The binary data pattern used to explain the operation and characteristics of the present invention in relation to codes as compared to the prior art is shown in FIG. , are shown occurring at intervals T with uniform spacing between the bits provided by the clock generator. The interval T is expressed in units of time or corresponding units of length of the storage medium. Various prior art codes shown in FIG. 1, namely NRZI,
FM, Gabor and MFM are each intended to encode binary data. It is recognized that all these codes are given on a common scale corresponding to the indicated binary data rate. In the case of NRZI codes, a signal transition occurs at the center of the interval T in the encoded waveform to represent a ``1'' bit, while no signal change occurs for a ``0'' bit. te2
decimal data is encoded. FIG. 2 displays various characteristics of the prior art code shown in FIG.
NRZI codes have the advantage of having a relatively wide reconstruction window (±0.5T) which derives from the fact that the closest signal transitions are spaced apart by an amount equal to T. In other words, a transition gate pulse or so-called recovery window located at the center of each data bit interval and having a width of approximately ±0.5T only detects signal transitions that occurred in the relevant interval. But this NRZI code is also not capable of self-clocking and also has SMAX
It has the serious drawback of having an extremely wide bandwidth as indicated by the ratio of SMIN to SMIN. Here
SMAX and SMIN represent the maximum and minimum distances between encoded signal transitions, respectively. This occurs because no signal transition occurs when "0" bits continue for a long time. In order to obtain a self-clocking function, the interval SMAX must not be too large since the phase-locked oscillator of the restoration system is controlled by the regenerated signal transitions as described above. If the interval SMAX exceeds a predetermined interval, the oscillator free-runs without clocking (synchronization), so that the recovery window generated by the oscillator is the recovered signal needed to recover the binary data. Transitions may not be tracked.

In FM codes, signal transitions occur in the encoded waveform at each boundary between intervals T of adjacent data bits and at the center of each bit interval where a "1" bit appears. Transitions that appear in the middle of the T-interval are data transitions, and transitions that appear at the boundaries are clock transitions that are specifically inserted to ensure self-clocking functionality. Since the maximum spacing between signal transitions is equal to T, self-clocking is easily achieved. Furthermore, the system bandwidth is S
The ratio of MAX to S MIN is significantly reduced compared to the NRZI code. For a clock speed of 2/T, one complete cycle of the restore window signal occurs in each interval T, with half a cycle required to be placed in the middle of the T interval to distinguish data transitions from clock transitions. shows. As a result, the restoration window for the FM code is reduced to 1/2 of the restoration window for the NRZI code. As shown in FIG. 2, reducing S MIN has the opposite effect of reducing the number of data bits encoded per S MIN , ie, per transition, to half of that obtained with the NRZI code.

The Gaber code described in U.S. Pat. It is characterized by encoded signal transitions occurring at the positions of . S
As the number of data bits encoded per MIN increases, the recovery window increases by increasing the minimum spacing between signal transitions, which reduces the storage density of binary data for FM codes. Gabar codes offer some improvement over FM codes in terms of increase, but not as much as is possible for NRZI codes.

MFM codes are characterized by the encoded signal being either at the center of the interval of data bits or at its boundaries; therefore, due to the self-clocking operation, the entire encoded signal is detected, e.g. In order to be able to distinguish between 1 bits and 0 bits, which are represented in the form of a signal encoded by transitions occurring at distinctive positions, denoted by ``1'' and ``0'' at the boundary of the T interval. ,
The restoration window is for each data bit interval T.
The MFM code is
It has the same clock speed as the FM code. MFM codes offer the advantage that more data bits are coded per S MIN compared to gaybar codes, and are in fact equivalent to NRZI codes, as shown in Figure 2, and they also have the advantage of having a self-clocking feature. Maintain restore window and S MAX. Furthermore, as the minimum spacing between encoded signals increases,
The binary data recording density obtained with MFM code is FM
or better than what can be obtained with gay bar codes, and in fact has almost twice the density of FM codes. In other words, if the minimum acceptable spacing between signal transitions is T/2 for the allowed bit shift with respect to the width of the reconstruction window, binary data is It will be delivered at about twice the speed. That is, the interval T of binary data can be reduced to T/2 in the case of MFM encoding. accordingly
MFM codes are recognized to have many desirable qualities for binary data encoding applications.

Although the methods and techniques for carrying out the invention are briefly described below, the main features of the invention are shown in Figures 1 to 3.
As shown in the figure. According to the present invention, the MFM code is further improved, particularly with respect to the minimum spacing of signal transitions of the encoded waveform and the number of data bits encoded per minimum spacing between transitions as shown in the comparison of FIGS. 3 and 2. A new code called 3PM (three-position modulation or three-phase modulation) is provided. More specifically, considering that the minimum spacing between signal transitions has increased, the recording density of binary data has increased to MFM
This is expected to be enhanced by 50% compared to the code. Thus, if the minimum acceptable spacing between adjacent transitions is T/2, then the 3PM code is only 3 times smaller than the FM coding and the MFM coding.
Enables binary data to be compressed by 50%. It will also be noticed from FIG. 3 that the recovery window of the 3PM code remains equal to that of the MFM code. S MAX and S MAX vs. S
Although the ratio of MIN increases together, the obtained parameters are nevertheless sufficient for self-clocking restoration with the circuits currently available in the state of the art. In the case of the 3PM code, transitions occur at both the midpoint and the boundary of the T interval, so the clock speed is 2/T, which corresponds to the clock speed of the FM and MFM codes. The above feature of the 3PM code is that binary data is divided into binary data words, and one signal transition occurs in a data cell with a length equal to the sum of the number of intervals T corresponding to the number of bits of each data word. or by encoding each data word to be represented by a combination of signal transitions spaced apart by at least a predetermined minimum amount. The occurrence of this code further defines when a signal transition in one data cell is spaced from a signal transition in an adjacent data cell by less than a specified minimum spacing, and if such occurs. It is based on allowing very closely spaced signal transitions to be replaced by a smaller number of signal transitions.

The preferred encoding circuit shown in FIG. 6, which will be explained a little later, has the function of dividing binary data into sets of three data words, each data word containing three data bits;
Each data word may be any one of eight possible data words, ie, each data word corresponds to one of eight possible combinations of data bits within a word. Each data word may also be defined by one signal transition location within a data cell of the storage medium or by a plurality of signal transition locations within that data cell separated from each other by at least a specified minimum distance S MIN = 3T/2 as shown in FIG. corresponds to either a single code signal or a combination of multiple code signals, each associated with a combination of signal transition positions.
FIG. 4 shows the arrangement of signal transition positions P1 to P6,
These are for the case of 3 data bits per data word.
Data cells of length equal to 3T are equidistantly spaced from each other by an amount T. Position P6 coincides with each boundary of the data cell.

Columns 3 and 5 of FIG. 7, with their respective names and binary data words and transition positions within the data cell, are 6
Displays the correlation of eight possible data words with two data cell transition positions. Other correlations of this data word and transition position may be used if desired, as long as they satisfy the coding criteria of the present invention in the manner described below.For the indicated correlation, a single transition position is
Used for binary data words 000, 001, 010, 100 and 101, two signal transition positions are used for binary data words 011, 110
You will notice that it is used in 111.
Also, in these examples two signal transitions are used, but from the above explanation, the specified minimum interval is
It will be noted that each signal transition is spaced apart by at least three positions found to be equal to 3T/2. When signal transitions occur at signal transition position P5 of one data cell and signal transition position P1 of the immediately following data cell, the interval between signal transitions is interval T.
Therefore, it is clear that the specified minimum spacing will not be reached. Therefore, if such signal transitions are required, they do not actually occur but instead occur at the signal transition position P6 between the two inhibit signal transitions.
is replaced by a single signal transition. More specifically, the current binary data word being encoded corresponds to a single signal transition to be generated at position P5 of the current data cell, and a signal transition to be generated at position P1 in the next data cell. If this is followed by a binary data word associated with a single signal transition that should Replaced by signal transition of P6. The current binary data word to be further encoded is located at the signal transition position P1 within the current data cell.
corresponding to the signal transition to be generated at signal transition position P5 in the preceding data cell (which under the conditions assumed here would be replaced by the signal transition at signal transition position P6). If the signal transition was preceded by a binary data word associated with the current data cell, the signal transition would be inhibited at the signal transition location P1 within the current data cell. It is thus guaranteed that the encoded signals do not occur less than three positions apart. In other words, the immediately following data cell has a signal transition to be generated at signal transition position P1, and there is a signal transition to be generated at signal transition position P5 within the current data cell.
The present invention provides that if there are signal transitions to be generated at P6, they are merged into a single signal transition that is generated at the signal transition position P6 at the boundary between the current data cell and the immediately following data cell. These are the rules for encoding technology. As will be explained in full detail below with respect to FIGS. 6, 7, and 8, when each binary data word is encoded sequentially, by simultaneously noting the immediately preceding and following data words. This is accomplished. Attention is first directed to FIG. 5, which illustrates a binary data pattern and associated encoded signal generated in accordance with the encoding technique of the present invention.

As shown in FIG. 5, the first binary data word 001 causes a signal transition at a signal transition position P4 of the first data Z1. The binary data word 111 of the second binary data group produces a signal transition at signal transition positions P1 and P4 in data cell Z2, which signal transition occurs at signal transition position P5 of the preceding data cell Z1. Since it did not occur, it is generated at the signal transition position P1 of data cell Z2. Third binary data word 010
generates a signal transition at signal transition position P2 of data cell Z3. The fourth binary data word 110 corresponds to the signal transitions to be generated at positions P1 and P5 of data cell Z4, but only the signal transition at signal transition position P1 is actually generated. Data cell Z4
The signal transition at signal transition location P5 of cell Z5 is inhibited because the next binary data word 101 is associated with the signal transition at signal transition location P1 of cell Z5. Therefore, according to the coding rules of the present invention, the signal transition occurs in data cell Z4.
is not generated at signal transition position P5, but is instead generated at signal transition position P6, which coincides with the intermediate boundary between data cells Z4 and Z5. Furthermore, data cell Z
Since the signal transition at the signal transition position P5 of 4 is replaced by the signal transition at the signal transition position P6, no signal transition occurs at the signal transition position P1 of the data cell Z5 corresponding to the binary data word 101.

According to FIG. 6 and FIG. 11a, the encoded 2
The signals representing binary data each include 3 bits,
Data input terminal 1 of a write data shift register 15 having a capacity sufficient to store three binary data words, hereinafter referred to as current, previous and subsequent data words according to their instantaneous position within the register.
4. For example, a binary data signal consists of a series of pulses obtained by representing each ``1'' bit by one pulse and each ``0'' bit by the absence of a pulse in discrete time increments. be done. A series of bit clock pulses occurring at this data rate are applied to the bit terminal 16 in order to advance the binary data by one register stage in response to each such pulse. It should be noted at this point that the condition of no data in the register corresponds to no pulse in the respective register stage, ie, a series of 0 bits. binary data word
It will be noticed from FIG. 7 that 000 corresponds to a signal transition at signal transition position P5, which would actually be moved to signal transition position P6 as described above. It is thus assumed that encoding begins when the first binary data word to be encoded is aligned with the binary-octal encoder 17. This state is the sixth state after applying binary data to the input terminal.
This occurs when the th bit clock pulse, ie, bit clock pulse 18a, occurs, and at that time, no data is loaded into the right three stages of register 15. Consider in more detail the sequence of events that begins after the fifth bit clock pulse 18b, that is, after the first five data bits have been loaded into register 15. First, the recording signal applied to the recording terminal 19 of the write signal shift register 20 changes from high level to low level, and at that time, the register 20 respectively changes the position P1 of the data cell.
Its respective stages S1-S6 corresponding to P6 are ready and ready to be loaded with signals. However, the actual rotation of signals into each stage of register 20 does not occur until the moment the leading edge of word clock pulse 21a applied to word clock terminal 22 changes from a high level to a low level.
In any case, the signal loaded into the register 20 stage is only transient at this moment, as the sixth data bit is loaded into register 15 and the first data group to be encoded is binary-octal. encoder 17
It does not become stable for writing until the occurrence of the sixth bit clock pulse 18a, which is aligned to . Therefore, for example, if data word 001 in FIG. 5 is the current binary data word to be encoded, a signal is supplied from the B1 terminal of the encoder 17 as shown in FIG. The signal is transmitted to stage S4 of the register 20 via 23. The signal at the output of OR gate 23 is the sign signal for the current data word 001. At the same time, binary-octal encoder 2
Three 0s in the preceding stage of register 15 aligned with 4
The bit is OR gate 26, inverter 27 and AND
operating through a logic circuit 25 including a gate 28;
If the signal is applied to terminals B5, B6 or B7 of the encoder 17, which is not actually the case for the current binary data word 001, the register 20
The signal is inhibited from being stored in stage S1. At the same time, subsequent data words in the next three stages of register 15, which in this example is 111 and aligned with binary-octal encoder 29, pass through OR gate 31, inverter 32, AND gates 33 and 34. Contains logic circuit 3
0 and the terminals B0, B3 of the encoder 17
Or, if a signal is supplied to B6, which is also not the case for the current binary data word 001, the storage of the signal in stage S5 is inhibited and stage S6
memorize the signal. Therefore, in the end, the data word 001 currently being encoded will generate a signal in stage S4 of register 20, but will not generate a signal in the other stages of register 20. At the trailing edge of word clock pulse 21a, further loading of signals into stages S1-S6 of register 20 is inhibited.

During the time between the trailing edge of word clock pulse 21a and the trailing edge of the next word clock pulse 21b, all six position clock pulses 35a-35f occur at twice the rate of all bit clock pulses and are is slightly ahead of the bit clock pulse. As each position clock pulse is applied to position clock terminal 36 of register 20, the contents of the respective register stage is shifted one stage. Thus, upon occurrence of position clock pulse 35a, the signal of register stage S1 is applied as an input trigger pulse to bistable flip-flop 37, and register stage S1 is applied as an input trigger pulse to bistable flip-flop 37.
The signal of stage S2 is shifted to stage S1, etc., and the signal of stage S6 is shifted to stage S5 in the same manner. For the assumed binary data word 001, only stage S4 contains a high level signal, so flip-flop 37
does not switch state until the signal originally stored in stage S4 is applied to the input of the flip-flop. This switching of the state of flip-flop 37 is well understood by those skilled in the art, and
It can be used to create magnetic flux transitions in a magnetic storage medium as detailed with respect to the figures. On the generation of the leading edge of position clock pulse 35f, the signal first stored in stage S6 is applied to the input of flip-flop 37, and shortly thereafter bit clock pulse 18e occurs, and the word clock signal changes to pulse 2.
At this point it is again at a low level as shown by 1b, so the bit clock pulse 1
8e sends the new code signal to stages S1 to S1 of the register 20.
S6 is applied. Position clock pulse 35a~
While 35f was occurring, bit clock pulses 18c-18e were also occurring, thereby shifting each signal in register 15 to three positions since the data bit that was first in the previous stage was shifted out of register 15. You will notice that the data bits that were originally in the current stage are now moved to the previous stage. Similarly, the first data bit in the next stage is moved to the current stage ready for encoding, and the next binary data group 010 (5th
) is loaded into the next stage. The slight time delay of bit clock pulse 18e with respect to position clock pulse 35f ensures that each signal of one data word is in register 20, and the signal corresponding to the next data word is in register 20.
ensure that the data is transferred from register 20 to flip-flop 37 before being loaded into flip-flop 37.

As previously mentioned, the bit clock rate is equal to the data rate and the position clock rate is twice the bit clock rate. It is therefore the position clock speed that determines the recording speed on the recording medium and the associated minimum spacing between signal transitions, so once the desired minimum spacing between signal transitions is established, the position clock speed determines the recording speed of the recording medium and the associated minimum spacing between signal transitions. It turns out that the bit clock speed must then be set to 1/2 of the position clock speed.

The recording operation of successive binary data words continues in the manner described above. Thus, for the binary data word 111 in the current encoding stage of register 15, a signal is generated at terminal B7 of encoder 17 as shown in FIG. is sent to stages S1 and S4. The signal at the output of OR gates 23 and 38 is the code signal for data word 111. Similarly, for the binary data word 010 of the current encoding stage of register 15, one signal is applied to terminal B2 of encoder 17, and encoder 17
OR gate 3 connected to stage S2 of register 20
A code signal is generated at the output of 9. Then the data word
110 provides a signal to terminal B6 of encoder 17 which generates a sign signal at the output of OR gates 38 and 40 which are coupled to stages S1 and S5 of register 20, respectively. However, in this example, the signal is not loaded into stage S5, but instead is supplied from encoder 29 and operates through logic circuit 30 so that the signal is not loaded into stage S5.
6. More specifically, referring to FIG. 5, it can be seen that data word 101 follows the data word 110 currently being encoded. encoders 24 and 29
is the same as encoder 17, so encoder 29 provides a signal at terminal C5 in response to the binary data word 101 applied to its input. The signal at terminal C5 is
A low level signal is generated at the input to AND gate 34 that is transmitted through OR gate 31 and inverter 32 and suppresses the passage of the signal provided from encoder 17 to AND gate 34 . At the same time, terminal C5
The signal sent from is also sent to AND gate 33, where it combines with the high level signal derived from terminal B6 through OR gate 40, thereby loading the signal into stage S6 of register 20.
This operation corresponds to the combination of serial number 12 in FIG. Finally, when binary data word 101 reaches the current encoding stage of register 15, binary data word 110 is shifted to the previous stage and another word (not shown in FIG. 5) is placed in register 15. Subsequent stages are loaded.
In this example, encoder 17 includes stage S of register 20.
This operation is responsive to the binary data word 110 applied to the encoder 24, which provides a signal at terminal B5 which generates a code signal at the output of an OR gate 38 coupled to an AND gate 28 which loads the signal to the encoder 24. is inhibited by a signal applied to terminal A6 of encoder 24. The signal at terminal A6 travels through OR gate 26 and inverter 27, producing a low level signal at the input of AND gate 28 to stop the signal passing through the gate. This operation is shown at serial number 9 in Figure 8.
Corresponds to the combination of The operation of encoders 17, 24, 29 and associated logic elements of FIG. 6 for various other combinations of binary words in the current, previous, and subsequent stages of register 15 is illustrated in FIG.

Before explaining the restoration device, it is important to note that a signal transition that should have been generated at signal transition position P1 of a certain data cell is actually generated due to a signal transition that was generated at signal transition position P6 of the previous data cell. Cases with serial numbers 9, 11, 13 and 15
It should be noticed from FIG. 8 that the combination of This is an important feature and must be properly taken into account when recovering binary data from a coded signal, as will become clear from the following description of the recovery device.

Referring to FIGS. 9 and 11, a stream of regenerated encoded signal pulses from which binary data is to be recovered is applied to input terminal 41 of read signal shift register 42. Referring to FIGS. This flow of regenerated encoded signal pulses records a signal originally encoded to represent binary data in the form of a series of magnetic flux transitions, each corresponding to a signal transition in the encoded signal. It is derived from an analog signal read from a magnetic storage medium and consists of a series of pulses, each pulse corresponding to a signal transition of the encoded signal. Position clock terminal 4 of register 42
A position clock pulse applied to 3 increments the encoded signal pulses through the register at the same rate that encoded signal transitions are generated during recording. Stages S1 to S6 of the register 42 correspond to signal transition positions P1 to P6 of each data cell of the recording medium, respectively, and stage S6' corresponds to signal transition position P6 of the data cell immediately before the current data cell whose data is being restored. handle. Since the signals are read from the recording medium in the same order as they were recorded or written, in order to restore the data, the pulses corresponding to the signal transitions recorded at the trailing boundary of the data cell before the current data cell must be The signal transition recorded in stage S6' of register 42 and recorded at the trailing boundary of the current data cell is recorded in stage S6 of register 42 in preparation for data recovery.

Referring again to FIG. 5, consider the restoration of the first recorded binary word, 001. This word produced a signal transition at signal transition position P4 during the encoding and recording process, but now during decompression, a step occurs upon completion of reading the first data cell of the storage medium occurring at position clock pulse 44a. A high level signal is generated at S4 and a low level signal is generated at all other stages of register 42. Position clock pulse 44a
Shortly before the occurrence of the read gate signal applied to the read gate terminal 45 of the read data shift register 46, the read gate signal is applied to the read gate terminal 45 of the read data shift register 46. It changed from high level to low level to make it. Word clock terminal 4 of register 46
The occurrence of the leading edge of word clock pulse 47a applied to terminal D0, D1 and D2 actually loads the signal to terminals D0, D1 and D2. It will be seen that these signals are transient and do not stabilize until the leading edge of position clock pulse 44a occurs.
As with recording, the bit clock pulse rate is one-half the position clock rate, and the bit clock pulses are slightly delayed relative to the position clock pulses. Therefore, when bit clock pulse 49a applied to bit clock terminal 49' of register 46 occurs, register 46
The signal in the stage associated with terminal D0 of is shifted out of the register onto the binary data line and transferred to stages D1 and
The signal at 2 is similarly advanced one step to the right. Word clock pulse 47a is then returned to a high level, inhibiting further signal input to terminals D0, D1 and D2, after which bit clock pulses 49b and 49c are connected to terminals D1 and D1, respectively, until the occurrence of word clock pulse 47b. The original signal in stage D2 is shifted onto binary data line 50 while position clock pulses 44b-44g shift into register 42 the encoded pulse corresponding to the next data cell transition.

The logic used to recover the original signal binary data words from the pulses in register 42 is shown in FIGS.
This will be explained with reference to FIG. Stage S4 of register 42
For the first binary data word 001 which generated a pulse at , a signal is applied to terminal D0 via OR gate 51. Stage S1 or S6' of register 42
Since the pulses do not occur simultaneously, the signal level at the output of OR gate 52 is low and therefore
The signals from the . . . are inhibited from passing through the AND gate 53 and entering the OR gate 54. Therefore, the result of only the pulses in stage S4 of register 42 is an output of 001 on binary data line 50, as shown by the combination number 3 in FIG. next binary data word
111 generates signals into stages S1 and S4 of register 42. The signal present in stage S4 is again loaded via OR gate 51 to terminal D0 of register 46 and also to the input of AND gate 53, while the signal present in S1 is ORed with OR gate 52.
It is transmitted to terminal D2 of register 46 via gate 56. The signal applied to the output of OR gate 52 is also applied to the input of AND gate 53, which in turn provides a signal via OR gate 54 to terminal D1 of register 46, so that this signal is combined with the signal from stage S4. do. The final result is a signal stored in each stage of register 46, so that binary data word 111 is responsive to the signals in stages S1 and S4 of register 42, as indicated by the combination of serial number 14 in FIG. is played.

A signal is stored in stage S2 of register 42 when the next binary data word 010 is to be recovered.
The signal of stage S2 is transmitted to terminal D1 of register 46 via OR gate 54, and since no further decoding takes place during reading of this cell, the data word
010 is easily reproduced on binary data line 50. The next binary data word 110 is at stage S of register 42.
1 and S6. The signal in stage S1 passes through OR gate 52 and passes through AND gate 57.
and is also transmitted to the terminal D2 of the register 46 via the OR gate 56. At the same time, the signal in stage S6 passes through OR gate 58 and
It is transmitted to the input of gate 59 and to the other input of AND gate 57, thereby applying a signal to terminal D1 of register 46 via OR gate 54. Accordingly, word 110 is applied to binary data line 50 in response to the signals in stages S1 and S6 of register 42, as indicated by the combination of serial number 12 in FIG.
Finally, when restoring the final binary data word 101, a signal is stored only in stage S6' of register 42.
This means that when restoring the preceding binary data word, stage S
This signal is the same as that stored in 6. The signal of stage S6' passes through OR gate 52 and is sent to stage S5 of register 42.
Since there is no signal at S6 and S6, the signal is transmitted from the inverter 60 to the input of the AND gate 55, which simultaneously receives the high level signal at the other input. This causes the OR gate 51 to be connected to the terminal D0 of the register 46.
A signal is applied via. Therefore, the signal present at S6' of register 42 is applied to terminals D0 and D of register 46.
2 and provides the word 101 on the binary data line 50, as indicated by the combination of serial number 9 in FIG.

The binary data word that the circuit of FIG. 9 restores in response to other signal combinations in stages of register 42 is
It is shown in FIG. 10, which corresponds to the encoded truth table of FIG.

In addition to the features mentioned above, some other features of the code of the invention are also of interest and can be appreciated in this respect. Referring to FIG. 10, it can be seen that a total of 23 "1's" representing signal transitions are generated at various positions for all possible combinations. Of these, 16 "1's" (encircled by a dotted line) occur in a double window, i.e., a signal that is an overlapping position represented by a combinatorial logic that can be expressed in the form of the following logical equation: The transition occurs at either the transition position P5 or P6, or the position P6' or P1.

D0=P4+P2・(P5+P6) +(P1+P6′)・(P5+P6) D1=P2+(P1+P6′)・(P5+P6) +(P1+P6′)・P4 D2=(P1+P6′)+P3 Here, the dot represents AND. , + indicates OR,
- represents NOT. Therefore, about two-thirds of the signal transition
is positioned to reduce timing tolerance. Furthermore, the combinations of serial numbers 5, 6, 10, 14, and 15 that have a double window state are:
Since there are only three or four position spaces between "1" and "1" of such signal transition combinations, they are relatively more packed than other combinations.
A total of 10 transitions are under such relatively congested conditions, and 6 of this total 10, or about two-thirds
signal transitions occur in double windows, thereby reducing timing tolerance.

A data recording and restoring system incorporating the encoding and decoding circuits of FIGS. 6 and 9 is shown in FIG. 12, with the encoding circuit 61 corresponding to FIG. 6 and the decoding circuit 62 corresponding to FIG. 9. Timing device 63 provides various clock signals and read and record signals used for recording and restoring data, respectively. Figure 11a
As previously discussed with respect to FIG. 11b, the position clock speed determines the data recording and reading speed. In read mode, the position clock signal provided by timing device 63 is provided by write clock generator 64, which may be, for example, a constant frequency crystal oscillator or an oscillator synchronized to the speed of the magnetic storage medium on which data is to be recorded. derived. 2 to be recorded
The decimal data is applied to the encoding circuit 61 which generates the 3PM encoded signal described above. The encoded signal then passes through a write signal processing circuit 65, a write driver 66 and a read/write switch 67 to a magnetic head 68 which records each signal transition of the encoded signal in the form of a corresponding magnetic flux transition to a storage medium 69. transmitted to.
Write signal processing circuit 65 may include signal processing circuitry that interfaces with the write driver to enhance the quality of magnetic recording.

In the restoration mode, the magnetic head 68 passes through the preamplifier 70 and the readout signal processing circuit 71 to the decoding circuit 6.
A signal is generated in response to each magnetic flux transition on the storage medium 69 for transmission to the inputs of 2. The signal provided by the magnetic head is in analog form and includes rising and falling portions representing successive magnetic flux transitions on the storage medium. Read signal processing circuit 71 operates to convert the analog signal into a stream of encoded signal pulses, each pulse corresponding to a magnetic flux transition on the storage medium.
The instants of occurrence of individual pulses in the encoded signal pulse stream do not coincide with the signal transitions of the recorded encoded signal due to bit shifts and other distortions inherent in the recording and restoring process. For this purpose, the pulse stream of the encoded signal is transmitted not only to the decoding circuit 62 but also to the readout clock generator 72.
It can also be added to The read clock generator operates, for example, at a frequency that is a harmonic of a frequency corresponding to the period of the minimum spacing between each signal transition, or
More precisely, a phase-locked oscillator can be provided which is synchronized by the coded signal pulse stream to operate at a frequency equal to 2/T, which is equivalent to the position clock rate. The position clock speed is controlled by the coded signal pulse stream and the decoding circuit 6
2 operates in the manner described above to reproduce the original binary data at its output.

A preferred embodiment according to the invention is provided such that each binary data word consists of three bits and is indicated by a signal transition at one or two selected positions of a total of six positions within the data cell. Although described in terms of an encoding scheme, it is recognized that other logical forms may be utilized within the scope of the present invention. For example, 2 each
decimal data words each of length equal to 1.5T,
It can be represented by signal transitions in one or both of two adjacent data cells such that each cell corresponds to 1.5 binary data bits. This type of encoding scheme is shown in FIG. It will be seen that in this case the data cell boundary coincides with the signal transition position of P3. To maintain the desired minimum spacing of 3T/2 between signal transitions, the binary data word
The "1" bits of signal transition positions P2 and P1 of cell 1 and cell 2, respectively, corresponding to 100 must be integrated into one signal transition at signal transition position P3 of cell 1, that is, at the boundary between cell 1 and cell 2. It probably won't happen. Similarly, an integration operation is required for binary data words 000, 011 and 110, for which a signal transition occurs at signal transition position P2 in cell 2, and then in cell 1. It is followed by one of words 101, 110, or 111 in which a signal transition occurs at signal transition position P1.

It should be understood that in addition to changing the configuration of data cells for data words as described in the previous section, other encoding circuit configurations may be utilized. For example, a write data shift register responsive to a bit clock signal and having a capacity of only one data word may be configured to receive data words from the data shift register and implement the integrated features of the present invention in conjunction with the storage shift function of the write signal shift register. It can be used in combination with encoding logic circuit means operated with a word clock signal to generate a code signal applied to a modulator comprising a modified shift register controlled by a polyphase clock signal.

Although the invention has been described in detail with respect to particular embodiments thereof, it will be apparent that improvements and modifications may be made within the scope of the invention without departing from the true spirit and scope of the claims. Probably.

[Brief explanation of the drawing]

FIG. 1 shows the waveform of an encoded signal represented by various prior art codes and the code of the present invention for common binary data generated at a predetermined rate of 1/T.
FIG. 2 is a table showing the characteristics of the prior art code shown in FIG. 1 for a data bit degree of 1/T. FIG. 3 is a table showing the characteristics of the code of the present invention with respect to the data bit degree of 1/T. FIG. 4 is a diagram of a data cell of the present invention showing select signal transition positions used in the code of the present invention. FIG. 5 is a diagram showing the waveform and binary data pattern of the associated encoded signal generated according to the present invention. FIG. 6 is a circuit diagram showing encoded data partly in logical form and partly in block form according to the present invention. FIG. 7 is a truth table useful in understanding the encoding process of the present invention. FIG. 8 is a truth table for the circuit of FIG. FIG. 9 is a circuit diagram showing partly in block and partly in logic form for encoded data according to the present invention. FIG. 10 is a truth table for the circuit of FIG.
Figures 11a and 11b are similar to Figures 6 and 9, respectively.
1 is a timing diagram useful in understanding the operation of the illustrated circuit; FIG. FIG. 12 shows a recording and restoring system incorporating the circuits of FIGS. 6 and 9 for recording and restoring binary data encoded according to the present invention. FIG. 13 shows another arrangement of encoded signal positions according to the encoding technique of the present invention, such that each data word corresponds to two consecutive data cells with three signal positions per cell. It is a table.

Claims (1)

[Scope of Claims] 1. Binary digital data consisting of a series of data bits occurring at predetermined time intervals T, each at a selected one of a plurality of signal transition positions on a magnetic storage medium. A method of encoding by converting into a series of code signals corresponding to signal transitions in which each selected signal transition position is separated from each other by at least a predefined minimum interval, dividing the binary digital data into a plurality of data words each containing three data bits; converting each data word into a code signal or a combination of two code signals, each code signal being magnetically at a selected signal transition position of only the first five of six uniformly spaced predetermined signal transition positions occurring sequentially on a data cell of the storage medium. Corresponding to one signal transition, the length of the data cell with a time interval of 3T corresponds to one data word, and the combination of the two code signals corresponds to a signal transition position with a predefined interval equal to at least 1.5T. corresponding to a combination of two signal transitions; signal transitions within one data word spaced apart by less than a predefined minimum distance from the signal transition position corresponding to the code signal in an adjacent data word; comparing successively occurring data words in the binary digital data to determine whether there is a code signal corresponding to a signal transition at a position; two signal transitions spaced apart by less than a predefined interval; Corresponding to the two signal transitions at the position,
merging two code signals in each of two adjacent data words into a code signal corresponding to a signal transition at the boundary of two data cells corresponding to said two data words; 1. A method of encoding binary digital data, the method comprising: 2 binary digital data consisting of a series of data bits occurring at predetermined time intervals T, each corresponding to a signal transition at a selected one of a plurality of signal transition positions on the magnetic storage medium; Apparatus for encoding binary digital data by converting it into a series of code signals in which each selected signal transition position is separated from each other by at least a predefined minimum interval. a first shift register for receiving and storing bits as a preceding data word, a current data word and a following data word of three bits each in discrete storage locations; a first encoder and associated logic circuit connected to an output of the encoder for providing a code signal or a combination of two code signals representative of the current data word; Each code signal provided by and is a signal selected from only the first five of six uniformly spaced predetermined signal transition positions that occur sequentially in the data cells of the magnetic storage medium. Corresponding to a signal transition at a transition position, said data cell corresponds to one data word.
Two signal transitions corresponding to a combination of two code signals having a time interval length of 3T are at least
are placed at signal transition locations with a predefined spacing equal to 1.5T; furthermore, one code signal or a combination of two code signals for the current data word is placed in any one or two of the six discrete storage locations. a second shift register for storing the current data word in the first shift register; connected to the output for the subsequent data word of the current data word in the first shift register and corresponding to the signal transition position that is the first of the six signal transition positions within the data cell; a second encoder and associated logic circuitry having only an output corresponding to a data word having a code signal that corresponds to a data cell of the current data word and a data cell of the subsequent data word; has a code signal corresponding to a signal transition position adjacent to the boundary of the data cell of the current data word and a data cell of the subsequent data word. The corresponding code signal is prohibited from being stored in the second shift register, and the signal transition position at the boundary between the data cell of the current data word and the data cell of the subsequent data word is placed in place of the prohibited code signal. Assign one code signal to the corresponding storage location of the second shift register; and six signal transitions in the data cell connected to the output for the data word preceding the current data word in the first shift register; a third encoder and associated logic circuitry having an output only corresponding to a data word having a code signal corresponding to a signal transition position in a fifth of the positions; the previous data word being the data of the current data word; When the current data cell adjacent to the boundary between the data cell of the current data word and the data cell of the previous data word has a code signal corresponding to a signal transition position adjacent to the boundary between the cell and the data cell of the previous data word. inhibiting storage of a code signal corresponding to a signal transition position in a data cell of a data word in a second shift register;
An apparatus for encoding binary digital data, comprising means for sequentially receiving code signals stored in a shift register and generating signal transitions corresponding to the code signals. 3 The first, second and third encoders each have 2
An apparatus for encoding binary digital data as claimed in claim 2, which is a hex-octal encoder.