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JPS55138950A - Digital signal modulation and demodulation system - Google Patents

Digital signal modulation and demodulation system

Info

Publication number
JPS55138950A
JPS55138950A JP4709979A JP4709979A JPS55138950A JP S55138950 A JPS55138950 A JP S55138950A JP 4709979 A JP4709979 A JP 4709979A JP 4709979 A JP4709979 A JP 4709979A JP S55138950 A JPS55138950 A JP S55138950A
Authority
JP
Japan
Prior art keywords
bit
code
circuit
conversion
demodulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4709979A
Other languages
Japanese (ja)
Inventor
Masayoshi Kamo
Hajime Sasaki
Shigemasa Yoshida
Tadashi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4709979A priority Critical patent/JPS55138950A/en
Publication of JPS55138950A publication Critical patent/JPS55138950A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To make it possible to keep a high density record which is 1.5 times as high as the usual MFM modulation and demodulation, and to obtain a modulation and demodulation circuit for reading an information record, which makes a self- clock possible, by performing modulation and demodulation after a 4-bit code has been converted to a 8-bit code. CONSTITUTION:A NRZ data is given to ROM8, 9 at every 4 bits through the 8-bit series parallel conversion circuit 2. ROM8, 9 are 4-8 code conversion tables, and the conversion rules are that no bit ''1'' is continued in the conversion code, at least two bits ''0'' are put between adjoining bits ''1'', and also the eighth bit is necessarily made ''0''. The READ outputs of ROM8, 9 are subjected to code correction by the correction circuit 13 so that they can follow the aforementioned rules in case of the bit array between the adjoining codes, as well. The corrected 8-bit modulation output of the circuit 13 is provided to the recording unit through the parallel series conversion circuit 16. The demodulation circuit can be constituted easily by using the 8-4 code conversion ROM.
JP4709979A 1979-04-17 1979-04-17 Digital signal modulation and demodulation system Pending JPS55138950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4709979A JPS55138950A (en) 1979-04-17 1979-04-17 Digital signal modulation and demodulation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4709979A JPS55138950A (en) 1979-04-17 1979-04-17 Digital signal modulation and demodulation system

Publications (1)

Publication Number Publication Date
JPS55138950A true JPS55138950A (en) 1980-10-30

Family

ID=12765725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4709979A Pending JPS55138950A (en) 1979-04-17 1979-04-17 Digital signal modulation and demodulation system

Country Status (1)

Country Link
JP (1) JPS55138950A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184124A (en) * 1984-10-01 1986-04-28 Matsushita Electric Ind Co Ltd Digital modulator
JPH03137877A (en) * 1989-08-24 1991-06-12 Matsushita Electric Ind Co Ltd Binary information recording and reproducing system
JPH03145334A (en) * 1989-10-31 1991-06-20 Sony Corp Digital modulating method
JPH0646066A (en) * 1983-02-15 1994-02-18 Unisys Corp Encoding system for serial data transmission
WO2014142009A1 (en) * 2013-03-13 2014-09-18 株式会社イシダ Encoding apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5311011A (en) * 1976-07-14 1978-02-01 Sperry Rand Corp Method and device for coding or decoding binary degital data

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5311011A (en) * 1976-07-14 1978-02-01 Sperry Rand Corp Method and device for coding or decoding binary degital data

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0646066A (en) * 1983-02-15 1994-02-18 Unisys Corp Encoding system for serial data transmission
JPS6184124A (en) * 1984-10-01 1986-04-28 Matsushita Electric Ind Co Ltd Digital modulator
JPH03137877A (en) * 1989-08-24 1991-06-12 Matsushita Electric Ind Co Ltd Binary information recording and reproducing system
JPH0568785B2 (en) * 1989-08-24 1993-09-29 Matsushita Electric Ind Co Ltd
JPH03145334A (en) * 1989-10-31 1991-06-20 Sony Corp Digital modulating method
WO2014142009A1 (en) * 2013-03-13 2014-09-18 株式会社イシダ Encoding apparatus

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