JPS62147818A - Interference compensation circuit - Google Patents

Abstract

PURPOSE:To obtain a sufficient compensation effect to an optional signal independently of the modulation system of an interference signal by receiving an interference source signal through another antenna from an interference signal mixed in a main signal and adding the source signal to the interference component in the main signal with an equal amplitude and in an opposite phase. CONSTITUTION:An interference signal receiving from an auxiliary antenna 4 receiving only the interference signal component included in the main signal passes through a variable attenuator 8 and a variable phase shifter 9 and divided into two by a distributor 10. After the main signal including residual interference is subject to synchronization detection (12, 13) by a demodulator 100, the result is given to harmonic rejection filters 14, 15. The interference signal being an output of the distributor 10 is detected by using a carrier recovered by a main signal demodulator with orthogonal phase detectors 22, 23 and given to harmonic rejection filters 24, 25. The demodulation signal at the main signal is given to circuits 18, 19 taking the difference between the output of identification circuits 16, 17 and the input signal of the identification circuit to extract only the residual interference component only. To earn the control gain, the sum of products 27, 28 is taken and used a the control signal, and similarly, the difference between the products 29 and 30 is taken and used as a control signal to minimize the residual interference included in the main signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the configuration of an interference compensation circuit that eliminates interference from other systems that a digital signal receives in a digital communication system.

(Conventional technology) An example of the configuration of a basic conventional interference compensation circuit is shown in FIG.

The main signal received from the main antenna 1 is input to the combining circuit 3. On the other hand, the interference signal received from the auxiliary antenna 2 is set by the variable amplitude phase circuit 4 so that it has approximately the same amplitude and opposite phase as the interference component leaked into the main signal, and the signal is input to the combining circuit 3. Ru. The output of the synthesis circuit 3 is passed through a correlator 6 that correlates the remaining interference signal that cannot be completely canceled with the interference signal output from the auxiliary antenna, and the output is passed through an integrator 5 to generate a variable amplitude signal. Controls the phase circuit. The control loop operates such that the correlation between the residual interference signal and the interfering signal is minimized. Here, the input signal of the correlator 6 is a complex signal including amplitude and phase, and the variable amplitude phase shifter 4 is also treated as a complex quantity.

(Problems to be Solved by the Invention) In reality, an important issue is to realize an error signal generation circuit that extracts the residual interference component in the output of the combining circuit 3.

The present invention embodies the control part of the principle circuit configuration shown in FIG. The purpose is to obtain amplitude and phase control information for variable amplitude circuits and variable phase circuits by detecting the correlation of 100 output signals using the quadrature phase detector output, and to provide a simple circuit configuration for interference compensation circuits. do.

(Means for Solving the Problems) In the present invention, as a specific means for correlating the residual interference component contained in the main signal with the interference signal and obtaining amplitude and phase control information, the residual interference component and the interference signal are In order to decompose the signal into in-phase and quadrature components, the received main signal is passed through a demodulator that performs orthogonal phase coherent detection, and error information for the in-phase and quadrature components is obtained from the output. In addition, quadrature phase detection is performed using the carrier wave that has been regenerated from the interference signal by the main signal demodulator to obtain in-phase and quadrature signal components.

Then, the in-phase components of the error signal and the interference signal,
Alternatively, control information for the variable attenuator is obtained by correlating the orthogonal components and passing them through an integrator. Furthermore, control information for the variable phase shifter is obtained by correlating between the in-phase and quadrature components or the orthogonal and in-phase components of the error signal and interference signal and passing them through an integrator. Therefore, in order to control the variable attenuator and variable phase shifter, after decomposing the error signal and interference signal into in-phase and quadrature components, the external load circuit required to detect the correlation and the control circuit is as follows: , is characterized in that it only requires a quadrature detector for orthogonal phase detection of interference signals, a multiplier and an integrator for correlation detection.

(Example) A specific example of the present invention is shown in FIG. A main signal received from the main antenna 1 passes through a bandpass filter 2 and then a frequency converter 3 where it is converted into an IF signal. On the other hand, the auxiliary antenna 4 receives only the interference signal component included in the main signal.
The received interference signal passes through a bandpass filter 5 and is frequency-converted 6 by a local oscillator 7 common to the main signal side and converted into an IF signal. This interference signal passes through a variable attenuator 8 and a variable phase shifter 9, and is divided into two parts by a distributor 10, one of which is sent to a control section and the other to a combiner 11 for combining it with the main signal. The main signal before being combined here is expressed by the following equation.

Here, a 16CAM signal is considered as the main signal. Therefore, al, bk = (±1.±3)r(t,) is the impulse response of the entire system, and assuming a Nyquist transmission system, r
(0) = 1, r (kT) = O, where ≠0 is an integer, T is the clock period, and ω1 is the carrier wave angular frequency of the main signal. Further, a CW wave is considered as an interference component, where r is its amplitude, θ is its phase, and ω2 is each frequency of the interference component.

On the other hand, if the output signal of the distributor IO is normally controlled, it can be expressed by the following equation.

y, (1)=<,+, ,> ,,j(-2L+ 8
"Δe"π12>However, Δr and Δθ can be considered to be sufficiently small values.

As a result of adding equations (1) and (2), the residual interference component included in the main signal becomes as shown in the vector diagram of FIG. The main signal including residual interference is subjected to synchronous detection 12 by a demodulator 100.
．． 13, and then passed through harmonic component removal filters 14 and 15 to obtain in-phase and quadrature demodulated signals as shown in the following equation.

[-Δr-CO5(Δω 10)+r-Δθ ・5
in(Δω L+θ)] (3) [-Δr-sin(Δ
(all+θ) − “・Δθ−cos (Δωt, +θ)
(4) On the other hand, the interference signal of the distributor IO output is detected by the quadrature phase detector 22.23 using the carrier wave regenerated by the main signal demodulator, and after passing through the harmonic removal filter 24.25, the in-phase component given by the following equation is detected. and obtain the orthogonal component.

12(t,)=(r+Δr) −cos (ΔωL+θ
′÷Δθ+π)press−r−cos(Δωt+θtsu
(5) Q2(t,)=(r+Δr)−sin(Δ
ωt + θ° + Δθ + π) clause - "・5in (ΔωL÷θ'
) (6) Here, Δω represents the difference between ω and ω2.

θ" is the initial phase difference. Only the residual interference component is extracted by passing the demodulated signal on the main signal side through a circuit 18.19 that takes the difference between the output of the identification circuit 16.17 and the input signal of the identification circuit. The in-phase and quadrature error signals are as follows.

E, (L)=-Δr-cos (Δωt+θ)+r-Δ
θ−5in (ΔωL+θ)E q (j)= −
Δ r−8in(Δ ω t+θ)−r・Δ θ −c
os (Δ ω t+θ) where Equation (7), (8
) and the error component expressed by equation (5).

In order to perform correlation detection on the interference signal expressed by (6), the following calculation is performed. That is, i 2(t
) E r (t) (7)! 0r427 Matahaq 2
(t,) tE q(t)<7) By passing the result of 28 through the low-pass filter 34, the following formula is obtained. is used as a control signal. Also, Q2(t,
) and E, (t) product 29 or 12 (t, ) and E, 1 (
By passing the result of the inverse sign of the product 30 of t) through the low-pass filter 33, the following equation is obtained.

q2(L)x E+(t)=-j2(j)X Eq(1
:)=-r2·Δθ-cos(θ-θ') (10) Similarly, in order to obtain a control gain, the difference between the product of 29 and the product of 30 is used as a control signal. Here, θ and θ゛ are initial phases, and there is no need to consider that the amount of variation is almost no V, so if the initial adjustment is made so that θ = θ°, Equation (9)
From equation (10), there is a proportional relationship with Δr, and from equation (10), there is a proportional relationship with Δθ, so the amplitude of the variable attenuator is determined by equation (9), and equation (
As a result of 10), the phase of the variable phase shifter can be controlled. Lot in FIG. 1 indicates a control circuit. Therefore, Δr,
Δθ is optimally controlled and the residual interference component contained in the main signal is minimized.

Next, another specific embodiment of the present invention is shown in FIG. The main signal and the interference source signal are quadrature-phase detected using a carrier wave regenerated by a main signal demodulator, and the steps are performed until they are passed through a harmonic removal filter to obtain demodulated outputs of in-phase and quadrature components, respectively. is exactly the same. The demodulated signal of the main signal is identified by a discriminator 16.17, and the difference 18.19 between its output and the discriminator input signal is taken and the result is binarized to remove interference components remaining in the main signal. polarity can be obtained. Specifically, as shown in Figure 4.

By passing the four-level signal, which is a 16Q8M demodulated signal, through an A/D converter, the upper two bits become identification data, and the upper three bits indicate the polarity of the error signal, that is, the polarity of the residual interference component. In FIG. 3, the outputs of the subtracters 18 and 19 include information after the upper three bits, so to speak, and the polarity of this output corresponds to the upper three bits. Since the polarity is binary, for example, the positive polarity is "1" of the pulse, and the negative polarity is "0".
”, the output of 18.19 becomes exclusive OR29
can be done manually. The polarity of the error signal sampled every clock period T is expressed by the following equation.

sgn (E, (mT)) = sgn (−Δ
r-cos(Δω-mT+θ)+r-Δθ・5in(Δ
ω−mT+θ)) (11) sgn (E q (mT
) ) = Sgn (-Δr-sin(Δω・■T+
θ)-r-Δθ-cos (Δω-m'r+θ))
(12) On the other hand, by passing the polarity of the orthogonally detected output of the interference source signal through circuits 27 and 28, it is given by the following equation. However, as the sampling timing, it is necessary to use the timing signal reproduced by the main signal demodulator.

sgn (i2(mT)) = −sgn (co
s (ΔωφlT+θ')) (1:l)sgn(q
z(InT))=-sgn(sin(Δ(IJ ・m
T + θ°)) (th) Compared to equations (5) and (6), r is missing on the right-hand side above, but the above equation only takes the sign of the equation, and ``is positive, so this can be omitted. However, it is not a mistake.

Here, sgn(E, (mT)), sgn(Eq(m
')), sgn(i2(nlT)) and sgn
The following calculation is performed on (q 2 (mT) ). That is, Sgn (12(mT)) and sgn (E
t (mT) ), that is, by taking the exclusive OR 29 and passing it through the low-pass filter 38, the following equation is obtained.

sgn (i 2 (mT) ) x sgn (E
, (mT))=-sgn(-Δr°cos(θ-θ'
) + r−Δθ−5in(θ−θ゛)) Similarly, sgn (q 2 (mT) ) x sgn (E
q (mT) )=-sgn(-Δr-cos(θ-θ
°) + r・Δθ・5in (θ−θ°)) Similarly, sgn (q 2 (mT) ) x sgn (E
r (mT) )=-sgn(Δr-sin(θ-θ'
) + r−Δθ−cos(θ−θ゛)) Similarly, −sgn(i 2(mT))Xsgn(Eq(mT))
=-sgn(Δr-sin(θ-θ°)+"・Δθ・c
os (θ−θ゛)) Here, if we set θyuθ° as before, we get sgn(i 2(mT)) x sgn(E l ([I
IT))=sgn(q2(mT))xsgn(E, (n
lT))=+sgn(Δr) (1
9) sgn(q2(mT))xsgn(E,(mT))
=-sgn(i2(mT))xsgn(E,(mT)
)=-sgn(Δθ) (20)
Therefore, the amplitude of the variable attenuator 8 can be controlled using equation (19), and the phase of the variable phase shifter 9 can be controlled using equation (20). In the control circuit of 101, the results of equation (16) and equation (!7) are the same, and the results of equation (17) and equation (18) are the same, so both signals are added for the purpose of improving the control gain. An example is shown.

Above, in the circuits shown in Fig. 1 and Fig. 3, an example was shown where compensation is performed using a variable attenuator and a variable phase shifter in the IF band, but when compensation is performed using a variable attenuator and a variable phase shifter in the RF band. Same thing tomorrow.

In addition, although the explanation has been given using the CW wave as an example of an interference signal, the interference can be compensated for with the same circuit configuration since the same interference source as the interference component is received by a separate antenna. is possible.

Here, after passing the interference signal received from the auxiliary antenna through a variable phase shifter, one side is passed through a quadrature phase detector and the other is through a variable attenuator, and then combined with the main No. 8, that is, variable attenuation. A configuration may also be considered in which the interference signal is split before passing through the device. In this case, the level of the interference signal entering the quadrature phase detector is generally higher than in the above case because it is taken before the variable attenuator. Therefore, sensitivity can be improved during phase detection. The amplitude of the interference signal at the variable attenuator stage is determined by another value ``°'' instead of ``(r+Δr)''=r in equation (2).
Then, r'' and r are both positive values, and Equation (9).

It is clear that (10) and equations (19) and (20) hold similarly. Therefore, the amplitude and phase can be controlled in principle.

(Effects of the Invention) As explained above, in this compensation circuit, the interference signal mixed in the main signal is received by another antenna, and is added with equal amplitude and opposite phase to the interference component in the main signal. Therefore, a sufficient compensation effect can be obtained for any signal regardless of the modulation method of the interference signal, and the error signal generation circuit for extracting the interference component remaining in the main signal can be used for the main signal. Use the demodulator as is. Therefore, the newly added circuits are a quadrature phase detector that detects the interference signal in quadrature phase, an analog multiplier that correlates its output with the output of the error signal generation circuit, or a gain multiplier (exclusive OR circuit). The present invention has the advantage that it is possible to configure a control circuit for controlling the variable attenuator and the variable phase shifter with a simple circuit configuration using only the above-mentioned circuit and an integrating low-pass filter.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a vector diagram of a residual interference signal, Fig. 3 is a diagram showing another embodiment of the present invention, and Fig. 4 is a multi-value (four-value) identification Circuit (error signal generation circuit)
The input/output relationship diagram in FIG. 5 shows a conventional interference wave compensation circuit. Explanation of symbols (Fig. 1) l...Main antenna, 2.5-...Band filter,
: I, 6-... Frequency converter, 4... Auxiliary antenna,
7... Receiving local oscillator, 8... Variable attenuator, 9...
・Variable phase shifter, 10-...Distributor, 11...Synthesizer, 12, 13, 22, 2]...Detector, 2
1.26-90° phase shifter, 20-...regenerated carrier wave, +4
．． 15, 24.25...Low pass filter, 16.17-
...Identification circuit, 18.19-...Attenuator, 27.2
8,29. :10...multiplier, 31-...adder,
32--Attenuator, 33.34--Integrator,
100--Demodulator, +01--Control circuit, 102.10:J--Error signal generation circuit.

Claims (2)

[Claims] (1) A main antenna for receiving the main signal, an auxiliary antenna for receiving the interference signal, a variable phase circuit and a variable amplitude circuit connected in cascade to each other that vary the amplitude and phase of the output of the auxiliary antenna, and the variable a combining circuit (11) that combines the main antenna output with an interference signal whose phase and amplitude are controlled by the phase circuit and the variable amplitude circuit; and a regenerated reference carrier wave using the output of the combining circuit as an input signal A first quadrature phase synchronous detector (12, 13) that decomposes the in-phase component and quadrature component, and an interference component that remains in the output of the synthesis circuit using the outputs of the quadrature phase detector for the in-phase component and quadrature component as input signals, respectively. two error signal generation circuits (102, 103) for detecting the interference signal, and a circuit common to the quadrature phase synchronized detector (12, 13) using the interference signal as an input signal in order to decompose the interference signal into an in-phase component and a quadrature component. a second quadrature phase detector (22, 23) that performs quadrature phase detection using a reference carrier wave; and a quadrature phase detector (22, 23).
and the two outputs of the error signal generating circuit (102, 103) independently.
Two or more multipliers (27, 28, 29, 30) and two or more integrators (33, 34) whose output signals are input signals
An interference compensation circuit characterized in that the output of the integrator (33, 34) is used as an amplitude and phase control signal for the variable amplitude circuit and the variable phase circuit. (2) A main antenna for receiving the main signal, an auxiliary antenna for receiving the interference signal, a variable phase circuit and a variable amplitude circuit connected in cascade to each other that vary the amplitude and phase of the output of the auxiliary antenna, and their outputs. a combining circuit (11) for combining the output of the main antenna with the output of the main antenna; a two-way divider inserted between the variable phase circuit and the variable amplitude circuit for branching the output of the variable phase circuit; A first quadrature phase synchronized detector (12, 13) that uses the regenerated reference carrier wave as an input signal to decompose it into an in-phase component and a quadrature component.
and two error signal generation circuits (102 and 10
3) In order to decompose the interference signal into an in-phase component and a quadrature component, the branch output signal of the two-way splitter is used as an input signal, and a common reference carrier wave is used as the quadrature phase synchronized detector (12, 13). A second quadrature phase detector (22, 2
3), and at least two or more multipliers (27, 28) each independently correlating the output signal of the quadrature phase detector (22, 23) with the two outputs of the error signal generation circuit (102, 103). , 29, 30) and two or more integrators (33, 34) whose outputs are used as input signals, and the outputs of the integrators (33, 34) are input to the variable amplitude circuit and the variable phase circuit. An interference compensation circuit characterized in that the amplitude and phase control signals are used as control signals.