JPS62233943A - Interference compensation circuit - Google Patents

Abstract

PURPOSE:To eliminate an interference component leaked in a main signal by detecting an interference signal, supplying its signal to a bipolar variable attenuator whose polarity is varied in bipolar and adding the result to an output of a detector of the main signal. CONSTITUTION:The main signal is inputted to a demodulator 100. Phase detectors 8,9 apply orthogonal phase detection to the signal to obtain an in-phase and an orthogonal base band signal. Further, an interference signal is supplied to a phase detector 10, from which a base band signal is obtained. The interference signal is used, two bipolar variable attenuators 16,17 adjust the bopolar amplitude and the result is added to the in-phase and orthogonal component base band signals of the main signal. In order to detect a residual interference component, the component is fed to error signal generating circuits 20, 21, and on the other band, the base hand signal of the interference signal is identified by an identifier 22 by using a clock signal 23 recovered by the main signal. The identification signal output and the output of the circuits 20, 21 of the main signal side are subject to correlation detection to control the bipolar variable attenuator.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the configuration of an interference compensation circuit that eliminates interference from other systems that a digital signal receives in a digital communication system.

(Prior art) A conventional configuration IPlj is shown in FIG.
7881) FIG. 4 will be explained in detail below. The signal received by the main antenna 1 for receiving the main signal is passed through a band pass filter 2 to improve S as necessary, and then passed through a frequency converter 3.
is converted into an IP band. On the other hand, the interference signal received by the auxiliary antenna for interference signal reception is passed through a band-pass filter 5 to improve the sA if necessary, and then transferred to the IF band by a frequency converter 6 using a local oscillator 7 common to the main signal. converted. In order to adjust the phase and amplitude of the interference signal converted to the IF band, it passes through a variable phase circuit 9 and a variable amplitude circuit 8 so that it has almost the opposite phase and the same amplitude as the interference component leaking into the main signal. controlled. By adding the interference signal and the main signal in the combining circuit 11, the interference component in the main signal is removed. Next, a method of controlling the variable phase circuit and variable amplitude circuit will be described. 11 is input to the demodulator 100. In the demodulator 100, the input signal is subjected to quadrature phase detection 12.13 using the regenerated reference carrier wave 20, and the output signals are passed through harmonic removal filters 14.15 to obtain in-phase and quadrature baseband signals. . The obtained baseband signals are input to error signal generation circuits 102 and 103, respectively.

Here, a 16QAM signal is considered as the main signal. 16 Q
When AM is demodulated, a four-level baseband signal is obtained. Fifth
As shown in the figure, by passing the 4f[signal through the φ conversion word tail having an output of 3 bits or more, the upper 2 of the outputs are
The bit represents an identification signal, and the third most significant bit represents an error signal.

Therefore, the residual interference component can be detected using the output of the third most significant bit.

On the other hand, the interference signal is branched by a branching circuit 10, one of which is subjected to quadrature phase detection using the main signal reference carrier 20 by 22.23, passed through a harmonic removal filter 24.25, and reproduced by a main signal demodulator. Using the clock signal, the discriminator 2
7.28 to obtain the interference signal identification result. Then, correlation detection is performed between the identification results of the in-phase and quadrature component interference signals and the error signal. In other words, the result of multiplying the in-phase interference error signal and the in-phase error signal by 30 (this is done digitally here), the orthogonal interference identification signal, the orthogonal error signal, and the total The result obtained by adding the result multiplied by 29 in an analog manner using resistance circuits 33 and 34 is integrated by an integrator 38, thereby providing a control signal for the variable amplitude circuit 8. In addition, the result of multiplying the orthogonal interference identification signal and the in-phase error signal by 31, and the in-phase interference identification signal and the orthogonal error signal are multiplied by 31.
A signal obtained by subtracting the result of multiplication by 2 by 35.36 is passed through an integrator 37 and integrated, thereby providing a control signal for the variable phase circuit 9. As described above, interference compensation can be automatically performed.

(Problems to be Solved by the Invention) However, in the conventional method, since interference wave compensation is performed in a high frequency or intermediate frequency region, there is a drawback that circuit elements that are manufactured at high speed are required. Also, because of its high speed operation, it was unsuitable for digital circuits.

The present invention aims to improve this drawback and provide an interference compensation circuit that operates in the baseband region.

(Means for Solving the Problems) One feature of the present invention for achieving the above object is that it includes a main antenna for receiving a main signal, an interference signal receiving means, and a signal regenerated from the output of the main antenna and the main signal. A quadrature phase detector that inputs a reference carrier wave and decomposes it into an in-phase component and a quadrature component, and is coupled to the interference signal receiving means, and performs phase detection on the signal from the circuit by using the same reference floor transmission as the quadrature phase detector. a phase detector, first and second bipolar variable attenuators receiving the output of the phase detector, an in-phase component and a quadrature component of the output of the quadrature phase detector, and the first and second bipolar variable attenuators; first and second adders that each calculate the sum of the output of the bipolar variable attenuator, first and second error signal generation circuits that each use the output of the adder as an input signal, and the phase detector. a first multiplier that provides a multiplier between the output of the phase detector and the output of the first error signal generation circuit; and a second multiplier that provides the product of the output of the phase detector and the output of the second error signal generation circuit. a first integrator coupled to the output of the first multiplier, and a second integrator coupled to the output of the second multiplier; The interference compensation circuit controls the first bipolar variable MD device and controls the second bipolar variable Md device using the output of the second integrator.

(Function) Conventionally, when varying the amplitude and phase of an interference signal in the carrier band, a variable amplitude circuit and a variable phase circuit were used, but in the present invention, after detecting the main signal and the interference signal, the interference signal is detected in the baseband band. Make compensation. In other words, after detecting the interference signal, the signal is passed through a bipolar variable Md device that can change the polarity between positive and negative polarities, and is added to the main signal detector output to detect the interference components that have leaked into the main signal. This method differs from the conventional technology in that it erases . Since it operates in the low frequency baseband band, it is easy to implement the circuit.
It can also be realized by a digital circuit.

(Example) A specific example of claim (1) is shown in FIG. This will be explained in detail below. The main signal received from the main antenna 1 for receiving the main signal is passed through a band pass filter 2 to improve the S/N f if necessary, and then converted to an IF signal by a frequency converter 3. On the other hand, the interference signal received from the auxiliary antenna 4 is
After passing through the lff1 overfilter 5, it is converted into the IP band by a frequency converter 6 using a local oscillator 7 common to the main signal. The main signal converted to the IF band is input to the demodulation 6100. In the high frequency regulator, quadrature phase detection is performed by the regenerated reference carrier wave 12 and 8 and 9, and the harmonic removal filter 13
14, in-phase and quadrature baseband signals are obtained. Further, the interference signal converted to the optical F band is phase-detected by 1o using the reference carrier wave regenerated by the main signal demodulator, and then passed through the harmonic removal filter 15 to obtain the baseband signal of the interference signal. Using this interference signal, two bipolar variable attenuators 16 and 17 adjust the positive and negative amplitudes, and then in-phase and quadrature The component baseband signal is calculated by 7JO (1s, 19). By boosting the signal, most of the interference components that have leaked into the main signal are eliminated. An error signal generation circuit (20,
21). Consider, for example, a 16QAM signal as the main signal. The base gundo signal after demodulation becomes a four-level signal. If an A/D converter with an output of 3 bits or more is used as the error signal generating circuit 20.21, as shown in FIG.
The second bit causes the error signal to fluctuate. Here, the A//D converter is sampled using the clock signal 23 reproduced by the demodulator. On the other hand, the baseband signal of the interference signal is identified by the discriminator 22 using the clock signal 23 reproduced from the main signal. This identification signal output corresponds to the main signal. That is, by performing the summation 25 (here, an EX-θR circuit is sufficient since it is a 2-digit digital signal) of the interference signal identification result 22 and the output of the in-phase error signal generation circuit 21, and integrating (26), Ambidextrous variable # on the same phase side, sad instrument 16
control. Further, the bipolar variable attenuator 17 on the orthogonal side is controlled by multiplying the interference signal identification result 22 and the output of the orthogonal erroneous i signal generation circuit 20 by 24 and integrating (27''). Interfering components that have leaked into the system can be automatically removed.

An embodiment of claim (2) is shown in FIG. The difference from FIG. 1 in claim (1) is that all interference compensation is performed by digital processing.

That is, the l converter 21 has sufficient quantization accuracy for the in-phase and quadrature baseband signals demodulated from the main signal.
Digitize by 20.

At this time, the clock signal 23 reproduced from the main signal is used as the sampling timing. Further, the detected interference signal is also digitized by the A/D converter 22 having sufficient quantization accuracy using the clock signal 23 regenerated from the main signal. As an example, the main signal is 16 QAM, A/'I) K
Consider an 8-bit converter.

The interference signal, represented by 8 bits, is input to two bipolar variable attenuators 30, 31. Bipolar variable attenuator 30.31
For example, an 8-bit x 6-bit digital multiplier capable of performing positive and negative operations is used.

(6 bits are control signals) Output 8 of bipolar variable attenuator 30
The output of an 8-pit + 8-bit full adder 32 which adds the bit (if correct) and the 8-bit output from the in-phase converter 21 of the main signal is the in-phase component from which interference has been removed.

In addition, 8 bits of the output of the bipolar variable attenuator 31 and 8 bits of the output of the ADD converter 20 on the orthogonal side of the main signal are combined.
At the output of the bit+8 bit full adder 33, an orthogonal component from which interference has been removed is obtained. Full adder 32, . The upper 2 bits of the 33 output are the identification signal of the 4-level signal from which interference has been removed, and the upper 3 bits and below are error components. In particular, the third most significant bit represents the direction of the error signal. Further, in order to digitize the interference signal, the most significant bit of the output of the converter 22 ignores the polarity of the interference signal. In Figure 2, when correlating this interference signal with the remaining error signal,
It shows IIFIJ that focuses only on polarity. That is, the polarity of the interference signal (the most significant bit output of the A/D converter 22) and the error polarity on the in-phase side (the third most significant bit of the output of the full adder 32) are combined in the exclusive OR (EX-θR) circuit 35. After being multiplied by , the signal is passed through an integrator 36 that digitally integrates the signal, and its 6-bit output is used as a control signal for the bipolar variable attenuator 30 on the in-phase side. In addition, multiplication 3 of the polarity of the interference signal and the error polarity on the orthogonal side (the upper 3rd bit of the output of the full adder 33)
After performing step 4, an integrator 37 integrates the digital data.
The 6-bit output is used as a control signal for the bipolar variable attenuator 31 on the orthogonal side. In other words, all interference compensation is performed in the baseband by digital processing. Here, the digital integrator may be, for example, a reversible counter. In other words, if you want to input the multiplication result to the up/down'' terminal of a reversible counter and obtain, for example, a 6-bit control output, prepare a reversible counter with 6 or more stages and input the upper 6 bits of the output. This can be easily achieved by using the integrator output.

Claims (1) and (2) have the advantage that the circuit configuration is simple because a phase detector is used to detect interference No. 15, but there are restrictions on the modulation method of the interference signal. In other words, here, in order to perform interference compensation in the baseband after demodulation, as an interference signal,
An amplitude modulated signal will work normally, but it is impossible to compensate for quadrature amplitude modulation (QAM). FIG. 3 shows an embodiment of claim (3) as an interference compensation circuit capable of compensating for interference signals of any modulation method. The difference from FIG. 2, which is an embodiment of claim (2), is that while FIG. 2 uses a phase detector to detect the interference signal, FIG. 3 uses a quadrature phase detector instead of a phase detector. Use a detector. Therefore, a converter for converting the quadrature-phase detected interference signal into a di-notional signal, two bipolar variable attenuators whose output is used as an input signal, two full adders, two multipliers, and two integrators are also required. becomes. However, it has the advantage of not being restricted by the modulation method of the interference signal.

(Effects of the Invention) As explained above, when removing interference components that have leaked into the main signal, the operating speed of the component circuits is is lower, and the feasibility is higher than when removing in the carrier band. In addition, as claimed in claim (2), by performing interference compensation entirely in the baseband band, high accuracy and no adjustment are achieved, and L
It has the advantage of being suitable for SI.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interference compensation circuit according to the present invention, and FIG.
FIG. 3 is a block diagram of another embodiment of the interference compensation circuit according to the present invention, FIG. 3 is a block diagram of yet another embodiment of the interference compensation circuit according to the present invention, and FIG. 4 is a block diagram of a conventional interference compensation circuit. , FIG. 5 is an explanatory diagram of the error signal generation circuit. (Explanation of symbols; Fig. 1) 1... Main antenna, 4... Auxiliary antenna, 2, 5...
・・Band pass filter, 3, 6 ・・Frequency converter, 7
...Local oscillator, 8,9.10...Phase detector, 1
1... 90° phase shifter, 12... Regenerated carrier wave, 13.
14゜15...Harmonic removal filter, 16.17...
- Bipolar variable attenuator, 18.19... adder, 20.
21...Error signal generation circuit, 22...Identification circuit, 2
3...Regenerated clock signal, 24.25...EX-0
8 circuits, 26°27... Integrator, 100... Demodulator, 101... Control circuit.

Claims (3)

[Claims] (1) a main antenna for receiving the main signal; an interference signal receiving means; a quadrature phase detector that inputs the output of the main antenna and a reference carrier wave regenerated from the main signal and decomposes it into an in-phase component and a quadrature component; and the interference signal. a phase detector that is coupled to the receiving means and performs phase detection on the signal from the circuit using the same reference carrier as the quadrature phase detector; and first and second bipolar devices that receive the output of the phase detector as inputs. a variable attenuator; an in-phase component and a quadrature component of the output of the quadrature phase detector;
first and second adders that each calculate the sum of the outputs of the first and second bipolar variable attenuators, and first and second error signal generators that use the outputs of the adders as input signals, respectively. a first multiplier for providing the product of the output of the phase detector and the output of the first error signal generation circuit; a second multiplier that provides a product; a first integrator coupled to the output of the first multiplier; and a second integrator coupled to the output of the second multiplier; An interference compensation circuit characterized in that a first bipolar variable attenuator is controlled by the output of the integrator, and a second bipolar variable attenuator is controlled by the output of the second integrator. (2) The first and second adders are digitally operated full adders, the first and second bipolar variable attenuators are digitally operated, and each output of the phase detector Claim 1, characterized in that an A/D converter for sampling and quantization is provided between the full adder and the bipolar variable attenuator, and is operated by a clock signal recovered from the main signal. Interference compensation circuit as described. (3) a main antenna for receiving the main signal, an interference signal receiving means, a first quadrature phase detector that inputs the output of the main antenna and the reference carrier wave regenerated from the main signal and decomposes it into an in-phase component and a quadrature component; a second quadrature phase detector coupled to the interference signal receiving means and decomposing the signal from the circuit into an in-phase component and a quadrature component using the same reference carrier as the first quadrature phase detector; first, second, third, and fourth A for sampling and quantizing in-phase component outputs and quadrature component outputs of the first and second quadrature phase detectors using the reproduced clock signal;
/D converter; first and second bipolar variable attenuators coupled to the output of the third A/D converter; and third and fourth bipolar variable attenuators coupled to the output of the fourth A/D converter. a bipolar variable attenuator; and a first bipolar variable attenuator that adds the outputs of the first and third bipolar variable attenuators.
a second full adder that adds the outputs of the second and fourth bipolar variable attenuators; and an output of the first full adder and an output of the second A/D converter. a third full adder that adds together; a fourth full adder that adds the output of the second full adder and the output of the first A/D converter; and the third and fourth full adders. output of the device and the third and fourth
four multipliers that perform multiplication with the output of the A/D converter, and four integrators respectively coupled to the output of each multiplier, and each of the bipolarities is variable according to the output of each integrator. An interference compensation circuit that controls an attenuator.