JPS62143478A - Junction-type field effect transistor - Google Patents

Abstract

PURPOSE:To decrease the area of a chip, by providing an n<+>-type resistance region on the surface of a gate region for incorporating a resistor required for constructing the circuit within a junction-type FET. CONSTITUTION:An n-type epitaxial layer 2 formed on a p-type semiconductor substrate 1 is divided by p<+>-type isolation regions 3 into an island. On the island region 4 thus formed, a p-type gate region 5 is provided. Further, an n<+>-type resistance region 6 is formed on the surface of the region 5. Source and drain regions are provided, respectively, by the sections of the region 4 divided by the region 5. The source region is provided with an n<+>-type contact region 7 and a source electrode 8, and the drain region is provided with an n<+>-type contact region 7 and a drain electrode 9. A ground potential is applied to the region 5 through the region 3, so that the transistor operates with the grounded gate by utilizing the substrate 1 as a back gate and the region 4 as a channel region.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention relates to a junction field effect transistor (hereinafter referred to as J-FET).
), especially for J-FETs with built-in resistors.
-Relating to FET.

(b) Prior Art Conventionally, a J-FET coexisting in a bipolar IC has been described, for example, in Japanese Patent Application Laid-Open No. 59-220962.

Figures 4 and 5 show such a J-FET, in which an N-type epitaxial layer (12) formed on a P-type semiconductor substrate (11) is separated into islands by a P+ type isolation region (13). A region (14) is formed, and P is extended on the surface of this island region (14) until its both ends overlap the separation region (13).
It has a structure in which a type gate region (15) is provided, and a source electrode (18) and a drain electrode (19) are arranged in an island region (14). A ground potential is applied to the gate region (15) via the separation region (13), and a gate grounding operation is performed using the substrate (11) as a bank gate and the island region (14) as a channel region. Note that the source is connected to the pole (18) and the drain electrode (
19) are taken out through N-type contact regions (19) (19), respectively.

A J-FET having such a structure is often used as a high-resistance device in a bipolar IC, and therefore, the J-FET is formed so that the channel length is longer than the channel width.

(c) Problems to be Solved by the Invention However, such a structure has the disadvantage that the pattern size is large in order to increase the channel length, and the chip area increases.

(Means for Solving the Problems) The present invention has been made in view of the above-mentioned drawbacks.
) The J-FET is characterized in that an N-type resistance region (6) is provided on the surface, and a resistor necessary for the circuit configuration is built into the J-FET.

(*) Effect According to the present invention, the J-FET and the resistor can be formed in the same pattern area as the conventional J-FET, so the overall chip area can be reduced.

(f) Example The present invention will be described in detail below with reference to the drawings.

1 to 3 show a J-FET according to the present invention, in which an N-type epitaxial layer is formed on a P-type semiconductor substrate (1).
An island region (4) is formed by separating 2) into an island shape by a P2 type separation region (3), and a P type gate is formed on the surface of this island region (4) with both ends thereof extending until it overlaps the separation region (3). A gate region (5) is provided, and a gate region (N+ type low resistance region 6) is further formed on the surface of the gate region (5) parallel to its longitudinal direction, and is used as a resistor. It has a structure in which one of the island regions (4) is a source region and the other is a drain region, and a source electrode (8) and a drain electrode (9) are attached via N" type contact regions (7), respectively. Separation region (3) in gate region (5)
A ground potential is applied through the substrate (1), and a gate grounding operation is performed using the substrate (1) as a back gate and the island region (4) sandwiched between the gate region (5) and the substrate (1) as a channel region.

Note that electrodes (10) (10) are also provided at both ends of the resistance region (6).

The most distinctive feature of the present invention is that a resistance region (6) is provided on the surface of the gate region (5). In this way, in the J-FET used with the gate grounded, the gate region (5) is at the ground potential and is only a region to which a potential is applied, so even if a resistance region (6) is formed there and a current flows, the PN This structure does not affect the operation of the J-FET due to junction separation, and since the channel length is longer than the channel width, there is sufficient space. Since the J-FET and the resistor necessary for the circuit configuration can be formed in the same pattern area as the J-FET, the overall degree of integration can be increased and the chip area can be reduced.

The present invention can also be used when it is desired that different wiring lines intersect with each other on the gate region (5). That is, by extending one wiring through the resistance area (6) and extending the other wiring over the resistance area (6), it is possible to cross over the gate area (5). .

(g) As described in detail, according to the present invention, a J-FET and a resistor can be formed in the same occupied area as a conventional J-FET, increasing the degree of integration and reducing the chip area. It has the advantage of being able to

Furthermore, since different wiring lines can cross each other on the gate region (5), there is an advantage that the degree of freedom in wiring increases and design becomes easier.

Furthermore, the present invention has the advantage that it does not require any additional steps and can be immediately incorporated into the current Novibora process.

[Brief explanation of drawings]

1 to 3 are plan views for explaining the present invention, respectively;
II, II sectional view, nm line sectional view, Figures 4 and 5
The figures are a plan view and a sectional view taken along the line ■-■ showing a conventional J-FET. (1) is a P-type semiconductor substrate, (3) is a P0-type isolation region, (
5) is a P-type gate region, and (6) is an N3-type resistance region. Applicant: Sanyo Electric Co., Ltd., and 1 other representative: Shizuo Sano, patent attorney Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] (1) An island region formed by separating an epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type by an isolation region of one conductivity type, and a gate region of one conductivity type whose both ends are extended until they overlap with the isolation region. A junction field effect transistor which operates with a gate grounded using the island region as a channel region, characterized in that a resistance region of an opposite conductivity type is formed on the surface of the gate region, and this is used as a resistor. Field effect transistor.