JPS61256665A - Input protection device for semiconductor integrated circuits - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input protection device for a semiconductor integrated circuit, and particularly to an input protection device for a semiconductor integrated circuit.
The present invention relates to an input protection device comprising a polysilicon resistance layer containing conductivity type impurities and a diffusion low resistance layer of one conductivity type.

[Conventional technology]

Conventionally, for example, as an input protection device in a complementary MO8 structure, as shown in FIGS. Ohmic connection is made to one end of the diffusion low resistance layer 33, and the other end of this N type diffusion low resistance layer 33 is
) is guided by the input.

Next, the other end of the polysilicon resistance layer 31 is connected to a bonding pad 34, and the P-type well 32 is connected to a VS8
It is ohmically connected to the power supply line 35. Note that the diode D is formed of a P-type well 32 and an N-type diffusion low resistance layer.

[Problem that the invention seeks to solve]

In the conventional input protection device described above, since the polysilicon layer 31 containing N-type impurities is the same wiring layer as the gate electrode layer of the transistor element, the polysilicon resistance layer 31 is formed in a planar manner from the N-type diffused low resistance layer 33. They had to be placed far apart from each other, requiring a large area in terms of pattern layout. In addition, the polysilicon resistance layer 31 and the diffusion low resistance layer 3
At the connection point with No. 3, the electric field concentration is greatest at the moment the surge voltage is applied, so there is also a drawback that the protection ability is limited at the connection point.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input protection device for a semiconductor integrated circuit which eliminates the above-mentioned drawbacks, allows for high-density integration of semiconductor integrated circuit devices, and has improved protection capability.

[Means for solving problems]

The configuration of the input protection device of the present invention includes input bonding and
A polysilicon resistance layer containing an impurity of one conductivity type is ohmically connected to a pad at one end, and a diffused low resistance layer of one conductivity type is connected to the other end of this polysilicon resistance layer. In the input protection device for a semiconductor integrated circuit whose other end is connected to an input gate to be protected, the polysilicon resistance layer is disposed on the upper surface of the diffused low resistance layer.

[Example] Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view of an input protection pattern in an input protection device according to an embodiment of the present invention, taking the input protection device of a complementary MO8 integrated circuit as an example. Figure 2 is A- of Figure 1.
It is a sectional view taken on the A' braid.

1 and 2, one end of an Nm diffused low resistance layer 12 formed on a P-type well 11 and a polysilicon resistance layer 1 containing an N-type impurity as a second layer different from the gate electrode layer.
One end of 3 is ohmically connected with a contact 14. The ohmic-connected polysilicon resistance layer 13 is formed at the upper part 6000 of the N-type diffused low resistance layer 12, and after obtaining a predetermined resistance value, it is connected to the aluminum 15 of the bonding pad and the contact 16. Connected. on the other hand,
The other end of the N-type diffusion low-resistance layer 12 connects to the one-way gate electrode G after a predetermined resistance value is obtained. Note that the P-type well 11 has a P-type diffusion layer 17 formed in the P-type well 11, J',
V8! It is ohmically connected to the i power supply a18 via a contact 19.

〔Effect of the invention〕

As explained above, according to the present invention, the conventional polysilicon resistance layer, which is the same as the gate electrode wiring layer, is replaced with a second polysilicon resistance layer that is different from the gate electrode wiring layer. The polysilicon resistance layer can be placed on the diffused low-resistance layer], thus eliminating the need for the placement area of the polysilicon resistance layer, which allows for higher density integration. Since it is placed above the diffusion low resistance layer, at the moment when a surge voltage is applied,
Due to the coupling capacitance between the polysilicon resistance layer and the diffused low resistance layer, an electric field is distributed and applied over the entire surface of the diffused low resistance layer, so the electric field is concentrated at the connection between the polysilicon resistance layer and the diffused low resistance layer. ], the effect is that the input protection capability can be improved.

Note that the present invention is applicable not only to complementary MO8 structures but also to ordinary MO8 structures.

[Brief explanation of drawings]

FIG. 1 is a plan view of an input protection device for a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line A- in FIG. 1, and FIG. 3 is a plan view of a conventional input protection pattern. FIG. 4 is an equivalent circuit of FIG. 3. In the same figure, 11.32...P-type well, 1
2.33...N-type diffusion low resistance layer, 13...
・Second layer N-type polysilicon resistance layer, 31...1
Layer N-type polysilicon resistance layer, 14.16.19...
. . . Contact hole, 17 . . . P type diffusion layer, Is, 34 . . . Bonding butt aluminum, 18.35 . . . Vlili power supply line. l Kaya /I! 1 grass 2 concave grass 3 concave leather 41! I

Claims (1)

[Claims] A polysilicon resistance layer containing an impurity of one conductivity type is ohmically connected to an input bonding pad at one end, and a diffused low resistance layer of one conductivity type is connected to the other end of this polysilicon resistance layer. An input protection device for a semiconductor integrated circuit in which the other end of the resistance layer leads to an input gate to be protected, wherein the polysilicon resistance layer is formed on the top surface of the diffused resistance layer. Input protection device.