JPS6214103B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an integrated circuit device, particularly an integrated circuit device including field effect transistors such as vertical static induction transistors (SITs) and FETs.

Field-effect transistors, especially SITs, have excellent high-frequency characteristics due to their high input impedance, low output impedance, low capacitance, and high conversion conductance, but when incorporated into integrated circuits, they have the advantage of high interconnection logic and low power consumption. is common knowledge. In particular, a vertical structure has the advantage of high integration density and easy manufacturing. However, some manufacturing problems have arisen to further improve performance. Horizontal pnp bipolar
N-channel with transistor (BJT) as load
The problems of conventional manufacturing methods will be explained using a logic circuit (SITL) using SIT as a driving transistor as an example. In FIG. 1, a drain electrode 1 and a gate electrode 4, which are a typical example of the conventional type, are on substantially the same plane. A plan view of the so-called flat type SITL (Fig. 1b). Cross-sectional view along line A-A' (Fig. 1a), B
- shows a cross-sectional view (Fig. 1c) along line B'. 1st
For simplicity, the surface oxide film 7 and metal wiring (injector electrode 5, gate electrode 4, drain electrode 1) are not shown in the plan view of FIG. This planar SITL
can be realized by a simple manufacturing process ^of four photolithography steps and two diffusion steps, but ^the In order to reduce the capacitance, it is necessary to make the area of the p ⁺ gate region 14 as small as possible. To achieve this, it is necessary to make the diffusion hole for forming the p ⁺ gate region 14 narrower and the diffusion depth shallower, but in reality, normally-off characteristics are required, so the gate spacing WG must be made sufficiently large. Narrow and n ⁺ source area 1
In order to form a potential barrier for electrons injected from the p ⁺ gate region 1 in the n ^- channel region 13 as far as possible from the n ⁺ drain region 11,
4 must be deep to some extent. As a result, the area of the p ⁺ gate region 14 becomes large, and the n ⁺ drain region 11, which is another main electrode region, overlaps with the p ⁺ gate region 14.
This causes the gate-drain capacitance to become extremely large, and the diffusion hole for forming the n+ drain region 11 requires extremely fine processing, and the n ⁺
Diffusion and positional shifts are no longer allowed. Furthermore, the outer peripheral portion of the p ⁺ gate region 14 is completely unnecessary for operation, and as the junction capacitance increases,
Holes are injected into the n ^- region 13 from the p ⁺ gate region 14, increasing the carrier accumulation effect.
As a result, it becomes impossible to improve performance in terms of operating speed and power consumption. In order to reduce the gate-drain capacitance, step-type or step-cut type SITLs in which the gate is placed on the bottom or side of the step have been proposed, but these methods do not improve the processing accuracy of the bottom of the step and are difficult to wire. Therefore, sufficient performance is not necessarily achieved.

The above-mentioned problem is not limited to the SITL example shown in Fig. 1, but also applies to so-called upright type SIT logic circuits and analog circuits in which the n ⁺ source region 12 is on the main surface side, p-channel SIT, normally-on SIT, etc. SIT
The same can be said for .

The present invention provides an easy method of manufacturing the SIT structure of FIG. 2 that eliminates the above-mentioned drawbacks. Second
The SIT structure shown in the figure is shown in plan view in Fig. 2b, and in A-
As shown in FIGS. 2a and 2c, cross-sectional views taken along lines A' and B-B', the n ⁺ drain region 11 and the p ⁺ gate region 14, which are one of the high impurity density regions of the main electrode, are shown. are exposed on substantially the same plane, and the first recessed portion _V1 is provided between both regions. This first recess prevents the n ⁺ drain region 11 and the p ⁺ gate region 14 from overlapping with high impurity density, and as a result, the gate-drain capacitance and breakdown voltage are sufficiently improved. Further, a second recess V 2 is provided outside the p ⁺ gate region 14, and a second recess V ₂ is provided outside the p ⁺ gate region 14.
4 is useful for reducing the area and reducing the minority carrier accumulation effect. Preferably, the depth of the first recess V ₁ is n ⁺
The second recess V ₂ is formed deeper than the drain region 11 and shallower than the p ⁺ gate region 14 ^.
Formed deeper than 4. The SITL structure example in Figure 2 shows a circuit example similar to Figure 1, so there is a p ⁺ injector region 15, an n ^- region 13, and a p + injector region 15 next to the SIT ^.
A pnp BJT is formed by the gate region 14, but because of the third recess V3, which is as deep as the second recess _V2 , the base width is substantially expanded, and conversely, _the plane distance is decreased, improving the integration density. useful for. This pnpBJT
Although the structure is not limited to this example and there are various modifications, the manufacturing method of the present invention can be easily applied to them. The purpose of the manufacturing method of the present invention is ^to
In order to obtain the width and position of the n ⁺ drain region 11 in one mask step, an insulating film such as an oxide film containing nitride such as Si ₃ N ₄ film or SiOxNy is used, and selective Si etching is performed.
The objective is to facilitate a manufacturing process with high precision and miniaturization using selective oxidation. Another purpose is to further facilitate manufacturing by using a {100} plane as the Si substrate and simultaneously forming the first recess V ₁ and the second recess V ₂ by anisotropic etching ^. Si area
The above manufacturing method includes depositing a polycrystalline layer with high impurity density on a single crystal, taking advantage of the easiness of diffusion and oxidation of the polycrystalline layer, and using the above-mentioned insulating film to facilitate contact holes. The purpose of this invention is to provide an SIT integrated circuit element with further improved reliability and characteristics.

The manufacturing method of the present invention will be described in detail below with reference to the drawings. Figures 3 a to j are the same as those in Figure 2.
1 is an example of the manufacturing method of the present invention for realizing a SITL structure. The n ⁺ Si substrate becomes the n ⁺ region 12, the n ^- channel region 13 and the n ^- base region 13a.
The n ^- region is deposited by epitaxial growth. The impurity density and thickness of n -region ¹³ are the same as the expected SIT
Depending on the characteristics, 10 ¹² to 10 ¹⁵ cm ^-3 , 1 to 20μ
It is m. Typically 10 ¹³ to 10 ¹⁴ cm ^-3 , 3 to 7μ
It is about m. Figures 3a and 3b respectively show
Using the oxide film 7 as a mask on the surface of the n ^- region 13, p ⁺
A cross-sectional view and a plan view are shown in which gate region 14 and p ⁺ injector region 15 are shallowly diffused. These p ⁺
Since the diffusion depth is adjusted to the final value in a subsequent process, shallow diffusion or tipping very close to the surface is sufficient. Furthermore, since the planar shape of the diffusion region is adjusted to the final dimension in the subsequent Si etching step, it may be wider than the final dimension. Further, the thickness of the oxide film 7 formed on the diffusion region is the thickness that will serve as a mask for n ⁺ diffusion in the next step, and is preferably thin, for example, 1000 to 2000 Å. Figures 3c and 3d each contain n ⁺
A cross-sectional view and a plan view of n ⁺ diffusion to form the drain region 11 are shown. This n ⁺ selective diffusion is performed to be wider and shallower than the final dimension, similarly to the p ⁺ diffusion described above. It is sufficient that there is no oxide film on this n ⁺ diffusion region, or that it serves as a buffer film for the Si ₃ N ₄ film deposition in the next step, and a thickness of 0 to 1000 Å is sufficient.
The surface density of n ⁺ diffusion may be higher or lower than that of p ⁺ diffusion, but when it is low, selective diffusion may not be necessary and it may be diffused over the entire surface as will be described later. The mask openings for the above two p ⁺ and n ⁺ diffusion steps may be very rough in size. In FIGS. 3e and 3f, an insulating film such as a Si ₃ N ₄ film or a SiOxNy film is deposited to serve as a mask for selective oxidation, and the gate region 1 is
4. The insulating films 84 and 8 are formed on the drain region 11 and the injector region 15 in predetermined plane dimensions on each region.
1 and 85, and the oxide film 7 below, the remaining portions are removed. In this figure, n ^- of a horizontal pnpBJT
A Si ₃ N ₄ film 83 is also formed on the base region (n ^- region 13).
However, the final structure is the horizontal type shown in Figure 2.
It is not necessary to make it like pnpBJT. 3g and 3h show Si ₃ N ₄ films 81, 83, 84,
84 as a mask to selectively etch Si to form a shallow first recess V ₁ , a third recess V ₃ and a deep second recess V ₂ ,
Thereafter, a cross-sectional view and a plan view are shown in which the Si ₃ N ₄ films 81, 84, and 85 are removed, leaving only the portions that will become contact openings in the future. The first recess V ₁ is mainly
It is preferably provided between the p ⁺ gate region 14 and the n ⁺ drain region 11 and is deeper than the final n ⁺ diffusion depth and shallower than the p ⁺ diffusion depth. The second recessed portion _V2 is
It is desirable that it be provided outside the p ⁺ gate region 14 or in an unnecessary part and be deeper than the final p ⁺ diffusion depth.
p ⁺ injector region 15 and p ⁺ gate region 14
A third recess V ₃ is formed between each of the n ⁻ base regions 13 in this example, the same size as the first recess V ₁ and preferably at least shallower than the final p ⁺ diffusion depth. This Si selective etching can be performed using a normal Si etching solution (HF-HNO ₃ system), plasma etching such as CF ₄ , or isotropic etching such as ion etching, but a mask process and etching are required to form each recess. Several steps are required. If the crystal plane of the main Si surface is {100} plane and each region is parallel to the <110> direction, alkaline aqueous solutions such as APW and KOH, CCL ₄
By anisotropic etching using plasma such as trichlene or trichloride, recesses with different depths depending on the opening width can be formed at the same time. For example, if the opening width between the gate and drain is 0.5 to 4 μm, the first recess V ₁ is 0.35 μm.
The depth is ~2.8μ, and the second recess V ₂ is deeper than the first recess V ₁
The depth can be greater than or equal to the depth. This is because anisotropic etching is extremely slow for {111} planes. Also, since the etch rate may be slower than in the p ⁺ region, other etching methods may be used to first remove the high density areas. This anisotropic etching process substantially determines the final planar dimensions of each region, and the relative positional deviation of each region depends only on the dimensional accuracy of the mask. Thereafter, Si ₃ N ₄ films 81, 84, and 85 are left in portions of each of the n ⁺ drain region 11, p ⁺ gate region 14, and p ⁺ injector region 15 that require contact openings. Thereby, there is no displacement of the contact opening from each region. In Figure 3 i, the above Si ₃ N ₄
A cross-sectional view is shown in which selective diffusion is performed using films 81, 84, and 85 as masks, and each diffusion depth is set to a final value. Since the p ⁺ gate region 14 needs to be deeper than the n ⁺ drain region, the diffusion coefficient of the p type impurity is selected to be larger than that of the n type impurity. For example, B and As are used respectively. In Figure 3j,
The Si ₃ N ₄ films 81, 84, 85 are removed, and the underlying oxide film 7 is etched over the entire surface to expose the Si to obtain a contact opening, and metal (Al, Pt, Al
-Si, etc.) is deposited and wiring is performed.

As described above, according to the present invention, each selective diffusion step requires only rough openings, and impurities with a small diffusion coefficient are injected into the region where the final diffusion depth is desired to be shallow, and impurities with a large diffusion coefficient are added into the region where the final diffusion depth is desired to be deep. Just add impurities. In the n-channel SIT shown in Figure 3, B,
A p ⁺ gate region is formed of Al, Gs, etc., and an n ⁺ drain region is formed of As, Sb, etc. Conversely, in the p channel, In, Tl, B, etc. are added to the p ⁺ drain region.
P is added to the n ⁺ gate region. Of course, it is possible to control the final value by preliminarily selectively diffusing the region deeper into the region where it is desired to diffuse deeper. Also, n ^-
Unlike the example of FIG. 3, the base region 13a has a second
Although the third recess V ₃ as deep as recess V ₂ was not provided,
It is possible to provide the process without changing the process shown in FIG _. 3, and by providing a third recess V3 as shallow as the first recess _V1 , the capacitance and surface recombination can be reduced to some extent, and the second recess V3 can be provided. ₂ until it reaches the n ⁺ source region 12, the base region of the lateral BJT does not disappear, and the second recessed portion V ₂ eliminates the need for isolation and diffusion between elements.

FIG. 4 shows a sectional view illustrating another manufacturing example in which the present invention is applied to the same circuit example as in FIG. 3. In FIG. 4a, n ⁺ source region 12
An n ^- region 13 is epitaxially grown on top of the Si ₃ N ₄
An insulating film 18 such as a p ⁺ gate region 1 is deposited.
4 shows a cross section of p ⁺ injector region 15 subjected to shallow selective diffusion. A thin oxide film 7 is formed during p ⁺ diffusion. In FIG. 4b, the Si ₃ N ₄ film 18 is removed by etching the entire surface, and an n ⁺ diffusion layer is formed on the entire surface except the p ⁺ diffusion region. This n ⁺ diffusion layer includes what is to become an n ⁺ drain region 11 and an n ⁺ base region 16. It is desirable that the oxide film 7 on each diffusion layer be thin.
In FIG. 4c, after depositing the Si ₃ N ₄ film again, the planar shape and dimensions of each region are the same as Si ₃ N ₄ films 81, 83, 8.
4, 85, 86 A cross-sectional view in which the oxide film 7 is left, and in _FIG .
A cross-sectional view is shown in which after forming the second recess V ₂ and the third recess V ₃ , the Si ₃ N ₄ films 81, 84, 85 on the contact openings were left and the other surfaces were selectively oxidized. The rest is the same as in FIG. 3. In this example of Figure 4,
The mask process can be reduced once, and horizontal BJT
The n ⁺ base region 16 can be formed on the n ⁻ base region 13a, reducing surface recombination and improving the hole arrival rate α. Furthermore, in this example, the second recess V ₂ is provided in a V-shape, but it has the same effect as the second recess shown in FIG. 2.

For the initial shallow p and n diffusion layers, ordinary gas diffusion, solid source diffusion, source coating diffusion, doped oxide method, etc. can be used, but impurity-doped polycrystals can also be used. FIG. 5 shows the method of the invention using an impurity-doped so-called doped polycrystal. For convenience, only a cross-sectional view near the surface of the SIT is shown. In FIG. 5a, first a p-type doped polycrystalline layer 24 is deposited, and after removing the remaining portions except for the future gate region, an n-type doped polycrystalline layer 21 is deposited over the entire surface. At this time, the diffusion coefficient of each added impurity is larger in the p-type, and the density is lower in the n-type. In FIG. 5b, Si ₃ N ₄ is deposited on the polycrystalline layer 21.
A film is deposited, and the Si ₃ N ₄ films 81, 85 and polycrystalline layers 21, 24 are left so that each region has a desired planar shape, and the n ^- (single crystal) region 13 is exposed. Next, as shown in FIG. 5c, selective oxidation is performed once, and n ^-
Oxide film 7 is formed thicker than the surface of (single crystal) region 13. Low-temperature, high-pressure oxidation is desirable to avoid unnecessary impurity diffusion. As shown in FIG. 5d, the surface of the n ^- (single crystal) region 13 is exposed by etching the entire surface of the oxide film using the difference in oxide film thickness, and anisotropic etching is performed to form the first recess V ₁ and the second recess V 1 . Form a recess V ₂ . Next, as shown in FIG. 5e, the Si ₃ N ₄ films 81 and 84 on the contact openings are left and other regions are selectively oxidized and diffused. At this time p ⁺ gate region 1
Polycrystalline layers 21 and 24 under the contact opening portion of No. 4
All polycrystals become p-type due to rapid diffusion, and other polycrystals are easily oxidized, so a thick oxide film 7 is formed.
is formed and helps reduce wiring capacitance. The following steps can be carried out in the same manner as in the example shown in FIG. 3, but contact can be made through the polycrystalline layer and the metal spike phenomenon can be prevented. The impurity density of the polycrystalline layers 21 and 24 is only required to be high enough to make a resistive contact, and in this example, the impurity density of the p-type is 10 ¹⁹ to 10 ²⁰ cm ^-3 and the impurity density of the n-type is 5×10 ¹⁸ to 9×10 ¹⁹ A slightly lower value of cm ^-3 is sufficient. Diffusion using doped polycrystals can be applied in the same manner as the methods shown in FIGS. 3 and 4, but selective oxidation of the side surfaces is desirable to prevent side etching. Conversely, it goes without saying that p ⁺ selective diffusion and n ⁺ all-over diffusion (relatively low density) methods can be applied not only to doped polycrystals but also to other diffusion methods.

According to the manufacturing method of the present invention, the planar shape and dimensions of each region are almost determined only by a masking process that leaves a Si ₃ N ₄ film (or an insulating film that can withstand selective oxidation, such as a SiOxNy film); Because of this, highly accurate miniaturization is possible. Furthermore, since the contact holes can be formed in self-alignment, there is no positional shift, which is advantageous for miniaturization. Further, since the first recess, the second recess, the third recess, etc. can be effectively etched in one step, there are advantages in that the number of steps is reduced and the device characteristics are significantly improved due to the recess. Of course, the first recesses _V1 between the gate and drain do not all have to have the same depth, and the same applies to the other recesses. As shown in Figures 3 and 4, the dimensions of the present invention are effective not only for vertical SITs but also for lateral BJTs, and by simply changing the n ^- region to the p ^- region, it can be used for lateral p-channel SITs and FETs. is also effective. Furthermore, although an inverted type was described as an example of a vertical SIT, the same applies to an upright type in which an n+ source region is provided on the main surface, and the same can be said to vertical FETs and BJTs. Of course, it goes without saying that it can be applied to a complementary type in which the conductivity types of each region are reversed, and to both normally-on and normally-off types.

As described above, since integrated circuits, especially transistors such as SIT and FET, produced by the manufacturing method of the present invention have low capacitance and improved breakdown voltage, all high-speed, low-power operation logic circuits, analog ICs, memory transistors, etc. The present invention can be applied to ICs to greatly improve their characteristics, and is extremely effective industrially.

[Brief explanation of the drawing]

Figure 1b is a plan view of a planar SITL with a conventional structure.
Figures 1a and 1c are A- in Figure 1b, respectively.
FIG. 3 is a cross-sectional view taken along line A' and line B-B'. Second
Figure b is a plan view of a new planar SITL structure to which the manufacturing method of the present invention is applied, and Figures 2a and 2c are views taken along lines A-A' and B-B' in Figure 1b, respectively. FIG. FIGS. 3a to 3j are a cross-sectional view and a plan view, respectively, for explaining an example of the manufacturing method of the present invention. 4A to 4D are cross-sectional views for explaining examples of other manufacturing processes of the present invention, and FIGS. 5A to 5E are partially enlarged cross-sectional views for further explaining examples of other manufacturing processes of the present invention. It is a diagram. DESCRIPTION OF SYMBOLS 1... Drain electrode, 2... Source electrode, 4... Gate electrode, 5... Injector electrode, 11... n ⁺ drain region, 12... n ⁺ source region, 13... n ^- (single crystal) region (n ^- channel region), 13a...n ^- base region, 14...p ⁺ gate region, 15...p ⁺ injector region, 16...n ⁺ base region, 7... oxide film, 18, 81, 83, 84, 85, 86...
Si ₃ N ₄ film, 21...n ⁺ doped polycrystalline layer, 24...p ⁺
Doped polycrystalline layer, V ₁ ... first recess, V ₂ ... second recess, V ₃ ... third recess.

Claims (1)

[Claims] 1. A gate region in which a first impurity of an opposite conductivity type is selectively added shallowly to the surface of a low impurity density single crystal semiconductor region of one conductivity type on a high impurity density semiconductor first main electrode region; a first step of providing a second main electrode region larger than a predetermined area, in which a second impurity of one conductivity type is shallowly selectively added to at least a part of the surface of the low impurity density region other than the region; a second step of depositing an insulating film containing a nitride film on the electrode region; and selectively leaving the insulating film on the gate and second main electrode region in a predetermined planar shape and dimensions of the gate and second main electrode region. a third step, selectively etching the low impurity density region using the insulating film as a mask, forming a first recess deeper than the final diffusion depth of the second main electrode region and shallower than the final diffusion depth of the gate region; a fourth step of forming a second recess deeper than the final diffusion depth; a fifth step of selectively leaving the insulating film on the gate and second main electrode regions smaller than the predetermined planar shape and dimensions; Using the insulating film as a mask, a selective oxide film is formed on the surface of the gate and second main electrode regions and on the sides and bottoms of the first and second recesses, while forming the gate and second main electrode regions to the final diffusion depth of the step. a sixth step; a seventh step of removing the insulating film to form a contact opening to the gate and second main electrode regions; and depositing and selectively etching a conductive film to form the gate and second main electrode regions. An eighth step of forming wiring to the integrated circuit device. 2. The integrated circuit device according to claim 1, wherein the crystal plane of the low impurity density region is a {100} plane, and the first and second recesses are formed simultaneously by anisotropic etching. manufacturing method. 3. The method of manufacturing an integrated circuit device according to claim 1 or 2, wherein the diffusion coefficient of the first impurity is larger than the diffusion coefficient of the second impurity. 4. The first step includes forming a gate region in which the first impurity is added to the entire surface of the low impurity density region at a density lower than the second impurity doping density of the second main electrode region, and selectively forming a second main electrode region. 4. The method of manufacturing an integrated circuit device according to claim 3, wherein substantially the gate region and the second main electrode region are selectively formed. 5. In the first step, at least one of the gate and second main electrode regions is formed by diffusion from the polycrystalline film doped with the first or second impurity, and in the third step, the insulating film is formed. Following the selective etching, the polycrystalline film is also selectively etched into the same shape, and further a selective oxide film is provided on at least the side surfaces of the polycrystalline film, and the surface of the low impurity density region to be selectively etched is exposed in a fourth step. 3. The method of manufacturing an integrated circuit device according to claim 1, wherein a fourth step is performed after the step.