JPS62132348A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62132348A JPS62132348A JP27304085A JP27304085A JPS62132348A JP S62132348 A JPS62132348 A JP S62132348A JP 27304085 A JP27304085 A JP 27304085A JP 27304085 A JP27304085 A JP 27304085A JP S62132348 A JPS62132348 A JP S62132348A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- metal wiring
- steps
- semiconductor device
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000002184 metal Substances 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000008018 melting Effects 0.000 claims abstract description 8
- 238000002844 melting Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 description 7
- 238000002474 experimental method Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法における金属配線層の
段差の緩和やステップカバレッジ改善等の技術に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to techniques for alleviating steps in metal wiring layers and improving step coverage in a method of manufacturing a semiconductor device.
本発明は、段差部を有する半導体基板に金属配線層を施
すものにおいて、金属配線層を形成し該金属配線層を溶
融させることにより、急峻な段差を緩和し被覆形状を改
善したものである。The present invention applies a metal wiring layer to a semiconductor substrate having a stepped portion, and by forming the metal wiring layer and melting the metal wiring layer, the steep step difference is alleviated and the covering shape is improved.
半導体装置の高集積化、微細化に伴い、その製造技術に
おいては、急峻な段差を有する狭い凹部に被覆性良く膜
を形成する技術の必要性が高まっている。2. Description of the Related Art As semiconductor devices become more highly integrated and miniaturized, there is an increasing need in their manufacturing technology for forming a film with good coverage in narrow recesses with steep steps.
即ち、半導体装置の微細化傾向に従って、所謂多層配線
構造の要求が強くなり、多層配線構造の半導体装置を製
造する際の課題の1つが段差の緩和やステップカバレッ
ジの改善である。That is, with the trend towards miniaturization of semiconductor devices, there is a growing demand for so-called multilayer wiring structures, and one of the challenges when manufacturing semiconductor devices with multilayer wiring structures is to alleviate steps and improve step coverage.
ところで、一般に金属膜を形成する方法としては、蒸着
法、スパッタリング法、CVD法等が知られている。Incidentally, vapor deposition methods, sputtering methods, CVD methods, and the like are generally known as methods for forming metal films.
例えば、蒸着法、スパッタリング法によって段差を有す
る半導体基板等に金属膜を形成したときは、第3図に示
すように、部分的に薄(形成されて均等には被着形成さ
れない。即ち、凹部の底部33や側壁部34では、金属
膜32の膜厚が、凸部の上面に形成される金属膜32の
膜厚とは異なって薄いものになり、例えば、凸部の上面
に形成される金属膜32の膜厚と、凹部の底部33や側
壁部34の金属膜32の膜厚とは、10:3程度の比に
なることがある。For example, when a metal film is formed on a semiconductor substrate having a step by vapor deposition or sputtering, as shown in FIG. The thickness of the metal film 32 is different from the thickness of the metal film 32 formed on the top surface of the convex part and is thinner on the bottom part 33 and side wall part 34 of the convex part. The ratio of the thickness of the metal film 32 and the thickness of the metal film 32 on the bottom 33 and side wall 34 of the recess may be about 10:3.
そこで、段差部を有する半導体基板に金属配線層を施す
技術として、半導体基板にバイアスを加えながらスパッ
タリングを行う所謂バイアススパッタ法や気相成長を用
いた所謂選択CVD法が知られている。Therefore, as techniques for forming a metal wiring layer on a semiconductor substrate having a stepped portion, there are known a so-called bias sputtering method in which sputtering is performed while applying a bias to a semiconductor substrate, and a so-called selective CVD method using vapor phase growth.
然しなから、例えばバイアススパッタ法は、下地形状へ
の依存性が大きく、基板の段差が急峻なときには、平坦
化が容易でない。また、削りながら被膜を形成するため
半導体基板へのダメージも大きい。更に、半導体装置の
微細化に従って、コンタクト孔等の凹部の縦横比いわゆ
るアスペクト比が小さくされた場合には、バイアススパ
ッタを施すことにより、当該四部に形成された金属膜に
空洞部等が形成される虞れもある。However, for example, the bias sputtering method is highly dependent on the underlying shape, and flattening is not easy when the substrate has steep steps. Furthermore, since the film is formed while being scraped, damage to the semiconductor substrate is also large. Furthermore, when the so-called aspect ratio of concave portions such as contact holes is reduced due to miniaturization of semiconductor devices, by applying bias sputtering, cavities etc. are formed in the metal film formed in the four portions. There is also a possibility that
また、上記選択CVD法は、被膜性に関しては優れた方
法であるが、その一方で、装置の構成が複雑になり、ま
た、ガス、温度等の種々の条件をコントロールすること
が難しい。更に、厚く金属膜を形成することも容易でな
い。Furthermore, although the selective CVD method is an excellent method in terms of film properties, on the other hand, the configuration of the apparatus is complicated and it is difficult to control various conditions such as gas and temperature. Furthermore, it is not easy to form a thick metal film.
そこで、本発明は上述の問題点に瀝み、簡便な方法によ
り、急峻な段差に対して被膜形状を良好なものとする半
導体装置の製造方法の提供を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a method for manufacturing a semiconductor device that provides a good coating shape for steep steps using a simple method.
本発明は、半導体基板上に形成された段差部上に金属配
線層を形成する工程と、上記金属配線層を熱処理により
溶融させる工程とを有することを特徴とする半導体装置
の製造方法により上述の問題点を解決する。The present invention provides a method for manufacturing a semiconductor device characterized by comprising the steps of forming a metal wiring layer on a stepped portion formed on a semiconductor substrate, and melting the metal wiring layer by heat treatment. Solve problems.
ここで、金属配線・層の材料は、例えばSn、Zn、I
n、Pb、Mg、AA等の金属材料や合金等であり、こ
れに限定されるものではないが、熱処理で溶融し得る比
較的低融点の金属材料が選択される。Here, the material of the metal wiring/layer is, for example, Sn, Zn, I
Metal materials and alloys such as n, Pb, Mg, AA, etc. are selected, but are not limited thereto, and metal materials with a relatively low melting point that can be melted by heat treatment are selected.
上記金属配線層の形成は、例えば蒸着法やスパッタリン
グ法によって当該金属配線層を形成することが可能であ
る。The metal wiring layer can be formed by, for example, a vapor deposition method or a sputtering method.
また、熱処理は、基板を水平に保持しながら行われ、例
えば縦型の電気炉や赤外線ランプアニール装置を用いて
行うことができる。Further, the heat treatment is performed while holding the substrate horizontally, and can be performed using, for example, a vertical electric furnace or an infrared lamp annealing device.
金属配線層を形成した後、熱処理を施して該金属配線層
を溶融させる。このとき、熱によって溶融した金属配線
層は、段差部の凹部を埋め込み、当該金属配線層によっ
て全面が平坦化されることになる。After forming the metal wiring layer, heat treatment is performed to melt the metal wiring layer. At this time, the metal wiring layer melted by the heat fills the recessed portion of the stepped portion, and the entire surface is flattened by the metal wiring layer.
本発明の好適な実施例を図面を参照しながら説明する。 Preferred embodiments of the present invention will be described with reference to the drawings.
本実施例は、本件発明者らが行った実験例に基づくもの
である。尚、本発明は本実施例に限定されるものでない
ことは言うまでもない。This example is based on an experimental example conducted by the inventors of the present invention. It goes without saying that the present invention is not limited to this embodiment.
先ず、実験例における工程に従って本実施例を具体的に
説明する。First, this example will be specifically explained according to the steps in the experimental example.
(a)実験では、第1図(a)に示すような酸化シリコ
ンの段差部2や段差部3を有する基板1を用いる。段差
部2の高さhは、例えば6000人である。段差部2と
段差部3は、それぞれ断面上の幅が異なっている。(a) In the experiment, a substrate 1 having silicon oxide stepped portions 2 and 3 as shown in FIG. 1(a) is used. The height h of the stepped portion 2 is, for example, 6000 people. The stepped portion 2 and the stepped portion 3 have different widths in cross section.
(b)続いて、第1図(b)に示すように、膜厚tの金
属配線層4を形成する。膜厚tは、例えば8000人で
あり、金属配線層4は、本実験ではSn(スズ)を用い
ている。尚、金属配線層4は、これに限定されず、Zn
、In、Pb、Mg、A1等の金属材料や合金等でも良
く、熱処理で溶融し得る比較的低融点の金属材料が選択
される。(b) Subsequently, as shown in FIG. 1(b), a metal wiring layer 4 having a thickness of t is formed. The film thickness t is, for example, 8000, and the metal wiring layer 4 is made of Sn (tin) in this experiment. Note that the metal wiring layer 4 is not limited to this, and may be made of Zn
, In, Pb, Mg, A1, or other metal materials or alloys, and a metal material with a relatively low melting point that can be melted by heat treatment is selected.
金属配線層4の形成は、本実験では、電子ビーム加熱蒸
着法によって行っている。In this experiment, the metal wiring layer 4 was formed by electron beam heating evaporation.
(c)次に、赤外線ランプを用いた熱処理によって当該
金属配線層4を加熱溶融する。加熱溶融によって金属配
線層4は平坦化され、上記段差部2.3の急峻な段差は
緩和されることになる。また、後述するように金属配線
層4は溶融されるため、下地への依存性が小さく段差緩
和を図ることができ、更に、上記金属配線層4の膜厚が
厚い場合でも容易に平坦化を図ることが可能である。(c) Next, the metal wiring layer 4 is heated and melted by heat treatment using an infrared lamp. The metal wiring layer 4 is flattened by heating and melting, and the steep step portion 2.3 is alleviated. In addition, since the metal wiring layer 4 is melted as will be described later, it is less dependent on the underlying layer and can reduce the level difference.Furthermore, even if the metal wiring layer 4 is thick, it can be easily flattened. It is possible to achieve this goal.
ここで、本実験では、熱処理の最高到達温度を200℃
、250℃、300℃、350℃、400℃の各温度に
設定して実験を行っている。Here, in this experiment, the maximum temperature reached by heat treatment was 200°C.
, 250°C, 300°C, 350°C, and 400°C.
これら各最高到達温度と上記Snを材料とする金属配線
層4との関係を第1表に示す。Table 1 shows the relationship between each of these maximum temperatures and the metal wiring layer 4 made of Sn.
(以下、余白)
第1表
第1表に示すように、例えば金属配線層4として、Sn
を選択した場合には、熱処理の最高到達温度が300℃
〜400℃でステップカバレンジの改善がなされている
。(Hereinafter, blank space) Table 1 As shown in Table 1, for example, as the metal wiring layer 4, Sn
If you select , the maximum temperature of heat treatment will be 300℃.
The step coverage range is improved at ~400°C.
また、表面膜差計による実測形状を第2図(a)〜第2
図(C)に示す。In addition, the actual shape measured by the surface film difference meter is shown in Figures 2(a) to 2.
Shown in Figure (C).
第2図(a)〜第2図(c)は、表面膜差計を用いた、
縦軸を基板主面上の一方向の距離(μm)とし、横軸を
高さくk人)とする基板の表面のデータである。Figures 2(a) to 2(c) show the results obtained using a surface film difference meter.
This is data on the surface of the substrate, with the vertical axis representing the distance (μm) in one direction on the main surface of the substrate, and the horizontal axis representing the height (k people).
第2図(a)は、基板自体の形状を示し、第2図(a)
中、点Aは段差部の底部を示し、また、点Bは段差部の
上部を示している。これは第1図(a)に対応する。Fig. 2(a) shows the shape of the substrate itself; Fig. 2(a)
In the middle, point A indicates the bottom of the step, and point B indicates the top of the step. This corresponds to FIG. 1(a).
第2図(b)は、第2図(a)に示す基板に対して、S
nを蒸着した後の表面の段差形状を実測したものである
。このときには、多少段差が有り、Sn7着後でも、段
差部の底部は点A1であり、また、段差部の上部は点B
1になっている。FIG. 2(b) shows that the S
This is an actual measurement of the step shape on the surface after n was vapor-deposited. At this time, there is a slight difference in level, and even after reaching Sn7, the bottom of the level difference is point A1, and the top of the level difference is point B.
It has become 1.
そして、第2図(C)は上記赤外線ランプアニール装置
を用いて、300℃で熱処理したものであり、この熱処
理による金属配線層の溶融から、急峻な段差が緩和され
、下地依存性もなく約1000人以内の平坦化が行われ
ていることが示されている。FIG. 2(C) shows the result of heat treatment at 300°C using the above-mentioned infrared lamp annealing equipment.As the metal wiring layer melts due to this heat treatment, the steep level difference is alleviated, and there is no dependence on the underlying layer, and the result is approximately It is shown that flattening within 1000 people has been achieved.
上述のような実験結果より、本実施例において良好な段
差緩和やステップカバレンジの改善が行われていること
が示されている。また、本実施例は、金属配線層の形成
を行った後、所定の熱処理を行って当該金属配線層を溶
融させて平坦化を図るものである。従って、段差の緩和
は、従来の方法に比較して容易であって、しかも確実な
平坦化を実現するものである。また、段差を緩和させる
ことによるコンタクト孔での良好な接続を実現できる。The above-mentioned experimental results indicate that the present example achieves good step reduction and step coverage improvement. Further, in this embodiment, after forming a metal wiring layer, a predetermined heat treatment is performed to melt the metal wiring layer and planarize it. Therefore, it is easier to reduce the level difference than in the conventional method, and moreover, it is possible to achieve reliable flattening. Furthermore, by reducing the level difference, it is possible to realize a good connection in the contact hole.
本発明の半導体装置の製造方法を用いることにより、急
峻な段差を下地依存性もなく緩和させ平坦化を図ること
ができる。また、平坦化による配線層のコンタクト孔で
の良好な接続も可能である。By using the method of manufacturing a semiconductor device of the present invention, it is possible to reduce a steep step difference without depending on the underlying layer and achieve flattening. In addition, good connections can be made in the contact holes of the wiring layer by planarization.
更に、その製造プロセスは簡便なものであり、デバイス
の信頼性を高めることができる。Furthermore, the manufacturing process is simple and the reliability of the device can be improved.
第1図(a)〜第1図(c)は本発明の半導体装置の製
造方法を工程順に説明するための実験例を示すそれぞれ
断面図であり、第2図(a)〜第2図(C)は本発明の
半導体装置の製造方法に基づく実験の表面膜差計のデー
タを示す図であり、第3図は従来の半導体装置の製造方
法を説明するための断面図である。
1 −−−−−−−−−−・−一−・・、基牟反2 ・
−−−−−−−−一−−−−−−−−−一段差部3 −
−−一−・・−−−−−・・−・−・一段差部4−・−
・−・−・−−−−−−・−金属配線開時 許 出 願
人 ソニー株式会社代理人 弁理士
小泡 見間 田村榮−
第1図(0)
&属eJt!N!形へ
第1 図(b)
干出1イヒー
第1図(C)
蓋板の半抜
第2図(0)
Snnフロ漬日)−
第2図(b)
第2図(C)
喪東ゼ′]
第3図FIGS. 1(a) to 1(c) are cross-sectional views showing experimental examples for explaining the method for manufacturing a semiconductor device of the present invention in the order of steps, and FIGS. C) is a diagram showing data from an experimental surface film difference meter based on the semiconductor device manufacturing method of the present invention, and FIG. 3 is a cross-sectional view for explaining the conventional semiconductor device manufacturing method. 1 ---------------・-1-・・, Motomutan 2 ・
−−−−−−−−1−−−−−−−−−One step part 3 −
−−1−・・−−−−−・・−・−・One step part 4−・−
・−・−・−−−−−−・−When metal wiring is opened Applicant Sony Corporation representative Patent attorney
Kobua Mima Tamura Sakae - Figure 1 (0) & Genus eJt! N! Figure 1 (b) Hideout 1 Figure 1 (C) Lid plate half-extracted Figure 2 (0) Snn Flo soaking day) - Figure 2 (b) Figure 2 (C) Motoze '] Figure 3
Claims (1)
する工程と、 上記金属配線層を熱処理により溶融させる工程とを有す
ることを特徴とする半導体装置の製造方法。[Scope of Claim] A method for manufacturing a semiconductor device, comprising the steps of: forming a metal wiring layer on a step portion formed on a semiconductor substrate; and melting the metal wiring layer by heat treatment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27304085A JPS62132348A (en) | 1985-12-04 | 1985-12-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27304085A JPS62132348A (en) | 1985-12-04 | 1985-12-04 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62132348A true JPS62132348A (en) | 1987-06-15 |
Family
ID=17522327
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27304085A Pending JPS62132348A (en) | 1985-12-04 | 1985-12-04 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62132348A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2253939A (en) * | 1991-03-20 | 1992-09-23 | Samsung Electronics Co Ltd | Forming a metal layer on a semiconductor device |
US5534463A (en) * | 1992-01-23 | 1996-07-09 | Samsung Electronics Co., Ltd. | Method for forming a wiring layer |
US5569961A (en) * | 1992-12-30 | 1996-10-29 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-layer metallization structure |
-
1985
- 1985-12-04 JP JP27304085A patent/JPS62132348A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5869902A (en) * | 1990-09-19 | 1999-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device and manufacturing method thereof |
GB2253939A (en) * | 1991-03-20 | 1992-09-23 | Samsung Electronics Co Ltd | Forming a metal layer on a semiconductor device |
DE4200809A1 (en) * | 1991-03-20 | 1992-09-24 | Samsung Electronics Co Ltd | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT |
GB2253939B (en) * | 1991-03-20 | 1995-04-12 | Samsung Electronics Co Ltd | Method for manufacturing a semiconductor device |
US5534463A (en) * | 1992-01-23 | 1996-07-09 | Samsung Electronics Co., Ltd. | Method for forming a wiring layer |
US5589713A (en) * | 1992-01-23 | 1996-12-31 | Samsung Electronics Co., Ltd. | Semiconductor device having an improved wiring layer |
US5569961A (en) * | 1992-12-30 | 1996-10-29 | Samsung Electronics Co., Ltd. | Semiconductor device having a multi-layer metallization structure |
US5851917A (en) * | 1992-12-30 | 1998-12-22 | Samsung Electronics Co., Ltd. | Method for manufacturing a multi-layer wiring structure of a semiconductor device |
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