JPS62131567A - solid-state imaging device - Google Patents
solid-state imaging deviceInfo
- Publication number
- JPS62131567A JPS62131567A JP60271859A JP27185985A JPS62131567A JP S62131567 A JPS62131567 A JP S62131567A JP 60271859 A JP60271859 A JP 60271859A JP 27185985 A JP27185985 A JP 27185985A JP S62131567 A JPS62131567 A JP S62131567A
- Authority
- JP
- Japan
- Prior art keywords
- type
- conductivity type
- imaging device
- solid
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003384 imaging method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims description 31
- 239000012535 impurity Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 230000002542 deteriorative effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/15—Charge-coupled device [CCD] image sensors
- H10F39/158—Charge-coupled device [CCD] image sensors having arrangements for blooming suppression
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Light Receiving Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、固体撮像装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a solid-state imaging device.
従来の技術
従来、Ｐウェル型固体撮像装置は、第２図に示す構造で
あった。第２図すは、受光部を模式的に示したものであ
り、第２図＆は、第２図すのＢ −Ｂ′方向の不純物分
布を示しだものである。第２図すにおいて、５はＮ型シ
リコン基板で、２３はＰ型層、２４はＮ型領域である。2. Description of the Related Art Conventionally, a P-well type solid-state imaging device has a structure shown in FIG. FIG. 2 schematically shows the light receiving section, and FIG. 2 & shows the impurity distribution in the B-B' direction of FIG. In FIG. 2, 5 is an N-type silicon substrate, 23 is a P-type layer, and 24 is an N-type region.
実効的な受光傾城は、Ｐ型層２３とＮ型領域２４で形成
される。実動作として、Ｐ型層２３はＯｖに接地され、
Ｎ型シリコン基板５とＮ型領域２４は、Ｐ型層２３に対
して逆バイアスされている。An effective light-receiving tilted wall is formed by the P-type layer 23 and the N-type region 24. In actual operation, the P-type layer 23 is grounded to Ov,
N-type silicon substrate 5 and N-type region 24 are reverse biased with respect to P-type layer 23.
そして、第２図の従来の固体撮像装置の構成で必要なプ
ルーミング抑制を行なうためには、Ｐ型層２３を完全に
空乏化しなければならない。そのためには、特にＮ型シ
リコン基板５に加える電圧（以下、基板電圧と呼ぶ）は
重要である。少なくとも基板電圧は、通常の駆動電圧（
２０Ｖ以下）にする必要がある。In order to perform the necessary pluming suppression in the configuration of the conventional solid-state imaging device shown in FIG. 2, the P-type layer 23 must be completely depleted. For this purpose, the voltage applied to the N-type silicon substrate 5 (hereinafter referred to as substrate voltage) is especially important. At least the substrate voltage is the normal driving voltage (
20V or less).
前記、基板電圧を決める要因は、Ｐ型層２３の不純物分
布（濃度、深さ）およびＮ型シリコン基板６の濃度であ
る。そして、それらの関係は、プロセスの安定性から、
Ｎ型シリコン基板５は低濃度のものが用いられ、撮像装
置の分光特性の要求から、Ｐ型層２３は、拡散長は深く
、低濃度のものが必要であった。The factors that determine the substrate voltage are the impurity distribution (concentration, depth) of the P-type layer 23 and the concentration of the N-type silicon substrate 6. And the relationship between them is determined by the stability of the process.
The N-type silicon substrate 5 used had a low concentration, and the P-type layer 23 had to have a deep diffusion length and a low concentration due to the requirements for the spectral characteristics of the imaging device.
発明が解決しようとする問題点
このような従来の構造では、撮像装置の光学的特性とプ
ロセス安定性を同時に満たそうとすると基板電圧は必然
的に高くなる。基板電圧を低くするには、基板の不純物
濃度を上げるかあるいはＰ型層の不純物濃度を下げるか
拡散長を短くする必要がある。しかし、前者は、プロセ
ス変動に敏感になり、後者は、光学的特性が劣化すると
いう問題があった。Problems to be Solved by the Invention In such a conventional structure, if the optical characteristics and process stability of the imaging device are to be satisfied at the same time, the substrate voltage inevitably increases. In order to lower the substrate voltage, it is necessary to increase the impurity concentration of the substrate, lower the impurity concentration of the P-type layer, or shorten the diffusion length. However, the former has the problem of being sensitive to process variations, and the latter has the problem of deteriorating optical characteristics.
本発明はこのような問題点を解決するもので、光学的特
性を劣化させることなく、基板電圧の低電圧化が図れし
かもプロセス安定性をも同時に実現することを目的とす
るものである。The present invention is intended to solve these problems, and aims to reduce the substrate voltage without deteriorating the optical characteristics, and also realize process stability at the same time.
問題点を解決するだめの手段
この問題点を解決するために本発明は、高濃度不純物半
導体基板上に低濃度不純物エピタキシャル層が形成され
たものを出発基板として、ウェル型固体撮像装置が形成
されたものである。Means for Solving the Problem In order to solve this problem, the present invention provides a well-type solid-state imaging device in which a well-type solid-state imaging device is formed using a starting substrate in which a low-concentration impurity epitaxial layer is formed on a high-concentration impurity semiconductor substrate. It is something that
作用
この構造により、Ｐ型層を完全に空乏化するに必要なＮ
型基板側の空乏層幅の広がりを高濃度不純物基板によっ
て制限することにより、空乏化に必要な基板印加電圧の
低電圧化を図ることとなる。Effect: This structure allows the N required to completely deplete the P-type layer.
By restricting the spread of the depletion layer width on the type substrate side by the highly doped impurity substrate, it is possible to reduce the voltage applied to the substrate necessary for depletion.
実施例
第１図ａ、ｂはそれぞれ本発明の一実施例によるＰウェ
ル型固体撮像装置受光部の深さ方向不純物濃度分布と模
式的断面図すである。Embodiment FIGS. 1a and 1b are respectively a depth direction impurity concentration distribution and a schematic cross-sectional view of a light receiving part of a P-well type solid-state imaging device according to an embodiment of the present invention.
第１図すにおいて、１は高濃度Ｎ型シリコン基板、２は
低濃度Ｎ型エピタキシャル層、３は低濃度Ｐ型層、４は
Ｎ型領域である。第１図ａは、第１図すの人−Ａ′の断
面における深さ方向の不純物濃度分布を示したものであ
る。表面側から、Ｎ／Ｐ／Ｈ／Ｎ＋構造となっている。In FIG. 1, 1 is a highly doped N-type silicon substrate, 2 is a lightly doped N-type epitaxial layer, 3 is a lightly doped P-type layer, and 4 is an N-type region. FIG. 1a shows the impurity concentration distribution in the depth direction in the cross section taken along line A' in FIG. From the surface side, it has an N/P/H/N+ structure.
ブルーミング抑制の基本動作は、従来型と同一で、低濃
度Ｐ型層３をＯｖに接地し、高濃度Ｎ型シリコン基板１
に正電圧を印加して、低濃度Ｐ型層３を完全空乏化する
ことにより行なわれる。ブルーミング抑制時には、Ｐ型
層３を完全空乏化するに必要なＮ型基板の不純物量が満
足されるまでＮ型基板側の空乏層は広がる。本発明によ
るＮ／Ｐ／Ｎ／Ｎ＋構造によれば、Ｎ型基板側の空乏層
幅は、Ｎ＋基板で制限され、第１図ａに示すＸ、までと
なる。一方、従来型（Ｎ／Ｐ／Ｎ−構造）では、第１図
＆に参考のため示したＸｓ ’′ｌ！、で広がる。その
結果、基板電圧は、従来型に比べ低電圧にすることがで
きる。The basic operation of blooming suppression is the same as that of the conventional type, in which the low concentration P-type layer 3 is grounded to Ov, and the high concentration N-type silicon substrate 1 is grounded.
This is done by applying a positive voltage to completely deplete the lightly doped P-type layer 3. When suppressing blooming, the depletion layer on the N-type substrate side expands until the amount of impurity in the N-type substrate necessary to completely deplete the P-type layer 3 is satisfied. According to the N/P/N/N+ structure according to the present invention, the width of the depletion layer on the N type substrate side is limited by the N+ substrate, and is up to X shown in FIG. 1a. On the other hand, in the conventional type (N/P/N-structure), Xs''l! , spreads. As a result, the substrate voltage can be lower than that of the conventional type.
また、本発明は第１図乙において、Ｐ型層やＮ−エビタ
キシャル層の不純物分布が変動しても、Ｎ型基板側の空
乏層端Ｘムの変動は、従来型のｘＢに比べて小さいだめ
、プロセス変動に対しても強い構造となっている。In addition, in the present invention, as shown in FIG. Due to its small size, it has a structure that is resistant to process fluctuations.
なお、実施例では、Ｐウェル型固体撮像装置について述
べたが、Ｐ型基板を用いたＮウェル型固体撮像装置にお
いても同様な効果が得られることは明白である。In the embodiment, a P-well solid-state imaging device has been described, but it is clear that similar effects can be obtained in an N-well solid-state imaging device using a P-type substrate.
発明の効果
以上のように本発明によれば、固体撮像装置の光学特性
の劣化およびプロセスの安定化を損うことなく、基板電
圧の低電圧化が図れ、かつ、プロセス変動に対しても強
いなどきわめて有効な効果が得られる。Effects of the Invention As described above, according to the present invention, it is possible to reduce the substrate voltage without deteriorating the optical characteristics of the solid-state imaging device or impairing the stability of the process, and it is resistant to process fluctuations. Very effective effects can be obtained.
第１図ａ、ｂは、本発明の一実施例によるＰつ＄
エル型固体撮像装置受光部の不純物量Ｗよび断面模式図
、第２図Δ、ｂは従来のＰウェル型固体硼。
撮像装置受九部の不純物分布および断面模式図である。
１・・・・・・高濃度Ｎ型シリコン基板、２・・・・・
・低濃度ＭＷエピタキシャル層、３．２３・・・・・・
低濃度Ｐ型層、４，２４・・・・・・Ｎ型領域、５・・
・・・・低濃度Ｎ型シリコン基板。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第
１ 図
１−・−１へ１便ＮＯソリ］ン獄
２−−−／ａ４，７Ｎｐｌｘｅ”ｙ＞＋Ｌ１３・−・
Ｐ４嘔
４−、ｙで１更へ
第２図
）にこ万１司
２４−・−ｆｔ傾に1A and 1B are schematic cross-sectional views of the impurity amount W and the light receiving section of a P-well type solid-state imaging device according to an embodiment of the present invention, and FIGS. 2A and 2B are a conventional P-well type solid-state image sensor. FIG. 4 is a schematic cross-sectional view of an impurity distribution and a cross-sectional view of the receiving portion of the imaging device. 1...High concentration N-type silicon substrate, 2...
・Low concentration MW epitaxial layer, 3.23...
Low concentration P-type layer, 4, 24...N-type region, 5...
...Low concentration N-type silicon substrate. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 1-・-1 to 1 flight NO SOLE] prison 2---/a4,7Nplxe"y>+L13・-・
P4 vo 4-, y to 1 further Fig. 2) Nicoman 1 Tsuji 24-・-ft tilt
Claims (1)
前記一導電型と同一導電型を有するとともに前記半導体
基板よりも低不純物濃度のエピタキシャル層、前記一導
電型と反対導電型の半導体層が順次形成され、前記反対
導電型の半導体層の表面に前記一導電型と同一導電型の
領域が形成されていることを特徴とする固体撮像装置。On the surface of a highly impurity-concentrated semiconductor substrate having one conductivity type,
An epitaxial layer having the same conductivity type as the one conductivity type and having an impurity concentration lower than that of the semiconductor substrate, and a semiconductor layer having an opposite conductivity type to the one conductivity type are sequentially formed, and the epitaxial layer has the same conductivity type as the one conductivity type and has an impurity concentration lower than that of the semiconductor substrate, and a semiconductor layer of the opposite conductivity type is formed on the surface of the semiconductor layer of the opposite conductivity type. A solid-state imaging device characterized in that regions of one conductivity type and the same conductivity type are formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60271859A JPH073867B2 (en) | 1985-12-03 | 1985-12-03 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60271859A JPH073867B2 (en) | 1985-12-03 | 1985-12-03 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62131567A true JPS62131567A (en) | 1987-06-13 |
| JPH073867B2 JPH073867B2 (en) | 1995-01-18 |
Family
ID=17505880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60271859A Expired - Lifetime JPH073867B2 (en) | 1985-12-03 | 1985-12-03 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH073867B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5522871A (en) * | 1978-08-08 | 1980-02-18 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor light detector |
| JPS58125976A (en) * | 1982-01-22 | 1983-07-27 | Nec Corp | solid-state image sensor |
-
1985
- 1985-12-03 JP JP60271859A patent/JPH073867B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5522871A (en) * | 1978-08-08 | 1980-02-18 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor light detector |
| JPS58125976A (en) * | 1982-01-22 | 1983-07-27 | Nec Corp | solid-state image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH073867B2 (en) | 1995-01-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |