JPS62130041A - Digital demodulation circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of a demodulation circuit by detecting the unlocking of a PLL circuit, using a detection output so as to apply a kick pulse to a VCO circuit, and a restoring the PLL circuit forcibly within the lock-in range. CONSTITUTION:If an error takes place in a PCM decoder 4 and an output of a switching circuit 13 goes to logical '1', a mute circuit 3 mutes the voice output of the decoder 4 and a multivibrator 21 starts the oscillation. When the error generation of the decoder 4 is restored just after the oscillation, the oscillation is finished by the oscillation of one pulse only. If the error is consecutive further, the oscillation of the multivibrator 21 is continued. A waveform shaping circuit 21 supplies a signal C being the waveform-shaped output signal B of the multivibrator 21 to use as a voltage control signal of a VCO circuit 5. As a result, an oscillation frequency (f) of the circuit 5 is returned from a frequency f' at the outside of the lock-in range into the lock-in range and reaches finally to the setting frequency f0.

Description

DETAILED DESCRIPTION OF THE INVENTION (+) Industrial Application Field The present invention relates to a digital demodulation circuit that demodulates a transmitted digital signal, and particularly relates to a four-phase differential PSK (Pbas
c5hif1. Keying
) Regarding a digital demodulation circuit that is optimal for signal demodulation.

(2) Conventional technology 4-phase differential PSK signal, that is, 2-bit digital data is transmitted to subcarriers of 06.90°, 180°, and 270°0]
A signal that transmits data in response to four phase changes is used for transmitting PCM audio in satellite broadcasting. As a demodulation circuit for this 4-phase differential PSK signal,
The circuits shown in FIGS. 4 and 5 are known. The circuit shown in Figure 4 is a demodulation circuit called an inverse modulation method, and the circuit shown in Figure 5 is a demodulation circuit called a Costas loop after its developer. . These circuits all use a low pass filter and a 76
A one-loop feedback circuit using a PLL circuit including a zero circuit is used to reproduce a carrier wave (detection axis) that serves as a phase reference for the demodulation circuit.

(3) Problems to be Solved by the Invention In the PLL circuit used in the demodulation circuit shown in FIGS. 4 and 5, the range in which lock-in is possible is limited, and this range can be The disadvantage is that once it is removed, it cannot return to the original lock-in range.
The circuit had low reliability.

(4) Means for Solving the Problems The present invention was made in view of the above points, and an object of the present invention is to forcibly return to the lock-in range when the PLL circuit becomes unlocked. In order to achieve this purpose, the present invention is configured to include a detection circuit that detects the frequency of error occurrence in the decoder, and a kick pulse generation circuit that applies a kick pulse to the 760 circuit in the PLL circuit using the output of the detection circuit. There is.

(5) Effect In this configuration, the detection circuit that detects the frequency of error occurrence in the decoder detects that the PLL circuit becomes unlocked, and the kick pulse generation circuit applies a kick pulse to the 760 circuit based on the output of this detection circuit. Then, strong 7
One purpose is to return to the lock-in range.

(6) Examples Hereinafter, the present invention will be explained based on the drawings.

1 and 2 are block diagrams showing one embodiment of a digital demodulation circuit according to the present invention. The circuits shown in FIGS. 1 and 2 have a circuit configuration in which an error occurrence frequency detection circuit 1, a kick pulse generation circuit 2, and a U-mute circuit 3 are added to the circuits not shown in FIGS. 4 and 5, respectively. There is.

In FIGS. 1 and 2, the error flag signal and frame synchronization detection signal are output from the PCM decoder 1 to the OR circuit 1.
1. The error flag signal is a flag signal that is set when an error occurs during decoding in the PCM decoder 4. Also, the frame synchronization detection signal is a signal that informs the outside whether or not frame synchronization was achieved during decoding in the PCM decoder 4, and an error occurs in the decode signal when frame synchronization cannot be achieved. For this reason, the frame synchronization signal detection signal is treated in the same manner as the error flag signal, and the OR circuit 11 calculates the logical sum.

The output of the OR circuit 11 is an integral circuit Wa! in order to detect the frequency of error occurrence. 2 through the switching circuit 13
is supplied to Here, the switching circuit 13 detects whether the 1st cycle integrated by the integrating circuit 12 exceeds the same value set in the switching circuit 13, and outputs °゛l°゛ when it exceeds the threshold value. , t41i or less, the output of the switching circuit 13 is branched and supplied to the mute circuit 3 and the multivibrator 2I.In the mute time!1i43, the output of the PCM decoder 4 when errors occur frequently Since the audio signal is just noise, it is muted. Also, the multivibrator 21 is an unstable multivibrator, and when the output of the switching circuit 13 is °゛1'', an image is fired. Oscillation is stopped when the signal is '0''. The output of this multivibrator 21 is waveform-shaped by a waveform shaping circuit 22 and then supplied to the 700 circuit 5 as a kick pulse.

Next, the operation will be explained.

When an error occurs in the PCM decoder 4 and the output of the switching circuit 13 becomes Jllll+ as described above,
The mute circuit 3 mutes the audio output of the PCM decoder 4, and the multivibrator 2I starts oscillating. Immediately after the oscillation, when the occurrence of errors in the PCM decoder 4 has subsided, the oscillation ends with only one pulse, as shown in one word B shown by the solid line in FIG. 3(b). Incidentally, if the error continues further, the oscillation of the multivibrator 210 will continue as shown by the signal B' indicated by the broken line in FIG. 3(b). The waveform shaping circuit 22 waveform-shapes the output signal B of the multivibrator 21 and generates a signal C (FIG. 3).
is applied as a voltage control signal to the 700 circuit 5. As a result, the salt generation frequency f of the 700 circuit 5 is pulled back to the lock-in range from the frequency f' (FIG. 3) which is out of the lock-in range, and finally settles down to the set frequency t'o. Signal A shown in FIG. 3 shows the state of change in the output of the 700 circuit 5 during this period.

(7) Effects of the Invention As explained above, the present invention provides a digital demodulation circuit having a demodulation circuit including a PLL circuit and a decoder, a detection circuit for detecting the frequency of error occurrence in the decoder, and an output of this detection circuit. Since a kick pulse generation circuit that applies a kick pulse to the 700 circuit is provided, the PLL
When the circuit goes out of lock, it can be forcibly returned to the lock-in range, and the reliability of the demodulation circuit can be improved.

[Brief explanation of drawings]

1 and 2 are block diagrams showing one embodiment of the digital demodulation circuit according to the present invention, FIG. 3 is a waveform diagram explaining the operation of the circuit shown in FIGS. 1 and 2, and FIGS. FIG. 5 is a block diagram showing a conventional digital demodulation circuit. l... Error frequency detection circuit 2... Kick pulse generation circuit 4... Conflict PCM decoder 5... VCO circuit Patent applicant NEC Home Electronics Co., Ltd.

Claims (1)

[Claims] In a digital demodulation circuit having a demodulation circuit including a PLL circuit and a decoder, a detection circuit for detecting the frequency of error occurrence in the decoder;
A digital demodulation circuit comprising: a kick pulse generation circuit that applies a kick pulse to a CO circuit according to the output of the detection circuit.