JPS62120054A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS62120054A JPS62120054A JP26043385A JP26043385A JPS62120054A JP S62120054 A JPS62120054 A JP S62120054A JP 26043385 A JP26043385 A JP 26043385A JP 26043385 A JP26043385 A JP 26043385A JP S62120054 A JPS62120054 A JP S62120054A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- substrates
- film
- stopper
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 229920005989 resin Polymers 0.000 claims abstract description 32
- 239000011347 resin Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 238000005452 bending Methods 0.000 abstract description 7
- 239000003822 epoxy resin Substances 0.000 abstract description 6
- 229920000647 polyepoxide Polymers 0.000 abstract description 6
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 abstract 1
- 229920002050 silicone resin Polymers 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は混成集積回路に関し、特に混成集積回路の折曲
げ構造の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit, and more particularly to an improvement in the folding structure of a hybrid integrated circuit.
（ロ）従来の技術
従来の混成集積回路は第２図に示す如く、二枚の金属基
板＜１１）（１２）と、基板（１１）（１２）を接続す
る絶縁フィルム（１３）と、フィルム（１３）上に設け
た導電路（１４）と、導電路（１４）上に固着した半導
体集積回路、チップ抵抗あるいはチップコンデンサー等
の複数の回路素子（１５）と、回路素子（１５）を被覆
する樹脂膜（１６）とを具備している。(B) Prior art As shown in Figure 2, a conventional hybrid integrated circuit consists of two metal substrates (11) and (12), an insulating film (13) connecting the substrates (11) and (12), and a film. (13) A conductive path (14) provided above, a plurality of circuit elements (15) such as semiconductor integrated circuits, chip resistors, or chip capacitors fixed on the conductive path (14), and covering the circuit element (15). A resin film (16) is provided.
金属基板（１ｔ）（１２）は０．５〜１．０■厚の良熱
伝導性のアルミニウムで形成され、エポキシ樹脂等の接
着剤により基板（１１）（１２）を夫々の厚みだけ離間
させてポリイミド等の絶縁フィルム（１３）で接続する
。絶縁フィルム（１３）の反対主面には導電路（１４）
となる銅箔を貼着しておき、銅箔を選択的にエツチング
して所望形状の導電路（１４）を形成する。導電路（１
４）は一方の基板（１２）の端部に外部リード（１７）
を半田付けするパッドを並べ、バッドから導電路（１４
）を絶縁フィルムク１３〉上に延在妨せる。回路素子（
１５）を固着する導電路（１４）の部分は両方の基板（
１１）（１２）上に位置する様に設計し、基板（１１）
（１２）の離間部分には折曲げのために回路素子（１５
）を設けない。回路素子（１５〉を固着した後、回路素
子（１５）を保護するために回路素子（１５）上にエポ
キシ樹脂等を塗布し樹脂膜（１６）を形成する。しかる
後、基板（１１）＜１２＞の離間部分の絶縁フィルム（
１３）を折曲げ配置するものである。The metal substrates (1t) (12) are made of aluminum with good thermal conductivity and have a thickness of 0.5 to 1.0 mm, and the substrates (11) and (12) are separated by their respective thicknesses using an adhesive such as epoxy resin. Connect with an insulating film (13) made of polyimide or the like. There is a conductive path (14) on the opposite main surface of the insulating film (13).
A conductive path (14) having a desired shape is formed by selectively etching the copper foil. Conductive path (1
4) is an external lead (17) at the end of one board (12).
Line up the pads to be soldered, and connect the conductive path (14
) on the insulating film 13〉. Circuit element (
The part of the conductive path (14) that fixes the substrate (15)
11) Designed to be located on (12), the board (11)
(12) is provided with a circuit element (15) for bending.
) is not provided. After fixing the circuit element (15), epoxy resin or the like is applied on the circuit element (15) to form a resin film (16) in order to protect the circuit element (15). Insulating film (
13) is arranged by bending.
上述した同様の技術は特願昭５５−１６９８６８号公報
に記載されている。A technique similar to that described above is described in Japanese Patent Application No. 169868/1983.
（ハ）発明が解決しようとする問題点
上述した従来の技術では、回路素子を保護するために塗
布していた樹脂膜（１６）が第３図に示す様に基板（１
１）（１２）の離間部まで流出して基板を折曲げるのに
必要な折曲げ距離が短くなり基板の折曲げが行なえなく
なる欠点があった。(c) Problems to be Solved by the Invention In the conventional technology described above, the resin film (16) applied to protect the circuit elements is removed from the substrate (16) as shown in FIG.
1) There is a drawback that the bending distance required for bending the substrate becomes short because the liquid flows to the spaced part of (12), making it impossible to bend the substrate.
（ニ）問題点を解決するための手段
本発明は上述した点に鑑みてなされたものであり、第１
図に示す如く、金属基板（１）上に回路素子（５）を組
込んだ後、基板（１）（２）間の離間部上にシリコン系
樹脂を塗布して樹脂止め部（７）を設けた後、回路素子
（５）を保護する樹脂膜（６）を形成する。(d) Means for solving the problems The present invention has been made in view of the above-mentioned points.
As shown in the figure, after the circuit element (5) is assembled on the metal substrate (1), silicone resin is applied on the space between the substrates (1) and (2) to seal the resin stopper (7). After the formation, a resin film (6) is formed to protect the circuit element (5).
くホ）イ乍用
この様に本発明によれば、基板（１）（２）間の離間部
上にシリコン系樹脂を塗布して樹脂止め部（７）を設け
ることにより、樹脂膜（６）の流出を防げるものである
。As described above, according to the present invention, the resin film (6) is coated with silicone resin on the spaced apart part between the substrates (1) and (2) to provide the resin stopper part (7). ) can be prevented from leaking.
（へ）実施例
以下に図面に示した実施例に基づいて本発明の詳細な説
明する。(F) Examples The present invention will be described in detail below based on the examples shown in the drawings.
第１図は本発明の実施例を示す混成集積回路である。FIG. 1 shows a hybrid integrated circuit showing an embodiment of the present invention.
本発明の混成集積回路は二枚の金属基板（１）（２）と
基板（１）（２）を接続する絶縁フィルム（３）と、フ
ィルム（３）上に設けた導電路（４〉と、導電路（４）
上に固着した半導体集積回路、チップ抵抗あるいはチッ
プコンデンサー等の複数の回路素子（５）と、回路素子
（５）を被覆する樹脂膜（６）と、樹脂止め部（７）と
を具備している。The hybrid integrated circuit of the present invention includes two metal substrates (1) (2), an insulating film (3) connecting the substrates (1) and (2), and a conductive path (4) provided on the film (3). , conductive path (4)
It comprises a plurality of circuit elements (5) such as semiconductor integrated circuits, chip resistors, or chip capacitors fixed thereon, a resin film (6) covering the circuit elements (5), and a resin stopper (7). There is.
金属基板（１）（２）は０，５〜１．０１ｍ１厚の良熱
伝導性のアルミニウムで形成され、エポキシ樹脂等の接
着剤により基板（Ｌ）（２）を夫々の厚みだけ離間部せ
てポリイミド等の絶縁フィルム（３）で接続する。The metal substrates (1) and (2) are made of aluminum with good thermal conductivity and have a thickness of 0.5 to 1.01 m1, and the substrates (L) and (2) are separated by their respective thicknesses using an adhesive such as epoxy resin. Connect with an insulating film (3) made of polyimide or the like.
絶縁フィルム（３）の反対主面には導電路（４）となる
銅箔を貼着しておき、＃４箔を選択的にエツチングして
所望形状の導電路（４）を形成する。導電路（４）は一
方の基板（２）の端部に外部リード（８）を半田付けす
るパッドを並べ、バンドから導電路（４）を絶縁フィル
ム（３）上に延在させる。回路素子（５）を固着する導
電路（４）の部分は両方の基板＜１）（２）上に位置す
る様に設計し、基板（１）（２）の離間部分には折曲げ
のために回路素子（５）を設けない。A copper foil serving as a conductive path (4) is adhered to the opposite main surface of the insulating film (3), and the #4 foil is selectively etched to form a conductive path (4) in a desired shape. The conductive path (4) is arranged with pads to which external leads (8) are soldered at the end of one substrate (2), and extends from the band onto the insulating film (3). The portion of the conductive path (4) that fixes the circuit element (5) is designed so that it is located on both substrates <1) (2), and the separated portion of the substrates (1) and (2) is provided with a portion for bending. No circuit element (5) is provided in the.
回路素子（５）を固着した後、本発明の特徴である樹脂
止め部（７）を設ける。樹脂止め部（７）には接着性の
無いシリコン系樹脂を用い、基板（１）（２）間の離間
部上にシリコン系樹脂を塗布して樹脂止め部（７）を設
ける。樹脂止め部（７）はシリコン系樹脂を用いている
ため、硬化しても弾性力を有しているので基板（１）（
２）を折曲げ配置する時にはなんら支障はない。After fixing the circuit element (5), a resin stopper (7), which is a feature of the present invention, is provided. A non-adhesive silicone resin is used for the resin stopper (7), and the resin stopper (7) is provided by applying the silicone resin on the space between the substrates (1) and (2). Since the resin stopper (7) is made of silicone resin, it has elasticity even after it hardens, so it does not stick to the substrate (1) (
2) There is no problem when folding and arranging.
樹脂止め部（７）を設けた後、従来と同様に回路素子（
５）を保護するためにエポキシ系の樹脂を塗布し樹脂膜
（６）を形成して回路素子（５）を保護する。しかる後
、基板（１）（２）の離間部分の絶縁フィルム（３）を
折曲げ配置する。After installing the resin stopper (7), attach the circuit element (
5), an epoxy resin is applied to form a resin film (6) to protect the circuit element (5). After that, the insulating film (3) on the separated portions of the substrates (1) and (2) is bent and arranged.
斯る本発明に依れば、基板（１）＜２）の離間部上に樹
脂止め部（７）を設けることにより、樹脂膜（６）の流
出が防げ基板（１）（２）の折曲げ配置がスムーズに行
なえる。According to the present invention, by providing the resin stopper (7) on the separated part of the substrates (1)<2), the resin film (6) can be prevented from flowing out and the substrates (1) and (2) can be folded. Bending placement can be done smoothly.
（ト）発明の効果
上述した如く、本発明に依れば、基板の離間部にシリコ
ン系の樹脂を塗布し樹脂止め部を設けることにより、回
路素子を保護する樹脂膜を形成しても樹脂膜の流出を防
ぐことができるので、従来発生していた基板の折曲げが
行なえない欠点を補うことができ生産能率が向上するも
のである。(G) Effects of the Invention As described above, according to the present invention, by applying a silicone resin to the spaced apart portions of the substrate and providing a resin stopper, even if a resin film is formed to protect the circuit elements, the resin Since the film can be prevented from flowing out, the conventional disadvantage of not being able to bend the substrate can be compensated for and production efficiency can be improved.
第１図は本発明の実施例を示す断面図、第２図および第
３図は従来例を示す断面図である。
（１）＜２＞・・・金属基板、 （３）・・・絶縁フィ
ルム、（４）・・・導電路、 （５）・・・回路素子、
（６）・・・樹脂膜、（７）・・・樹脂止め部、 （
８）・・・外部リード。FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 and 3 are sectional views showing a conventional example. (1)<2>...Metal substrate, (3)...Insulating film, (4)...Conducting path, (5)...Circuit element,
(6)...Resin film, (7)...Resin stopper, (
8)...External lead.
Claims (1)
結合する絶縁フイルムと、該フイルム上に設けた所望形
状の導電路と、該導電路上に設けた複数の回路素子と、
該回路素子を被覆する樹脂膜とを具備し、前記絶縁フイ
ルムを折曲げて前記基板の金属露出面が接する様に配置
した混成集積回路に於いて、前記二枚の金属基板の離間
部上に樹脂止め部を有することを特徴とした混成集積回
路。(1) Two metal substrates, an insulating film that connects the two metal substrates at a distance, a conductive path of a desired shape provided on the film, and a plurality of circuit elements provided on the conductive path. ,
a resin film covering the circuit element, and in a hybrid integrated circuit in which the insulating film is bent and arranged so that the exposed metal surfaces of the substrates are in contact with each other, A hybrid integrated circuit characterized by having a resin stopper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26043385A JPH0719858B2 (en) | 1985-11-20 | 1985-11-20 | Method for manufacturing hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26043385A JPH0719858B2 (en) | 1985-11-20 | 1985-11-20 | Method for manufacturing hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62120054A true JPS62120054A (en) | 1987-06-01 |
| JPH0719858B2 JPH0719858B2 (en) | 1995-03-06 |
Family
ID=17347866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26043385A Expired - Lifetime JPH0719858B2 (en) | 1985-11-20 | 1985-11-20 | Method for manufacturing hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719858B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5780933A (en) * | 1995-05-12 | 1998-07-14 | Kabushiki Kaisha Toshiba | Substrate for semiconductor device and semiconductor device using the same |
| US6022763A (en) * | 1996-05-10 | 2000-02-08 | Kabushiki Kaisha Toshiba | Substrate for semiconductor device, semiconductor device using the same, and method for manufacture thereof |
-
1985
- 1985-11-20 JP JP26043385A patent/JPH0719858B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5780933A (en) * | 1995-05-12 | 1998-07-14 | Kabushiki Kaisha Toshiba | Substrate for semiconductor device and semiconductor device using the same |
| US6022763A (en) * | 1996-05-10 | 2000-02-08 | Kabushiki Kaisha Toshiba | Substrate for semiconductor device, semiconductor device using the same, and method for manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0719858B2 (en) | 1995-03-06 |
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