JPS62116543U - - Google Patents
Info
- Publication number
- JPS62116543U JPS62116543U JP269986U JP269986U JPS62116543U JP S62116543 U JPS62116543 U JP S62116543U JP 269986 U JP269986 U JP 269986U JP 269986 U JP269986 U JP 269986U JP S62116543 U JPS62116543 U JP S62116543U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- metal substrate
- substrate
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 238000005452 bending Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はこの考案の実施例による混成集積回路
の構成断面図、第２図は従来の混成集積回路の構
成断面図、第３図は絶縁金属基板の部分断面図で
ある。各図において、
１：絶縁金属基板、１ａ：リード接続部、４…
…導体層、５：回路部品、６：ケース、７：外部
接続リード、９：ボンデイングワイヤ。
FIG. 1 is a sectional view of the structure of a hybrid integrated circuit according to an embodiment of this invention, FIG. 2 is a sectional view of the structure of a conventional hybrid integrated circuit, and FIG. 3 is a partial sectional view of an insulated metal substrate. In each figure, 1: insulated metal substrate, 1a: lead connection part, 4...
...conductor layer, 5: circuit component, 6: case, 7: external connection lead, 9: bonding wire.
Claims (1)
に組み込み、該基板上の導体層にケース内へ引き
込んだ外部接続リードを接続して成る混成集積回
路において、前記絶縁金属基板上の導体層と外部
接続リードとの間をワイヤボンデイングにより接
続したことを特徴とする混成集積回路の構造。 (2) 実用新案登録請求の範囲第１項記載の混成
集積回路の構造において、絶縁金属基板がその一
側縁をＬ字状に起立屈曲して成るリード接続部を
有し、該リード接続部と外部接続リードとの間が
ワイヤボンデイングにより接続されていることを
特徴とする混成集積回路の構造。[Scope of Claim for Utility Model Registration] (1) A hybrid integrated circuit comprising an insulated metal substrate on which circuit components are mounted is assembled in a case, and an external connection lead drawn into the case is connected to a conductor layer on the substrate, A hybrid integrated circuit structure characterized in that a conductor layer on an insulated metal substrate and external connection leads are connected by wire bonding. (2) In the structure of the hybrid integrated circuit described in claim 1 of the utility model registration claim, the insulating metal substrate has a lead connection portion formed by bending one side edge of the substrate in an L-shape, and the lead connection portion A structure of a hybrid integrated circuit characterized in that the and external connection leads are connected by wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP269986U JPS62116543U (en) | 1986-01-13 | 1986-01-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP269986U JPS62116543U (en) | 1986-01-13 | 1986-01-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62116543U true JPS62116543U (en) | 1987-07-24 |
Family
ID=30781782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP269986U Pending JPS62116543U (en) | 1986-01-13 | 1986-01-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62116543U (en) |
-
1986
- 1986-01-13 JP JP269986U patent/JPS62116543U/ja active Pending