JPS62115379A - Logical lsi testing circuit - Google Patents

Abstract

PURPOSE:To perform discriminating test of accurate highest working frequency in the state of a wafer of low cost by providing an M-stage delay circuit and an N-stage delay circuit made by connecting M units and N units of basic gates having any equal load in series. CONSTITUTION:To make speed test of an LSI, an M-stage delay circuit 300 made by connecting M(>=1) units of basic gates 100-1-100-M having any equal load in series and an N-stage delay circuit 301 made by connecting N(>M) units of basic gates 101-1-101-N in series are connected in parallel to an input circuit 50, and output circuits 200, 201 are connected respectively to output side of circuits 300, 301, and incorporated in a logical LSI as a testing circuit. When any digital signals are inputted to an input terminal 10, the signals are passed through the circuit 50 and circuits 200, 201 and outputted to output terminals 11, 12 delaying respectively by transmission delay time tauM, tauN, Difference in transmission delay time of N-M units of basic gates, and accordingly, transmission delay time tauF per unit basic gate can be obtained by a specified expression.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic LSI test circuits, and particularly to logic III test circuits that are updated at high speed.

[Conventional technology]

Conventionally, this type of logic LSI has a configuration that does not include a circuit for measuring the transmission delay time of the basic gate as an LSI test circuit. As a result, if the operating frequency of the designed LSI was higher than the test frequency conducted in the unused state, it was impossible to test the highest operating frequency in the unused state. Therefore, we have developed a high-quality product with the highest operating frequency.
Defective product discrimination testing methods include determining non-defective products by specifying the transmission delay time between the input terminal and output terminal, which is 2 in the - state, and determining non-defective products by actually conducting an operation test after assembly. There is a way to determine.

[Problem that the invention seeks to solve]

However, with the former testing method, it is not possible to accurately measure the transmission delay time due to errors due to variations in LSI test models of the same type and errors in measurement values of the testing machine. In the current testing method, which distinguishes between good and defective products by rounding and setting a standard at a certain point, good products are judged to be defective or defective. As a result, the yield of the product decreases, resulting in a disadvantage that the product cost increases. In addition, in the latter test method, the test is conducted on the wafer to determine whether it is a good product or a defective product, and the cost after one assembly is higher than in the case of wafers. It has the disadvantage of high cost. In addition, if the propagation delay time cannot be measured using a tester with a low test frequency, we will introduce a tester with a high test frequency and good measurement resolution during development.

Since the highest operating frequency must be tested, there is a drawback that a large amount of development and equipment costs are required.

[Means for solving problems]

The logic LSI test circuit of the present invention includes, as an LSI test circuit, an M-stage delay circuit in which M basic gates having arbitrary equal loads are connected in series, and an N-stage delay circuit in which N basic gates are connected in series. The input of the M-stage delay circuit and the N
The circuit includes an input circuit connected in parallel to the input of the stage delay circuit, an output circuit connected to the output of the M stage delay circuit, and an output circuit connected to the output of the N stage delay circuit.

〔Example〕

The present invention will now be described with reference to the drawings.

FIG. 1 shows the block factors of the present invention. To the input terminal 10,
When an arbitrary digital signal is input, the input signal passes through the input circuit 50, M-stage basic gates (100-1 to 100-M), and the output circuit 200, and is output to the output terminal 11 with a delay of the transmission delay time τM. Ru. At the same time, the input signal is connected to the input circuit 50 and the N-stage basic games) 101-1 to 101-M.
It passes through the output circuit 201 and is output to the output terminal 12 with a delay of the transmission delay time τM. Here, input circuit 50 and N
M-stage basic gate of stage delay circuit 300 and output circuit 201
Since the signals pass through elements having the same configuration, the transmission delay time caused by .tau.M can be equal to .tau.M. That is, the difference (τN-τM) between the transmission time by the N-stage delay circuit 301 and the transmission delay time by the M-stage delay circuit 300 is the transmission delay time of the basic game (N-M).

Therefore, the transmission delay time τF per stage of basic gate
can be obtained from the following formula.

This has conventionally been conveniently used as a transmission delay time side circuit in prototype LSI ICs.

The transmission delay times of the output circuits 200 and 201, which were previously assumed to be equal, do not completely match due to differences in input capacitance and input impedance between the terminals of the terminal system of the measurement system. Also, the measured propagation delay time itself includes errors due to the testing equipment. If all these differences are defined as error 7e, then 7F includes an error of re/(N-M) (
It becomes. Therefore, by choosing a large value of (N-M), the error included in τF can be made negligible.

Even when the test frequency and measurement resolution of the LSI tester are low, by increasing the number of delay stages M, it is possible to increase the value of τM up to the measurable range of the tester.

For example, when designing an LSI circuit, if the design satisfies the maximum operating frequency if the propagation delay time per basic gate stage is within Tmax in the worst case, then test the maximum operating frequency of the LSI and measure it during the test. If the transmission delay time τF is less than or equal to the above-mentioned τmax, the standard may be set to pass. That is, the highest operating frequency can be tested by accurately measuring the propagation delay time.

Further, even in the case of a semi-custom LSIVcB, the highest operating frequency can be similarly tested by preparing the circuit according to the present invention as a block library or incorporating it as a basic component in advance.

〔Effect of the invention〕

As explained above, the present invention includes a circuit for measuring the propagation delay time of an arbitrary basic gate as an LSI speed test circuit on the same chip of a logic LSI, and uses the circuit to measure the propagation delay time. By doing so, it is possible to perform a test for determining the highest operating frequency more accurately than in the past. Namely.

In the form of a wafer, which costs less than after assembly.

Since it is possible to perform a test to determine the highest operating frequency more accurately than before, it has the effect of lowering product costs. In addition, by using inexpensive low-speed testing machines and testing machines that have already been introduced,
Since the highest operating frequency can be tested, it also has the effect of reducing equipment costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention. 300...M-stage delay circuit, 301...
N-stage delay circuit 210...Input terminal, 11.12
...Output terminal, 50...Input circuit, 1
00-1 to 100-M. 101-1 to 101-N・・・Basic gate, 20
0゜201...Output circuit. Agent Patent Attorney Oto Uchihara 4 \1. ) (, le 1 pa・

Claims (1)

[Claims] In logic LSI, in order to perform LSI speed test,
An M-stage delay circuit in which M (≧1) basic gates having arbitrary equal loads are connected in series, and the basic gates are connected in series with N (>
M) N-stage delay circuits connected in series, an input circuit in which the input of the M-stage delay circuit and the input of the N-stage delay circuit are connected in parallel, and an output circuit connected to the output of the M-stage delay circuit. , an output circuit connected to the output of an N-stage delay circuit, and is incorporated into a logic LSI as a test circuit.