JPS62114312A - Variable gain amplifier - Google Patents
Variable gain amplifierInfo
- Publication number
- JPS62114312A JPS62114312A JP25262185A JP25262185A JPS62114312A JP S62114312 A JPS62114312 A JP S62114312A JP 25262185 A JP25262185 A JP 25262185A JP 25262185 A JP25262185 A JP 25262185A JP S62114312 A JPS62114312 A JP S62114312A
- Authority
- JP
- Japan
- Prior art keywords
- differential
- variable gain
- amplifier
- trs
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007423 decrease Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 241000689109 Corella <basidiomycete fungus> Species 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は利得可変増幅器に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a variable gain amplifier.
従来、利得町変増幅器として第2図に示すものが知られ
ている(特開昭57−211814号公報参照)。Conventionally, a variable gain amplifier as shown in FIG. 2 has been known (see Japanese Patent Laid-Open No. 57-211814).
図示の増幅器は、差動制御回路1a、減衰回路1b。The illustrated amplifier includes a differential control circuit 1a and an attenuation circuit 1b.
ダイオード回路ICからなる利得制御回路1を有し。It has a gain control circuit 1 consisting of a diode circuit IC.
減衰回路1bの減衰器R,,、R,は、入力信号S1の
供給を受は出力信号S、を出力する差動増1@器2の差
動トランジスタQ、、Q、の夫々のエミッタ電極に直列
に接続されている。前記利得制御回路1の制御端子3に
制御信号S3が印加されると、ダイオード回路1aのダ
イオードD、、D、の接続対向点4及び減衰回路1bの
減衰器R,,R,の接続中間点5の電流が変化し、差動
増幅器2の入力電流が増減して利得が制御される。The attenuators R, , R, of the attenuation circuit 1b are connected to the emitter electrodes of the differential transistors Q, , Q, of the differential amplifier 1@unit 2, which receive the input signal S1 and output the output signal S. connected in series. When the control signal S3 is applied to the control terminal 3 of the gain control circuit 1, the connection point 4 of the diodes D, , D, of the diode circuit 1a and the connection midpoint of the attenuators R, , R, of the attenuation circuit 1b. 5 changes, the input current of the differential amplifier 2 increases or decreases, and the gain is controlled.
この利得可変増幅器の最大利得G頗及び最小利得G−は
次式で示される。The maximum gain G and minimum gain G- of this variable gain amplifier are expressed by the following equations.
T
4 ・□
O
VT
2几g+2・−
O
RL:コレクタ抵抗(R3,R4)
RB:エミッタ電極(几t、Rt)
Ia:差aトラ4ンジスタQs 、 Q4のコレクタ電
流上式より明らかな様に、抵抗RLを大きく、また抵抗
RBを小さく設定することにより、上述した利得町変増
幅器は広い可変幅を有するが、差動トランジスタQ、、
Q、のベース容量やコレクタ容量の影響でその周波数特
性が低下してしまうという欠点を併せ持つものであった
。T 4 ・□ O VT 2⇠g+2・− O RL: Collector resistance (R3, R4) RB: Emitter electrode (⇠t, Rt) Ia: Difference a 4 transistor Qs, as is clear from the above formula for the collector current of Q4 By setting the resistor RL large and the resistor RB small, the gain variable amplifier described above has a wide variable range, but the differential transistor Q,...
It also had the disadvantage that its frequency characteristics deteriorated due to the influence of the base capacitance and collector capacitance of Q.
〔発明の目的j
本発明は上述の従来の問題点lこ鑑み成されたもので、
広帯域な周波数特性を有すると共に広い可変利得幅を持
つ利得町変増幅器を得ることを目的とする。[Objective of the Invention The present invention has been made in view of the above-mentioned conventional problems,
The purpose of this invention is to obtain a variable gain amplifier that has wide frequency characteristics and a wide variable gain width.
本発明に係る利得可変増幅器は1例えば第1図に示す如
く差動増幅器2の差動トランジスタQ、、Q。The variable gain amplifier according to the present invention includes differential transistors Q, , Q of a differential amplifier 2, for example, as shown in FIG.
の各エミッタ電極に夫々のベース電極が接続され。A respective base electrode is connected to each emitter electrode.
互いのコレクタ電極同士、エミッタ電極同士が接続され
るトランジスタQ、 、 Q、を付設し、このトランジ
スタQ、、Q、のベース・エミッタ電極間容量を可変さ
せ、高利得時にピーキングをかけ広帯域な周波数特性と
広い可変利得幅の双方を得ることを可能としたものであ
る。Transistors Q, , Q, whose collector electrodes are connected to each other and emitter electrodes to each other are attached, and the capacitance between the base and emitter electrodes of these transistors Q, , Q is varied, and peaking is applied at high gain to achieve a wide band frequency. This makes it possible to obtain both characteristics and a wide variable gain range.
第1図に本発明の一実施例を示す。第2図に示した従来
の利得町変増幅器と異なる点は、トランジスタQ・〜Q
i、抵抗Rg、几6.及び電流源■1が付加されたこと
にある。すなわち、差動増幅器2の差動トランジスタQ
、 、 Q、の各エミッタ電極には、夫々トランジスタ
Q、、Q、のベース電極が接続され。FIG. 1 shows an embodiment of the present invention. The difference from the conventional gain variable amplifier shown in Figure 2 is that the transistors Q.
i, resistance Rg, 6. and the addition of current source (1). That is, the differential transistor Q of the differential amplifier 2
, , Q, are connected to the base electrodes of transistors Q, , Q, respectively.
こレラトランジスタQ?、 Q、のコレクタ電極は共に
抵抗R,を介して電源に接続される。さらに前記トラン
ジスタQ1.Q、のエミッタ電極は共通接続されトラン
ジスタQ、のコレクタに接続される。このトランジスタ
Q、のベース電極は差動制御回路1aの制御トランジス
タQ、のベース電極に接続され、エミッタ1tfflは
トランジスタQ6のエミッタ電極に接続されると共に電
流源11に接続される。さらに上記トランジスタQ6の
ベース電極は制御トランジスタQ2のベース電極に接続
され、コレクタ電極は抵抗島を介して電源に接続される
。Corella transistor Q? , Q, are both connected to a power supply via a resistor R,. Furthermore, the transistor Q1. The emitter electrodes of Q, are commonly connected and connected to the collector of transistor Q. The base electrode of this transistor Q is connected to the base electrode of the control transistor Q of the differential control circuit 1a, and the emitter 1tffl is connected to the emitter electrode of the transistor Q6 and to the current source 11. Furthermore, the base electrode of the transistor Q6 is connected to the base electrode of the control transistor Q2, and the collector electrode is connected to the power supply via the resistive island.
上述の如く構成された利得可変増幅器によれば。According to the variable gain amplifier configured as described above.
トランジスタQヮ、Q8のベース・エミッタ電極間容量
が、そのトランジスタに流れる電流によって変化し、こ
れにより高利得時に帯域特性の補償(ピーキング)が行
われるものである。すなわち、差動制御回路1aの制御
トランジスタQ、 、 Q2のオン・オフに応じ、トラ
ンジスタQ7.Q、に流れる電流量は制御される。例え
ば、制御トランジスタQ、がオンし、ダイオード回路I
C側に電流が流れるときは(高利得時)、トランジスタ
Q、、Q、にも電流が流れ、そのペース台エミッタ電極
間容量は増大する。The capacitance between the base and emitter electrodes of the transistors Qヮ and Q8 changes depending on the current flowing through the transistors, thereby compensating (peaking) the band characteristics at high gain. That is, depending on whether the control transistors Q, , Q2 of the differential control circuit 1a are turned on or off, the transistors Q7, . The amount of current flowing through Q is controlled. For example, the control transistor Q turns on, and the diode circuit I
When current flows to the C side (at high gain), current also flows to transistors Q, , Q, and the capacitance between the emitter electrodes of the pace board increases.
また、制御トランジスタQ2側がオンし、−減衰回路l
b側に16流が流れるときは(低利得時)、トランジス
タQ、、Q、に流れる電流量は減少し、そのベース・エ
ミッタ電極間容量も減少する。Also, the control transistor Q2 side is turned on, and - the attenuation circuit l
When 16 current flows to the b side (at low gain), the amount of current flowing through the transistors Q, , Q decreases, and the capacitance between the base and emitter electrodes also decreases.
よって1本発明に係る利得可変増幅器は上述のようなト
ランジスタQγ+Qsの容量変化により、高周波におけ
る帰還債が減少し、高利得時には帯域特性の補償(ピー
キング)が行われ、広帯域な周波数特性を得ることがで
きる。また、低利得時にはピーキングは行われないため
、従来回路同様広い可変利得幅を維持することができる
。Therefore, in the variable gain amplifier according to the present invention, due to the capacitance change of the transistor Qγ+Qs as described above, the feedback bond at high frequencies is reduced, and when the gain is high, band characteristic compensation (peaking) is performed, and wide band frequency characteristics can be obtained. I can do it. Furthermore, since peaking is not performed when the gain is low, a wide variable gain width can be maintained as in the conventional circuit.
以上説明したように不発明によれば、広帯域な周波数特
性と広い可変利得幅の双方を兼ね備えた。As explained above, according to the invention, both broadband frequency characteristics and wide variable gain width are provided.
利得可変増幅器を提供することができる。A variable gain amplifier can be provided.
第1図は本発明の一実施例に係る利得可変増幅器の構成
図、第2図は従来の利得可変増幅器の構成図。
1・・・利得制御回路、 2・・・差動増幅器。
P、、P2・・・ダイオード、 R,、R,・・
・抵 抗。
Ql、Q、、Q、・・・制御トランジスタ。
Q、、Q、・・・差動トランジスタ、 Qy、Qg・
・・トランジスタ。FIG. 1 is a block diagram of a variable gain amplifier according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional variable gain amplifier. 1... Gain control circuit, 2... Differential amplifier. P,, P2...Diode, R,, R,...
・Resistance. Ql, Q,,Q,...control transistor. Q,,Q,...differential transistor, Qy,Qg・
...Transistor.
Claims (1)
ッタ電極と他方のエミッタ電極との間を接続する2つの
直列抵抗と、この直列抵抗に並列接続される対向した2
つのダイオードと、ベース電極が夫々前記差動対トラン
ジスタの一方のエミッタ電極と他方のエミッタ電極とに
接続され、互いのコレクタ電極同士及びエミッタ電極同
士が接続される第1、第2のトランジスタと、前記直列
抵抗の中間接続点ならびに前記2つのダイオードの中間
接続点における電流を制御信号に応じて差動的に変化さ
せると共に前記第1、第2のトランジスタに流れる電流
を変化させる電流変化手段とを備え、前記制御信号の増
減により利得が変化するように構成したことを特徴とす
る利得可変増幅器。Two series resistors are connected between one emitter electrode and the other emitter electrode of the differential pair transistors constituting the differential amplifier, and two opposite resistors are connected in parallel to the series resistors.
a diode, first and second transistors whose base electrodes are respectively connected to one emitter electrode and the other emitter electrode of the differential pair transistors, and whose collector electrodes and emitter electrodes are connected to each other; Current changing means that differentially changes the current at the intermediate connection point of the series resistor and the intermediate connection point of the two diodes according to a control signal, and also changes the current flowing through the first and second transistors. A variable gain amplifier comprising: a variable gain amplifier configured such that the gain changes according to an increase/decrease in the control signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25262185A JPS62114312A (en) | 1985-11-13 | 1985-11-13 | Variable gain amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25262185A JPS62114312A (en) | 1985-11-13 | 1985-11-13 | Variable gain amplifier |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62114312A true JPS62114312A (en) | 1987-05-26 |
Family
ID=17239905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25262185A Pending JPS62114312A (en) | 1985-11-13 | 1985-11-13 | Variable gain amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62114312A (en) |
-
1985
- 1985-11-13 JP JP25262185A patent/JPS62114312A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4395643A (en) | Broadband circuit with rapidly variable resistor | |
US4547741A (en) | Noise reduction circuit with a main signal path and auxiliary signal path having a high pass filter characteristic | |
JPS62250706A (en) | Variable attenuator | |
JPS6333727B2 (en) | ||
JPS6027449B2 (en) | Push-pull amplifier | |
US4365206A (en) | Differential amplifier | |
JPS62114312A (en) | Variable gain amplifier | |
JPS631768B2 (en) | ||
JP2504075B2 (en) | Transistor amplifier | |
US4303890A (en) | Circuit arrangement for transferring a signal | |
JPS62114313A (en) | Variable gain amplifier | |
JPH0114726B2 (en) | ||
JPH0239881B2 (en) | ||
JPH0154884B2 (en) | ||
JPH0241929Y2 (en) | ||
JPS58213517A (en) | Gain control type differential amplifier | |
JPS6259926B2 (en) | ||
JPH0346406A (en) | Variable gain amplifier | |
JP2969678B2 (en) | Band correction circuit | |
JPS6143304Y2 (en) | ||
JPS58108810A (en) | Variable gain amplifier | |
JPH0570325B2 (en) | ||
JPH0578965B2 (en) | ||
JPS6125312A (en) | Amplifier | |
JPH0545088B2 (en) |