JPS62102556A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a complementary type (field effect transistor (hereinafter referred to as CMOS)
Regarding integrated circuits including integrated circuits (abbreviated as FE'r), latch-up (1at
chup) phenomenon.

[Conventional technology]

Figure 2 is a wiring diagram showing the internal wiring of a conventional semiconductor integrated circuit including a CMt)S FWT'. ) deme 5, (21 is the power supply wiring using metal wiring used inside the integrated circuit, (3) is the ground wiring used inside the semi-harmful circuit, and (4) is the ground wiring ( 3) is a ground pad for connecting external circuits in a low-temperature manner, and (5) is a signal pad for inputting/outputting 1gr between the semiconductor integrated circuit and the external circuit.

In a semiconductor integrated circuit as shown in Fig. 2, when pulse noise or nervous noise enters from the signal pad (5) or power supply pad (1), the CMOSFET operates due to this noise. As a result, a so-called latch-up phenomenon tends to occur, in which a control signal is generated to maintain the state after the operation, and that state is held. It will be held until the supply is cut off, and eventually CMOSFgr
may be physically destroyed.

[Problem that the invention seeks to solve]

Conventional semiconductor integrated circuits such as MOSFET's have a problem in that the latch-up phenomenon described above is likely to occur.Furthermore, once the latch-up phenomenon occurs, it can lead to destruction of the semiconductor integrated circuit. There was also a problem in that there were cases.

This invention was made to solve the above-mentioned problems, and it makes it difficult for the latch-up phenomenon to occur.
Moreover, it is an object of the present invention to provide a semi-obtainable transverse cover which can easily eliminate the latch-up phenomenon that occurs.

[Means for solving problems]

In the semiconductor integrated circuit according to the present invention, the boundary pad and (
A field effect transistor (hereinafter FE'r) is connected between the source wiring and the
), a latch-up occurred, and Tokiko's F'l! ? The latch-up phenomenon was eliminated by controlling the rt-off state (cutting off the power supply to the source wiring).

[Effect]

The FET connected between the tIf source pad and the power wiring has a resistance of +#F for the first current from the i source pad to the tlLl source, and there is a static capacitance between the power wiring and the trowel. Therefore, a time constant is formed by the resistor and the la capacitance, and the pulse noise entering the four-source wiring from the outside is attenuated by a filtering effect, thereby reducing the chance of occurrence of latch-up phenomenon. Furthermore, when a latch-up phenomenon occurs (FE'r between the source pad and the 4-source wiring is cut off, the 4-voltage of the 1-source wiring disappears, and the latch-up phenomenon is automatically resolved).

[Conventional technology]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a wiring diagram showing an embodiment of the present invention, where the same symbols as in FIG. (8) Hull channel IVIO8Fgr, +91 is n%'r
Channel MOSFE'l' % Ial d F'h'+'
This is a connection point where r +81° (9) gates are connected in parallel.

Under normal conditions, n-channel MOSFET +91 is in the off state p-channel 1VIO8F'! , T +sl is in the off-state, and therefore the p-channel MOSFgrt6
1 is in the on state and is applied from the outside (source, 4 voltage is 4 source pad f1, p channel 1V10S FKT t61 connected to E section source wiring). In this case, p-channel 1VIO8FET +61 resistance and tm wiring +21 static Fl! Depending on the amount of trough, a filter circuit is formed to absorb the noise manually inputted through the four-source pad (11) to attenuate this noise, and when a latch-up phenomenon occurs, the level of the fat point in Figure 1 decreases. , p-channel MOSFET I8) is in the on-state, n-channel MOSFk: 'f' +91 is in the off-state, thus p-channel +VDS FE'r
161 is turned off, the (2) pressure is eliminated, and the latch-up phenomenon is eliminated. When the latch-up phenomenon is eliminated, the 4 pressure at the Ial point becomes high, and the p-channel VIO8FgT ( 6) is turned on and automatically returns to the normal state.

By the way, is there a resistor in place of the n-channel VIO8FET +91 in Figure 1? You can get a lo1-like effect even if you bark for 1 time.

〔Effect of the invention〕

As described above, according to the present invention, the occurrence of the latch-up phenomenon can be suppressed and the latch-up phenomenon can be eliminated, thereby improving the reliability of the system against noise.
Moreover, physical destruction of the semiconductor integrated circuit due to latch-up phenomenon can be prevented.

[Brief explanation of drawings]

Fig. 1 is a wiring diagram showing one embodiment of this invention, Fig. 2 is a wiring diagram showing an embodiment of the present invention.
FIG. 2 is a wiring diagram showing internal wiring of a conventional semiconductor integrated circuit including MOSFET gold. (1) is source pad, (2) is 4 source wiring, (3) is ground wiring, 14) is ground pad, (5) is signal pad, (6
) is p channel/Lt IVIO8FET', (71
is the resistance, (8) is the p-channel MDSFET1 (9) is the n
Channel Ivios FtT. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) In a semiconductor integrated circuit including a CMOS transistor, a power pad to which an external power line is connected, a ground pad to which an external ground line is connected, and a ground terminal inside the semiconductor integrated circuit are connected in parallel. a ground wire connected to the ground pad, a power wire that connects power supply terminals inside the semiconductor integrated circuit in parallel, a field effect transistor connected between the power wire and the power pad, and the semiconductor integrated circuit. 1. A semiconductor integrated circuit, comprising: a control means for detecting a latch-up phenomenon that occurs in the semiconductor integrated circuit, and for cutting off the field-effect transistor when the latch-up phenomenon occurs. (2) The control means for controlling the cutoff of the field effect transistor connected between the power supply pad and the power supply wiring includes a p-channel MOS transistor connected between the power supply pad and the gate of the field effect transistor; , n connected between the gate of the field effect transistor and ground
a channel MOS transistor, the gates of the p-channel and n-channel MOS transistors are connected in parallel;
2. The semiconductor integrated circuit according to claim 1, further comprising means for connecting to a power supply wiring, and a resistor connected between the gate of said p-channel MOS transistor and said power supply pad. (3) The control means for controlling the cutoff of the field effect transistor connected between the power supply pad and the power supply wiring includes a p-channel MOS transistor connected between the power supply pad and the gate of the field effect transistor; A resistor connected between the gate of the field effect transistor and a ground point, a means for connecting the gate of the p-channel MOS transistor and the power supply wiring, and a resistor connected between the power supply pad and the gate of the p-channel MOS transistor. The semiconductor integrated circuit according to claim 1, further comprising a resistor.