JPS61276249A - Input protective circuit - Google Patents
Input protective circuitInfo
- Publication number
- JPS61276249A JPS61276249A JP60117049A JP11704985A JPS61276249A JP S61276249 A JPS61276249 A JP S61276249A JP 60117049 A JP60117049 A JP 60117049A JP 11704985 A JP11704985 A JP 11704985A JP S61276249 A JPS61276249 A JP S61276249A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- input
- gate
- drain
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
Landscapes
- Electronic Switches (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体集積回路の入力保護回路に関するもので
、特に高電圧が入力端子に入力されるおそれのある場合
に、その高電圧が内部回路に印加されないようにするた
めの回路に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an input protection circuit for a semiconductor integrated circuit, and in particular, when there is a risk that a high voltage may be input to an input terminal, the high voltage may be applied to an internal circuit. This relates to a circuit for preventing voltage from being applied.
〔発明の技術的背景および背景技術の問題点〕従来のこ
の種の入力保護回路は、例えば第３図に示すように構成
されていた。即ち、入力端子３に一端が接続され、他端
が集積回路の内部回路１１．１２に接続された入力抵抗
１７と、ドレインが入力抵抗１７の他端に接続されたｎ
チャンネルＭＯ８ＦＥＴ１６とを備え、ＦＥＴ１６のソ
ースおよび基板はアース２に接続されていた。第４図に
示すように入力端子３の電圧ｖ３が高くなって例えば＋
２０Ｖになると、ＦＥＴ１６の基板−ドレインにより構
成されるＰ−Ｎ接合の逆方向ブレークダウンを生じさせ
、節点１５の電位ｖ１５が逆方向ブレークダウン電圧（
図示の例では１０Ｖ程度）より高くはならないようにし
ていた。一方、−２０Ｖが入力されたときには、基板−
ドレインのＰ−Ｎ接合が順方向にバイアスされることを
利用し、節点１５の電位が略Ｏ■となる（正確には０■
よりも、Ｐ−Ｎ接合の降下分だけ低い値）となるように
していた。しかるに、Ｐ−Ｎ接合のブレークダウン電圧
は、基板の不純物濃度に依存するが、精度良く制御する
ことが困難であり、上記のような入力保護回路には、次
のような欠点があった。[Technical Background of the Invention and Problems of the Background Art] A conventional input protection circuit of this type has been configured as shown in FIG. 3, for example. That is, an input resistor 17 whose one end is connected to the input terminal 3 and the other end connected to the internal circuit 11.12 of the integrated circuit, and an input resistor 17 whose drain is connected to the other end of the input resistor 17.
The source of the FET 16 and the substrate were connected to the ground 2. As shown in FIG. 4, the voltage v3 at the input terminal 3 increases, for example +
When the voltage reaches 20V, reverse breakdown of the P-N junction formed by the substrate and drain of the FET 16 occurs, and the potential v15 of the node 15 becomes the reverse breakdown voltage (
In the illustrated example, the voltage was set not to exceed 10 V (approximately 10 V). On the other hand, when -20V is input, the board -
Utilizing the fact that the drain P-N junction is biased in the forward direction, the potential at node 15 becomes approximately O (more precisely 0).
(lower value by the amount of drop of the P-N junction). However, the breakdown voltage of the PN junction, which depends on the impurity concentration of the substrate, is difficult to control accurately, and the input protection circuit as described above has the following drawbacks.
（イ） 入力端子に正の高電圧が入力されたときに、内
部回路に印加される電圧を、電ｍ電圧以下には抑えられ
なかった。即ち、Ｐ−Ｎ接合の逆方向ブレークダウン電
圧が内部回路１１．１２の動作電圧よりも高い場合には
、その動作電圧よりも高い電圧が内部回路に加わるのを
避けることができなかった。(a) When a high positive voltage was input to the input terminal, the voltage applied to the internal circuit could not be suppressed to less than the m voltage. That is, when the reverse breakdown voltage of the PN junction is higher than the operating voltage of the internal circuits 11 and 12, it is impossible to avoid applying a voltage higher than the operating voltage to the internal circuits.
（ロ） Ｐ−Ｎ接合の逆方向ブレークダウンを利用し
ているため、正の高電圧の印加が頻繁に起こる場合に、
装置の寿命を縮める。(b) Since the reverse breakdown of the P-N junction is utilized, when high positive voltage is frequently applied,
Shorten the life of the equipment.
（ハ） 内部回路のＭＯＳＦＥＴ１１．１２に、そのゲ
ート酸化膜の耐圧以上の電圧が加わるおそれがあった。(c) There was a risk that a voltage higher than the withstand voltage of the gate oxide film would be applied to the MOSFETs 11 and 12 in the internal circuit.
ゲート酸化膜の耐圧は、プロセスの微細化に伴い低くな
る傾向があり、ゲート長が２μの場合、ゲート酸化膜の
耐圧は７■程度である。The breakdown voltage of the gate oxide film tends to decrease as the process becomes finer, and when the gate length is 2μ, the breakdown voltage of the gate oxide film is about 7μ.
一方、ＦＥＴ１６の基板−ドレイン間のＰ−Ｎ接合の逆
方向ブレークダウン電圧は基板の濃度に依存するが、精
度よく制御することが難しい。On the other hand, the reverse breakdown voltage of the PN junction between the substrate and the drain of the FET 16 depends on the concentration of the substrate, but is difficult to control accurately.
（発明の目的〕
本発明の目的は、ゲート酸化膜の耐圧が電源電圧に近い
場合にも、内部回路を十分に保護することができ、寿命
も長い入力保護回路を提供することにある。(Object of the Invention) An object of the present invention is to provide an input protection circuit that can sufficiently protect an internal circuit even when the withstand voltage of the gate oxide film is close to the power supply voltage and has a long life.
本発明の入力保護回路は、ドレインが電源に接続され、
ゲートおよびソースが前記入力抵抗に接続された第１導
電形の第１のＭＯＳＦＥＴと、ゲートが電源に接続され
た前記第１導電形の第２のＭＯＳＦＥＴと、一端が電源
に接続され、他端が前記第２のＭＯＳＦＥＴのドレイン
−ソース回路を介して前記入力抵抗に接続された負荷素
子とを備え、前記負荷素子の他端が前記内部回路に接続
されていることを特徴とするものである。The input protection circuit of the present invention has a drain connected to a power supply,
a first MOSFET of a first conductivity type having a gate and a source connected to the input resistor; a second MOSFET of the first conductivity type having a gate connected to a power supply; one end connected to the power supply and the other end; and a load element connected to the input resistor via the drain-source circuit of the second MOSFET, and the other end of the load element is connected to the internal circuit. .
本発明の一実施例を第１図に示す。図示のように、この
実施例の入力保護回路は、入力抵抗７と第１導電形、例
えばｎ−チャンネル形の第１および第２のＭＯＳＦＥＴ
８．９と負荷素子１０とを有する。第１のＭＯＳＦＥＴ
８はドレインが電源１に接続され、ゲートおよびソース
は共通接続されて入力抵抗７を介して入力端子３に接続
されている。第２のＭＯＳＦＥＴ９は、ゲートが電源１
に接続されている。負荷素子１０は一端が電源１に接続
されている。第１のＭＯＳＦＥＴ８のゲートおよびドレ
インは第２のＭＯＳＦＥＴ９を介して負荷素子１０の他
端に接続されるとともに集積回路の内部回路１１．１２
に接続されている。負荷素子１０としては、図示の実施
例では第２導電形例えばｐ−チャンネル形のＭ ＯＳ
Ｆ Ｅ−ｒが用いられ、そのゲートがアースに接続され
ている。An embodiment of the present invention is shown in FIG. As shown, the input protection circuit of this embodiment includes an input resistor 7 and first and second MOSFETs of a first conductivity type, e.g., n-channel type.
8.9 and a load element 10. First MOSFET
Reference numeral 8 has a drain connected to the power supply 1 , and a gate and a source connected in common and connected to the input terminal 3 via the input resistor 7 . The gate of the second MOSFET 9 is the power supply 1
It is connected to the. One end of the load element 10 is connected to the power supply 1. The gate and drain of the first MOSFET 8 are connected to the other end of the load element 10 via the second MOSFET 9, and the internal circuit 11.12 of the integrated circuit.
It is connected to the. In the illustrated embodiment, the load element 10 is a second conductivity type, for example, a p-channel type MOS.
F E-r is used, its gate connected to ground.
上記の回路は以下のように動作する。The above circuit operates as follows.
（イ） 入力信号の電圧■３が■ＣＣ＋■ＴＨＮ８（Ｖ
、ｏは電源１の電圧、Ｖ１１Ｉ８はＦＥＴ８のしきい値
電圧）よりも高い場合。(a) The input signal voltage ■3 is ■CC+■THN8(V
, o is the voltage of power supply 1, and V11I8 is the threshold voltage of FET 8).
この場合、ＦＥＴ８は導通状態となる。ＦＥＴ８は導通
状態の抵抗が入力抵抗７より十分小さくしてあり、この
ため、節点４の電圧ｖ４は■４ ” ｖＣＣ＋ｖＴＨＮ
８
今、Ｖ ｃｃ＝５ Ｖ
ｖＴｌ１８８＝３ Ｖ
ｖ３＝２０ｖ
とすると、■４十８Ｖとなり、ＦＥＴ８のゲート−ドレ
イン間には■ＴＨＮ８に相当する３ｖが加わるだけであ
る。また、Ｆ Ｅ Ｔ’ ９のゲー１〜はＶ。。＝５Ｖ
であるので、そのゲート−トレイン間にも３Ｖが加わる
だけである。また節点５の電圧■５は、ＦＥＴ９により
■。。以下に抑えられるとともにＦＥＴｌ０によりｖｃ
ｏにプルアップされているので、ＶＣＣである。即ち、
ＶＣＣよりも高くなることはない。従って、内部回路１
１．１２のゲートに加わる電圧もＶ。ｃ＝５ Ｖ以下に
抑えられる。In this case, FET8 becomes conductive. The conductive state resistance of FET8 is made sufficiently smaller than the input resistance 7, so the voltage v4 at node 4 is 4'' vCC+vTHN
8 Now, if V cc = 5 V vTl188 = 3 V v3 = 20v, it becomes 48V, and only 3V corresponding to THN8 is applied between the gate and drain of FET8. Also, games 1~ of FET'9 are V. . =5V
Therefore, only 3V is applied between the gate and the train. Also, the voltage (■5) at node 5 is changed to (■) by FET9. . It is suppressed to below and by FETl0, vc
Since it is pulled up to o, it is VCC. That is,
It will never be higher than VCC. Therefore, internal circuit 1
The voltage applied to the gate of 1.12 is also V. c=5 V or less.
一方、負荷素子として用いられているｐチャンネルＭＯ
８ＦＥＴ１０はゲートがアースに接続されているので、
ゲート−ソース間の電圧もＶＣＣ＝５ｖ以下に抑えられ
る。On the other hand, the p-channel MO used as a load element
Since the gate of 8FET10 is connected to ground,
The voltage between the gate and the source can also be suppressed to VCC=5v or less.
第２図には、入力端子３の電圧■３が２０Ｖのときの、
節点４、節点５の電圧Ｖ４．ｖ５が示されている。In Fig. 2, when the voltage 3 of the input terminal 3 is 20V,
Voltage V4 at node 4 and node 5. v5 is shown.
（０）ＶＣＣ＋Ｖ１１１Ｎ８＞■３＞ＶＣＣの場合・こ
の場合、ＦＥＴ８は導通しないが、節点４の電圧■４と
電源１の電圧Ｖ。０との差は■□１１８８以下であるの
で、ＦＥＴ９のゲート−ドレイン間の電圧はＶ （例
えば３Ｖ）以下である。一方、箇Ｔ ＩＩ ８８
点５の電圧■５は、（イ）の場合と同様で■。。＝５Ｖ
よりも高くならない。(0) When VCC+V111N8>■3>VCC In this case, FET8 is not conductive, but the voltage at node 4 is 4 and the voltage at power supply 1 is V. Since the difference from 0 is less than ■□1188, the voltage between the gate and drain of FET 9 is less than V (for example, 3V). On the other hand, the voltage ■5 at point 5 is the same as in case (a). . =5V
It cannot be higher than.
（ハ） 入力信号の電圧ｖ３がＯの場合。(c) When the voltage v3 of the input signal is O.
ＦＥＴＩ ｏはｐチャンネル形で、ゲー１−が接地され
ているので、導通状態にあり、また、ＦＥＴ９はゲート
にＭ’ｆ！ＡＴＩ圧Ｖ。０が印加されているため導通状
態にあるが、ＦＥＴｌ０はＦＥＴ９に比べ導通状態にお
ける抵抗が大となるよう形成されているため、節点５の
電圧Ｖ５は略０となる。FETI o is of the p-channel type and is in a conductive state because its gate 1- is grounded, and FET 9 has M'f! at its gate. ATI pressure V. Since 0 is applied, it is in a conductive state, but since the FET 10 is formed so that its resistance in the conductive state is larger than that of the FET 9, the voltage V5 at the node 5 is approximately 0.
（ニ） 入力信号の電圧ｖ３が負の場合。(d) When the voltage v3 of the input signal is negative.
この場合、ＦＥＴ８の塞板−ソース間のＰ−Ｎ接合、Ｆ
ＥＴ９の基板−ドレイン間のＰ−Ｎ接合がともに順方向
にバイアスされ、アースからこれらのＰ−Ｎ接合を通し
て、入力抵抗７、入力端子３の経路で導通状態となり、
節点４の電圧■４はＰ−Ｎ接合の順方向降下分だけＯよ
り低い値にクランプされる。従って、ＦＥＴ８のゲート
−ソース間にはＰ−Ｎ接合の順方向降下分（通常１ｖ以
下）しか加わらず、ドレイン−ゲート間にはＰ−Ｎ接合
の順方向降下分とＶ。０の和しか加わらない。In this case, the P-N junction between the plug plate and the source of FET8, F
Both the P-N junctions between the substrate and the drain of ET9 are biased in the forward direction, and the path from the ground through these P-N junctions to the input resistor 7 and the input terminal 3 becomes conductive.
The voltage 4 at node 4 is clamped to a value lower than O by the forward drop of the PN junction. Therefore, only the forward drop of the P-N junction (usually 1 V or less) is applied between the gate and source of the FET 8, and the forward drop of the P-N junction and V is applied between the drain and gate. Only the sum of 0 is added.
このことは、Ｖ３の値がいかに大きくてもあてはまる。This applies no matter how large the value of V3 is.
第２図にはまた■３＝−２０■の場合の■４．Ｖ５が示
されている。Figure 2 also shows ■4 when ■3=-20■. V5 is shown.
（発明の効果〕
以上のように本発明によれば正負いずれの高電圧が入力
端子に入力された場合にも、内部回路に印加される電圧
は電源電圧以下となる。また、入力保護回路内のいずれ
のＭＯＳＦＥＴにも、そのゲート−ドレイン、ソース間
にはほぼ電源電圧以下の電圧しか加わらないようにする
ことができる。(Effects of the Invention) As described above, according to the present invention, even if either positive or negative high voltage is input to the input terminal, the voltage applied to the internal circuit is equal to or lower than the power supply voltage. It is possible to apply only a voltage substantially less than the power supply voltage to any of the MOSFETs between the gate, drain, and source.
従って、ゲート酸化膜の破壊を避けることができる。ま
た、Ｐ−Ｎ接合のブレークダウンを利用していないので
、装置の寿命を縮めることがない。Therefore, destruction of the gate oxide film can be avoided. Furthermore, since breakdown of the PN junction is not utilized, the life of the device will not be shortened.
さらに、正の高電圧が入力されても、少数主１１リア（
ホール）が基板に注入されないため、ラッチアップが生
じない。Furthermore, even if a positive high voltage is input, the minority master 11 rear (
Since no holes (holes) are injected into the substrate, latch-up does not occur.
第１図は本発明の入力保護回路の一実施例を示す回路図
、第２図は第゛１図の回路の各節点の電圧を示す図、第
３図は従来の入力保護回路の一例を示す回路図、第４図
は第３図の回路の各節点の電圧を示す図である。
１・・・電源、３・・・入力端子、７・・・入力抵抗、
８．９−ｎ−チャンネルＭＯ８ＦＥＴ、１０−・・ｐ−
チャンネルＭＯ８ＦＥＴ。
出願人代理人 猪 股 清
■３
ら２ 口
色３ 図
島４ 図Fig. 1 is a circuit diagram showing an embodiment of the input protection circuit of the present invention, Fig. 2 is a diagram showing the voltage at each node of the circuit of Fig. 1, and Fig. 3 is an example of a conventional input protection circuit. The circuit diagram shown in FIG. 4 is a diagram showing voltages at each node of the circuit of FIG. 3. 1...Power supply, 3...Input terminal, 7...Input resistance,
8.9-n-channel MO8FET, 10-...p-
Channel MO8FET. Applicant's agent Kiyoshi Inomata 3 Ra 2 Mouth color 3 Zujima 4 Figure
Claims (1)
抵抗の他端に接続された第１導電形の第１のＭＯＳＦＥ
Ｔと、 ゲートが電源に接続された前記第１導電形の第２のＭＯ
ＳＦＥＴと、 一端が電源に接続され、他端が前記第２のＭＯＳＦＥＴ
のドレイン−ソース回路を介して前記抵抗の他端に接続
されると共に内部回路に接続された負荷素子とを備えた
入力保護回路。 ２、特許請求の範囲第１項記載の入力保護回路において
、前記負荷素子は、ゲートがアースに接続され、ドレイ
ンおよびソースが前記一端および他端を構成する第２導
電形のＭＯＳＦＥＴであることを特徴とする入力保護回
路。 ３、特許請求の範囲第１項または第２項に記載の入力保
護回路において、前記第１および第２のＭＯＳＦＥＴが
ともにｎチャンネルＭＯＳＦＥＴであり、その基板がア
ースに接続されていることを特徴とする入力保護回路。[Claims] 1. An input terminal, a resistor having one end connected to the input terminal, and a first conductivity type resistor having a drain connected to a power supply and a gate and a source connected to the other end of the resistor. 1 MOSFE
T, and a second MO of the first conductivity type whose gate is connected to a power supply.
SFET, one end connected to the power supply and the other end connected to the second MOSFET.
and a load element connected to the other end of the resistor via a drain-source circuit of the resistor and an internal circuit. 2. In the input protection circuit according to claim 1, the load element is a second conductivity type MOSFET whose gate is connected to ground and whose drain and source constitute the one end and the other end. Features an input protection circuit. 3. In the input protection circuit according to claim 1 or 2, the first and second MOSFETs are both n-channel MOSFETs, and the substrate thereof is connected to ground. input protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60117049A JPS61276249A (en) | 1985-05-30 | 1985-05-30 | Input protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60117049A JPS61276249A (en) | 1985-05-30 | 1985-05-30 | Input protective circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61276249A true JPS61276249A (en) | 1986-12-06 |
| JPH0244151B2 JPH0244151B2 (en) | 1990-10-02 |
Family
ID=14702157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60117049A Granted JPS61276249A (en) | 1985-05-30 | 1985-05-30 | Input protective circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61276249A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6439118A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Gaas semiconductor integrated circuit |
| JPH0329361A (en) * | 1989-06-26 | 1991-02-07 | Nec Corp | Semiconductor device |
| JPH05267658A (en) * | 1992-02-19 | 1993-10-15 | Nec Corp | Cmos semiconductor integrated circuit |
| JP2002076282A (en) * | 2000-08-30 | 2002-03-15 | Nec Corp | Semiconductor integrated circuit device and design method thereof |
| JP2003504860A (en) * | 1999-06-29 | 2003-02-04 | コックレア リミティド | High voltage protection circuit of standard CMOS process |
| EP0666596B1 (en) * | 1994-02-03 | 2003-05-14 | Infineon Technologies AG | Protection apparatus for series pass MOSFETs |
-
1985
- 1985-05-30 JP JP60117049A patent/JPS61276249A/en active Granted
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6439118A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Gaas semiconductor integrated circuit |
| JPH0329361A (en) * | 1989-06-26 | 1991-02-07 | Nec Corp | Semiconductor device |
| JPH05267658A (en) * | 1992-02-19 | 1993-10-15 | Nec Corp | Cmos semiconductor integrated circuit |
| EP0666596B1 (en) * | 1994-02-03 | 2003-05-14 | Infineon Technologies AG | Protection apparatus for series pass MOSFETs |
| JP2003504860A (en) * | 1999-06-29 | 2003-02-04 | コックレア リミティド | High voltage protection circuit of standard CMOS process |
| JP4763192B2 (en) * | 1999-06-29 | 2011-08-31 | コクレア リミテッド | Standard CMOS process high voltage protection circuit |
| JP2002076282A (en) * | 2000-08-30 | 2002-03-15 | Nec Corp | Semiconductor integrated circuit device and design method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0244151B2 (en) | 1990-10-02 |
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