JPS6191964A - MOS field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Tumor Application] The present invention is directed to a MOS@field effect transistor (hereinafter, M
This relates to the gate/magnetic pole structure of OSFET.

[Conventional technology]

Conventionally, the gate electrode of MOIIT has been formed in a planar manner, or in other words, as a two-dimensional structure existing in a planar manner between a source and a drain.

[Problem that the invention seeks to solve]

Such a structure requires a high mutual inductance (hereinafter referred to as pm), MOf! (
FET (1) t9 In is mrfR of the gate electrode
Since it is determined by geometric dimensions such as height and length, a large area is required, and a large 9m is required for MOSFE.
This has been an obstacle to miniaturization, higher integration, and smaller chips in T ICs and LSIs.

Also, because it has a two-dimensional structure, carriers (mobile charges) passing through the channel formed directly under the gate electrode are also 2-dimensional.
Due to dimensional constraints, the actual mobility of carriers (velocity of gear in unit electric field: ease of movement) in the substrate directly under the gate electrode (relative to the surface) is easy
! JJIfL could not be realized.

[Failure to solve the problem]

According to the present invention, the semiconductor substrate between the source region and the drain region is formed into an arch shape, and a gate opening is formed on the semiconductor substrate.
Obtain OSFET.

[Effect]

The gate electrode between the source and drain electrodes is arch-shaped, so a larger effective area can be obtained even with a small planar area, resulting in high gmt* with a smaller occupied area.
It is possible to obtain a MOSFET that can achieve high integration when applied to an IC or the like.

〔Example〕

This will be explained below using the drawings.

As shown in FIG. 3, in a conventional MOSFET, a source region 4 and a drain region 5 are formed on a semiconductor substrate 3 having a main surface, and a planar region is formed on the semiconductor substrate 3 between the source and drain regions 4 and 5. A gate oxide film 2 and a gate electrode 1 were formed thereon.

Therefore, the area of the gate electrode 1 is uniquely determined by the area between the source and drain regions 4 and 5, and in order to increase the height to 11 m, the area between the source and drain regions 4 and 5 must be increased to reduce the area occupied by both. Growth was inevitable.

In addition, since the movable charges under the gate electrode image 1 move in a two-dimensionally constrained region by the electric field, the speed is only about half that of the upper part of the semiconductor substrate 3, making it possible to operate at higher speeds. M (J8FET was not obtained.

Figure i1 shows an embodiment of the present invention, in which the source region 4
The semiconductor substrate 3 between the drain region 5 and the drain region 5 is provided with trapezoidal trenches on both sides. The gate oxide film 2 is provided in an arch shape on the surface of the trapezoidal portion, and the gate electrode 1 is also provided in an arch shape on the gate oxide film 2.

According to this embodiment, the effective gate area can be increased without requiring much planar area for the side portions of the arched gate electrode 1. Therefore, a high pm MOSFET can be obtained with a smaller planar area, the aperture occupied by the element on the semiconductor substrate can be reduced, and the integration density can be increased.

Next, the manufacturing method of this embodiment will be explained with reference to FIGS. 2(a) to 2(e).

First, as shown in FIG. 2A, a nitride film 6 is deposited on a semiconductor substrate 3, and the nitride film is removed by etching, leaving the gate portion.

Next, as shown in FIG. 3B, an oxide film 7 is grown on the semiconductor substrate 3. At this time, both sides of the gate section are dug down in an oxidation process.

Next, by removing the nitride film 6 and the oxide film 7, two grooves are formed on the semiconductor 3, as shown in FIG.

Furthermore, a field oxide film 8 is formed by field oxidation, and through an etching process and a gate oxidation process, as shown in FIG. form.

In this way, by depositing gate electrode metal on this, an arch-shaped gate electrode 1 as shown in FIG. 2(e) is formed.

Thus, according to one embodiment of the present invention, the gate electrode 1
By forming the gate electrode 1 in an arch shape, the gate electrode 1 is inclined in the gate width direction, and the gate hinge forms a three-dimensional space.
The channel can be placed under three-dimensional constraints similar to those in the semiconductor substrate 3.

In this three-dimensional space, minority carriers are induced by electric fields from two directions, so the channel is concentrated here, and the carriers pass through the three-dimensional space, and the magnetic flux is the same as that of the semiconductor substrate. The value is equivalent to 3, and the height is 11m.
can be realized.

Furthermore, it has an inclination in the width direction.

The area occupied is also reduced, and a high IIm can be achieved without requiring planar expansion.

[Effects of the Invention] “The present invention bends the gate in the width direction to form an arch-shaped gate electrode structure, thereby (1) reducing the area occupied by the transistor on an IC or LSI chip, and (2) 3 By forming a channel with dimensional expansion, it is possible to realize a high Im and a high amplifier, which not only makes it easy to apply to linear circuits.
Since it occupies a smaller area, it is also possible to realize high-density semiconductor devices such as ICs and LSIs.

[Brief explanation of the drawing]

Fig. 1 is a perspective view showing one embodiment of the present invention, and Fig. 2 is a perspective view showing an embodiment of the present invention.
A sectional view showing a manufacturing method of the embodiment shown in the order of manufacturing steps,
FIG. 3 is a perspective view of a conventional MO8 field effect transistor. DESCRIPTION OF SYMBOLS 1... Gate electrode, 2... Gate oxide film, 3... Semiconductor substrate, 4... Source region, 5... Drain region , 6... Nitride film, 7... Oxide film, 8... Field oxide film. 1911 Shi no Figure deceased) exposed i2 3 figure

Claims (1)

[Claims] A MOS field effect transistor having a gate electrode between a source region and a drain region, the cross section of which is perpendicular to the direction connecting the source region and the drain region is arch-shaped.