JPH01276669A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device that constitutes a MOS type transistor, and is particularly used in a MOS integrated circuit.

(Prior Art) This type of conventional semiconductor device has an M as shown in FIG.
OS)' transistor structure was used.

Here, 1 is a semiconductor substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is a source or drain region, and 5 is a field insulating film.

(Problems to be Solved by the Invention) In the above-mentioned conventional technology, a planar channel MOS transistor ellipse as shown in FIG. 3 is used, so when driving a large current, the transistor size must be increased. In addition, a strong electric field acts in the direction perpendicular to the channel plane between the substrates 1, t, and fi2, which causes problems in the mobility of electrons (carriers) between the source and drain. becomes small, making it difficult to draw large currents. Furthermore, when a fine transistor is formed, a narrow channel effect becomes a problem. In other words, in the case of m-thinning, since the channel width W becomes small, there is a problem that the anti-inversion layers under the field insulating film 5.5 are too close to each other, resulting in an increase in the threshold voltage.

The present invention was made in order to solve the problems that arose when trying to achieve high integration with a conventional transistor structure, and aims to increase the drive current of the transistor and improve the transistor characteristics.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a semiconductor device constituting a MOS transistor, the first feature of which is that the semiconductor substrate under the gate electrode has a convex shape. do. A second feature of the present invention is that the three surfaces of the convex top surface and both side surfaces of the semiconductor substrate below the gate electrode serve as channel regions. Further, in the present invention, the semiconductor substrate under the gate electrode has a convex strip, and the side surface of the convex strip of the semiconductor substrate is
It is characterized in that the direction is parallel to the direction of electrons flowing between the drain and source of the MOS transistor or the direction of the genuine tag.

That is, the present invention increases the drive current in a fine transistor and improves the transistor characteristics by forming the gate in a MOS type transistor structure in a raised shape on the topmost semiconductor substrate.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a perspective view of the MOS transistor showing the main parts of the same embodiment, but since this is an example in which it corresponds to that in Figure 3, corresponding parts will be given the same reference numerals and explained. This will be omitted and the characteristic points will be explained. Namely, in this MOS transistor, the semiconductor substrate under the gate electrode has a convex shape (convex strip), and the upper surface and both side surfaces of the convex portion 11 are covered with the gate insulating film 3. A gate electrode 2 is formed so as to straddle the convex portion 11, and the convex portion 1 surrounded by the gate electrode 2 becomes a channel region.
Place the sauce on the protrusions 11 on both sides.

Train 4 is formed. In this case, the carrier (@ child or genuine bill) flows in the vertical direction of the convex portion 11 .

Next, a method for manufacturing a transistor according to this embodiment will be explained. First, as shown in FIG. 2(a), for example, a P-type S1 single crystal substrate 1
A 500-layer 8102 film 10 is formed on the top by hydrogen combustion oxidation at 950° C., a 2,500-layer SiN film 11 is deposited by a chemical vapor phase method, and the above-mentioned S t N 11l in the element isolation region is deposited by a lithography technique. Cover the rest with resist,
The SiN film and 5102M in the element isolation region are
After performing RIE on the SL single crystal substrate 1, the resist is removed.

Next, as shown in FIG. 2(b), a 500 SiOZ film 12 was formed by hydrogen combustion oxidation at 950°C, and a 1000 SiN film 13 was further deposited by chemical vapor deposition. The SiN film 13 is removed by RIE. At this time, R
Since the SiN film 13 is removed by anisotropic etching using IE, the SiN film 13 remains on the rfIJW of the convex portion 11 of the SL single crystal substrate. And this SIN film 11.1
Using 3 as an oxidation mask, 5000 field acid films 5 are formed by hydrogen combustion oxidation.
111°13 CDE (Chemical Dry
EtChin! +) and 5LO2fi10°12 with NH4F solution. Then, by heat-treating the gate insulation M3 of the MOS transistor at 900°C in a dry oxygen atmosphere containing 10% HCj,
Form 300 people. Then, as a gate electrode, 4000 polycrystalline Si WA2 was deposited by chemical vapor deposition method, and 900'C, P was deposited to reduce the resistance of the gate electrode.
oCj 3. Perform phosphorus diffusion for 30 minutes. Next, using phosphorography technology, the gate tf! The polycrystalline Si film 2 is removed by RIE, and the resist is removed to obtain the structure shown in FIG. 1. Thereafter, using a well-known technique, a source is placed in the region sandwiching the gates t&2 in the convex portion 11 of FIG.
Form the drain 4 and attach it as shown in Fig. 2(d).
After forming 4 and 15, wiring is performed using A1 alloy 16 to form an integrated circuit.

With the above configuration, a channel region can also be formed in the vertical direction (height direction), so when driving a large current,
High integration can be achieved without increasing the planar transistor size. In other words, the channel region can be widened with a small planar area, the transistor size can be substantially increased, and a large current can be driven. In addition, in the configuration shown in FIG. 1, an electric field is generated not only on the upper surface of the convex part 11 but also in the horizontal direction on both sides of the convex part 11, so as can be seen by vector synthesis, the vertical electric field is relaxed. It becomes easier to obtain large current. Actually, the convex portion 11 in the area surrounded by the gate electrode 2
The electric field is most relaxed when the entire structure is made into an inversion layer. Also, since the upper part and both sides of the convex part 11 form a channel @W,
As the channel width increases, the noise during the narrow channel effect decreases.

[Effects of the Invention] As explained above, according to the present invention, it is possible to miniaturize the area of an integrated circuit, and when this miniaturization is carried out, it is possible to increase the drive current of the transistor and improve the transistor characteristics.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of essential parts of an embodiment of the present invention, FIG. 2 is a manufacturing process diagram of the same embodiment, and FIG. 3 is a perspective view of a conventional device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 11... Convex part (convex strip), 2...
- Gate electrode, 3... Gate insulating film, 4... Source or drain region, 5... Field oxide film. Applicant's agent Patent attorney Takehiko Suzue ζ Figure 1 Figure 3 Figure 2 1

Claims (3)

[Claims] (1) A semiconductor device constituting a MOS transistor, characterized in that a semiconductor substrate under a gate electrode has a convex shape. (2) The semiconductor device according to claim 1, wherein three surfaces of the semiconductor substrate having a convex shape below the gate electrode, including the top surface and both side surfaces, serve as channel regions. (3) The semiconductor substrate under the gate electrode has a protruding strip, and the side surface of the protruding strip of the semiconductor substrate is in a direction parallel to the direction of electrons flowing between the drain and source of the MOS transistor or the direction of the genuine tag. Claim 1 characterized in that
Or the semiconductor device according to 2.