JPS6142163A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6142163A JPS6142163A JP16405584A JP16405584A JPS6142163A JP S6142163 A JPS6142163 A JP S6142163A JP 16405584 A JP16405584 A JP 16405584A JP 16405584 A JP16405584 A JP 16405584A JP S6142163 A JPS6142163 A JP S6142163A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- layer
- semiconductor device
- well layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明社バイポーラトランジスタと接合形電界効果トラ
ンジスタとが混載する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device in which a bipolar transistor and a junction field effect transistor are mounted together.
（従来の技術）
従来、同一の半導体基板上にバイポーラトランジスタ（
Ｂ、−Ｔｒ）とＮチャンネルの接合形電界効果トランジ
スタ（ＮチャンネルＪ−ＦＥＴ）とを形成する製造方法
において、ＮチャンネルＪ−ＦＥＴのチャンネル部を形
成するのにイオン注入技術が利用されている。(Prior art) Conventionally, bipolar transistors (
In a manufacturing method for forming an N-channel junction field effect transistor (N-channel J-FET) with B, -Tr), ion implantation technology is used to form the channel portion of the N-channel J-FET. .
（発明が解決しようとする問題点）
ところが、チャンネル部の形成にイオン注入技術を用い
た従来の製造プロセスでは、Ｂ＋−５Ｔｒの製造プロセ
スに、ＮチャンネルＪ−ＦＥＴのチャンネル部の製造プ
ロセスが付加されるため、製造工程が増加するという問
題があった。(Problems to be Solved by the Invention) However, in the conventional manufacturing process that uses ion implantation technology to form the channel portion, the manufacturing process for the channel portion of the N-channel J-FET is added to the manufacturing process for the B+-5Tr. Therefore, there was a problem in that the number of manufacturing steps increased.
（問題点を解決するための手段）
本発明に係る半導体装置の製造方法は、Ｎ型エピタキシ
ャル層にＰ型ウェル層を形成し５該Ｐ型ウ工ル層の表面
部分の二カ所にＮ＋デポジット層の形成した後、チャン
ネル部となるＰ型ウェル層の表面の酸化膜を除去する工
程と、該酸化膜を除去した後、前記Ｎ＋デポジット層の
表面および前記チャンネル部となるＰ型ウェル層の表面
全体を酸化し、Ｎ＋デポジット層のドライブインを行っ
て接合形電界効果トランジスタのソース領域およびドレ
イン領域を形成すると同時に、Ｐ型ウェル層の表面にチ
ャンネル部を形成する工程とを備えているものである。(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes forming a P-type well layer on an N-type epitaxial layer, and depositing N+ deposits at two locations on the surface of the P-type well layer. After forming the layer, there is a step of removing an oxide film on the surface of the P-type well layer that will become the channel part, and after removing the oxide film, a step of removing the oxide film on the surface of the N+ deposit layer and the P-type well layer that will become the channel part. A method comprising the steps of oxidizing the entire surface and driving in the N+ deposit layer to form the source region and drain region of the junction field effect transistor, and at the same time forming a channel portion on the surface of the P-type well layer. It is.
（作用）
本発明に係る半導体装置の製造方法は、ＮチャンネルＪ
−ＦＥＴのチャンネル形成を、＃Ｉ化による不純物の再
分布作用を活用することにより、ソース領域およびドレ
イン領域の形成と同時に行うことができる。(Function) The method for manufacturing a semiconductor device according to the present invention includes an N-channel J
- The channel formation of the FET can be performed simultaneously with the formation of the source region and the drain region by utilizing the redistribution effect of impurities due to #I conversion.
（実施例）
本発明に係る半導体装置の製造方法を第１図（１）〜（
６）に示す。(Example) A method for manufacturing a semiconductor device according to the present invention is illustrated in FIGS.
6).
（１）Ｐ型Ｓ正基板１上にＮ型エピタキシャル成長を行
ってＮ型エピタキシャル層２を形成し、該Ｎ型エピタキ
シャル層２に、Ｐ−ウェル層４を形成する。３はＳｉ’
０２膜である〔第１図（１）〕。(1) N-type epitaxial growth is performed on a P-type S positive substrate 1 to form an N-type epitaxial layer 2, and a P-well layer 4 is formed on the N-type epitaxial layer 2. 3 is Si'
02 film [Figure 1 (1)].
＋２１ Ｓ ｒ ＯＺ膜３をホトレジスト処理し、Ｂ
等をデポジット・拡散してＮチャンネルＪ−ＦＥＴのゲ
ート電極取出し用となるＰ゛ゲートコンタクト拡散領域
５を形成する〔第１図（２）〕。このＰ゛領域の形成は
９図示はしないが、Ｂ、−Ｔ、のベース拡散領域の形成
と同時に行われる。+21 S r OZ film 3 is subjected to photoresist treatment, and B
and the like are deposited and diffused to form a P gate contact diffusion region 5 for taking out the gate electrode of the N-channel J-FET [FIG. 1(2)]. Although not shown in FIG. 9, the formation of the P region is performed at the same time as the formation of the base diffusion regions B, -T.
（３） ホトエツチングにより、将来ＮチャンネルＪ
−ＦＥＴのソース領域およびドレイン領域となる部分６
．７のパターニングを行う〔第１図（３）〕。このバタ
ーニングは、Ｂ、−Ｔ、のエミッタ領域およびコレクタ
コンタクト領域となる部分のパターニングと同時に行わ
れる。(3) By photo-etching, future N-channel J
- Portion 6 that becomes the source region and drain region of the FET
．． 7 patterning is performed [Figure 1 (3)]. This patterning is performed simultaneously with the patterning of the portions that will become the emitter regions and collector contact regions of B, -T.
（４） ソース領域およびドレイン領域となる部分６
゜７に、Ｐ、Ａｓ等をデポジットしてＮ＋デポジット層
の８９を形成する〔第１図（４）〕。これは。(4) Portion 6 that will become the source region and drain region
At step 7, P, As, etc. are deposited to form an N+ deposit layer 89 [FIG. 1 (4)]. this is.
Ｂ、−Ｔ、のエミッタ領域となる部分に、Ｐ。P in the part that will become the emitter region of B, -T.
Ａ８等をデポジットするのと同時に行われる。This is done at the same time as depositing A8 etc.
＋５１ Ｎ”デポジット層８．９の形成を完了した後
。+51 N” after completing the formation of deposit layer 8.9.
通常のホトエツチングによってチャンネル部となるＰ−
ウェル層４上の５ｉ０２膜３を除去する〔第１図（５）
〕。P- becomes the channel part by normal photoetching.
Remove the 5i02 film 3 on the well layer 4 [Fig. 1 (5)
].
（６） 前記Ｎ゛デポジツトｅｌｆ域、９の表面およ
びチャンネル部となるＰ−ウェル層の表面全体の酸化１
０を行う。この酸化、すなわちドライブインによって、
ＮチャンネルＪ−ＦＥＴのＮ３ソース拡散領域１１およ
びＮ°ドレイン拡散領域１２を形成する。このとき、酸
化による不純物の再分布により、Ｐ−ウェル層４の表面
に反転層、すなわち低濃度領域のＮ−チャンネル１３が
形成される〔第１図（６）〕。この、チャンネル部とな
るＰ−ウェル層の表面の酸化は、Ｂ、−Ｔ、のエミッタ
領域を形成するドライブインと同時に行われる。(6) Oxidation 1 of the entire surface of the N-deposit region 9 and the P-well layer that will become the channel part.
Do 0. This oxidation, or drive-in,
An N3 source diffusion region 11 and an N° drain diffusion region 12 of an N-channel J-FET are formed. At this time, due to the redistribution of impurities due to oxidation, an inversion layer, that is, an N-channel 13 in a low concentration region is formed on the surface of the P-well layer 4 [FIG. 1(6)]. This oxidation of the surface of the P-well layer, which will become the channel portion, is performed at the same time as the drive-in forming the B, -T, emitter regions.
このように１本発明の半導体装置の製造プロセスにおけ
るＮ−チャンネルの形成は、Ｎ＋ソース拡散領域および
Ｎ゛ドレイン拡散領域の形成と同時に行われる。In this manner, the formation of the N-channel in the manufacturing process of the semiconductor device of the present invention is performed at the same time as the formation of the N+ source diffusion region and the N'' drain diffusion region.
（発明の効果）
以上説明したように１本発明の半導体装置の製造方法に
よれば、ＮチャンネルＪ−ＦＥＴのチャンネル形成を酸
化による不純物の再分布作用を活用することにより、Ｂ
、−Ｔ、の製造プロセスに合わせて行うことができるか
ら、従来のイオン注入技術を利用した製造方法に比べて
製造工程を短縮することができ、しかもトランジスタ特
性等に影響を与えることなくＢｉ−Ｔ、とＮチャンネル
Ｊ−ＦＥＴを同一基板上に形成することができる。(Effects of the Invention) As explained above, according to the method of manufacturing a semiconductor device of the present invention, channel formation of an N-channel J-FET is achieved by utilizing the redistribution effect of impurities caused by oxidation.
, -T, can be performed in accordance with the manufacturing process of Bi- T, and N-channel J-FETs can be formed on the same substrate.
第１図（１）ないしく６）は半導体装置の本発明に係る
製造工程を示す概略断面図である。
１・・・Ｐ型Ｓ、基板
２・・・Ｎ型エピタキシャル層
３・・・Ｓ、Ｏ□膜
４・・・Ｐ ウェル層
５・・・Ｐ゛ゲートコンタクト拡散領域１１・・・Ｎ“
ソース拡散領域
１２・・・Ｎ“ドレイン拡散領域
１３・・・Ｎ−チャンネル
ほか１名
第７図FIGS. 1(1) to 16) are schematic cross-sectional views showing the manufacturing process of a semiconductor device according to the present invention. 1...P type S, substrate 2...N type epitaxial layer 3...S, O□ film 4...P well layer 5...P'gate contact diffusion region 11...N''
Source diffusion region 12...N Drain diffusion region 13...N-channel and one other person Figure 7
Claims (1)
スタとが混載する半導体装置を製造する方法であって、 Ｎ型エピタキシャル層にＰ型ウェル層を形 成し、該Ｐ型ウェル層の表面部分にＮ＾＋デポジット層
を形成した後、チャンネル部となるＰ型ウェル層の表面
の酸化膜を除去する工程と、 該酸化膜を除去した後、前記Ｎ＾＋デポジット層の表面
および前記チャンネル部となるＰ型ウェル層の表面全体
を酸化し、前記Ｎ＾＋デポジット層のドライブインを行
って接合形電界効果トランジスタのソース領域およびド
レイン領域を形成すると同時に、Ｐ型ウェル層の表面に
チャンネル部を形成する工程とを備えていることを特徴
とする半導体装置の製造方法。[Claims] 1) A method for manufacturing a semiconductor device in which a bipolar transistor and a junction field effect transistor are mounted together, the method comprising: forming a P-type well layer on an N-type epitaxial layer; After forming an N^+ deposit layer on the part, removing an oxide film on the surface of the P-type well layer that will become the channel part; After removing the oxide film, forming the N^+ deposit layer on the surface of the N^+ deposit layer and the channel. oxidize the entire surface of the P-type well layer, which will serve as the base layer, and drive-in the N^+ deposit layer to form the source and drain regions of the junction field effect transistor.At the same time, a channel is formed on the surface of the P-type well layer. 1. A method of manufacturing a semiconductor device, comprising the step of forming a portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16405584A JPS6142163A (en) | 1984-08-04 | 1984-08-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16405584A JPS6142163A (en) | 1984-08-04 | 1984-08-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6142163A true JPS6142163A (en) | 1986-02-28 |
Family
ID=15785928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16405584A Pending JPS6142163A (en) | 1984-08-04 | 1984-08-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142163A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5188978A (en) * | 1990-03-02 | 1993-02-23 | International Business Machines Corporation | Controlled silicon doping of III-V compounds by thermal oxidation of silicon capping layer |
| KR100344218B1 (en) * | 1995-09-14 | 2002-11-08 | 페어차일드코리아반도체 주식회사 | High density well manufacturing method of semiconductor device |
-
1984
- 1984-08-04 JP JP16405584A patent/JPS6142163A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5188978A (en) * | 1990-03-02 | 1993-02-23 | International Business Machines Corporation | Controlled silicon doping of III-V compounds by thermal oxidation of silicon capping layer |
| KR100344218B1 (en) * | 1995-09-14 | 2002-11-08 | 페어차일드코리아반도체 주식회사 | High density well manufacturing method of semiconductor device |
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