JPS6184981A - Scanning converting device - Google Patents

Abstract

PURPOSE:To make good scanning converting operation for an inputted signal and to store video signals in a memory by detecting the ratio of vertical scanning time to horizontal scanning time of inputted video signals of interlaced scanning system. CONSTITUTION:TV video signals (g) that make demodulated and interlaced scanning are A/D converted and inputted to a memory 2. A horizontal synchronizing signal (l) and a vertical synchronizing signal (k) are outputted from the video signals (g) by a synchronizing separator circuit 4, and the two synchronizing signals (l), (k) are applied to a controlling circuit 8. The ratio of vertical and horizontal synchronizing times is calculated by the circuit 8, and a signal (r) that changes the mode of the operation of the device 2 is applied from the circuit 8 to an address generator 7. The synchronizing signal l is added to a PLL circuit 5, and coincidence with an internal synchronizing signal (s) from the generator 7 is detected. Basic clock (m) of the systems is added to a counter 6, and an R/W signal from the counter is added to the device 2. An output signal (p) from the counter 6 is added to the generator 7, and address information (o) from the generator 7 is added to the device 2. Thus, scanning converting operation of video signals (g) is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention is capable of reproducing high-resolution images by doubling the number of scanning lines of one field of television signals by interpolating between scanning lines. The present invention relates to a scan conversion device.

(b) Conventional technology Interpolation between the scanning lines of a television video signal using an interlaced scanning method is performed using interpolation No. 15, the field frequency is the same as that of the interlaced scanning method, and the number of scanning lines is doubled, resulting in a high-resolution image. For example, a scan converter for obtaining
It is described in Figure 4 of Publication No. 73.

Storage device (14>(
15) are for delaying the signals by 262 horizontal scanning periods and 263 horizontal scanning periods, respectively, and perform only certain operations depending on the relationship between the vertical scanning period and horizontal scanning period of the input television video signal. It is.

In addition, the applicant has previously applied for Tokkyo 59-1658
The scan conversion device proposed in No. 21 is also designed to operate a storage device using 263 horizontal scanning periods as one operation cycle.

In these conventional devices, the expected standard format of the input video signal (for example, in the current NTSC format, one vertical scanning period is formed by 262.5 horizontal scanning periods)
Accordingly, the operation mode of the storage device is set fixedly. However, it cannot be said that video equipment other than video equipment that receives broadcast television video signals necessarily generates standard format video signals.

For example, compared to the standard method, one vertical scanning period is formed by 255 to 270 horizontal scanning periods in the playback video signal during special playback (fast forward or slow playback) of a video tape recorder, and therefore, the storage Conventional scan conversion devices that operate in a fixed manner have the disadvantage that good scan conversion cannot be performed.

(c) Problems to be Solved by the Invention In the present invention, as described above, a good scan conversion operation is performed even for a non-standard input video signal that deviates from the standard format.

2) Means for solving the problem Means for detecting the ratio between the vertical scanning period and the horizontal scanning period of the input video signal of the interlaced scanning method and controlling the storage device that stores the video signal information according to this ratio. has been established.

(E) Operation With the above configuration, the storage device operates at a cyclic cycle adapted to each of the standard and non-standard methods.

(f) Embodiment FIG. 5 is a block circuit diagram showing a schematic configuration of a scan conversion device of the present invention, in which a demodulated television video signal (g> is an A/D converter) which performs 2:1 interlaced scanning. (Analog-digital converter) (1) converts the diptal signal (
It is converted into h+ and is a device composed of semiconductors, ``lmory, etc.''.

This storage device (2) stores the image input to the A/D converter (1). If N is the smallest integer larger than the ratio of the vertical scanning period and horizontal scanning period of the signal (g), then N line 2
Counter (6)
A write/read operation control signal (hereinafter referred to as 'F') given from
``LAW signal'')《n) and address generator (7》)
It is controlled to perform write/read operations as described later by address information 'ffl(o) given from . From the memory bag #(2), the information (i
) is a D/A converter (digital-to-analog converter) (3
) can be converted to analog video official name (j), CRT
etc. (fii<rA not shown).

On the other hand, the input video signal (g) is given to the synchronization separation circuit (4), where each vertical synchronization signal is separated, and the horizontal synchronization signal (g) is sent to a phase-locked loop including a phase comparator and a voltage-controlled oscillator. The PLL circuit (PLL) (5) is configured such that the internal synchronization signal (S) outputted from the address generator (7) matches the phase with the horizontal synchronization signal (<1). 5), and as a result, the PLL circuit (5) forms a signal (m) that is the basic lock of this system. This clock signal (m) is given to the counter (6); ) generates the above-mentioned R/W signal (n).The force counter (
The output signal (p) of 6) is given to an address generator (7), which generates the address information (o) and an internal synchronization signal (S) based on this signal (p). At the same time, a horizontal deflection synchronization signal (q) used to horizontally deflect the output video signal is supplied to a horizontal deflection device (not shown). Note that this synchronization signal (q) can be set to twice the frequency of the internal synchronization signal (s).

The vertical synchronization signal (k
) is supplied to a vertical deflection circuit (not shown) and is given as one input of a control circuit (8). This control circuit (8) receives the vertical synchronization signal (k) and horizontal Based on the synchronization signal (1), 1
The ratio between the vertical scanning period and one horizontal scanning period is calculated, and a signal (r) instructing a change in the operation mode of the storage device (2) is supplied to the address generator (7) according to the value of this ratio. The address generator (7) changes the address information as described later by the signal (r), thereby changing the cycle period of the storage device (2).

Next, referring to FIGS. 1 and 2, the storage device (2)
The operation will be explained.

In FIGS. 1 and 2, (a) schematically shows a video signal waveform transmitted in a 2:1 interlaced scanning method, and a period H is one horizontal scanning period in the interlaced scanning method, and a period V indicates one vertical scanning period, Hs indicates a horizontal synchronization signal, and Vs indicates a vertical synchronization signal. (B) is a diagram showing the operation timing of the storage device, and the solid line shown with a bold line indicates the writing time of the storage device. The timing is shown, and the dashed line shows the timing of readout. Also, in the 1st ryJ (a), the ratio of the vertical scanning period to the horizontal scanning period is 7.5:1, as shown in Figure 2 (
In b), the ratio of the vertical scanning period to the horizontal scanning period is 8.
The waveform near the vertical synchronization signal has been significantly simplified, but it has been selected to be extremely small at 5:1.
Satisfies interlaced scanning conditions.

In the following, the case of FIG. 1 will be explained as an operation when a standard format video signal is input, and the case of FIG. 2 will be explained as an operation when a non-standard format video signal is input.

Vertical synchronization number 18 (k
> and the horizontal synchronization signal (1), the ratio of the vertical scanning period to the horizontal scanning period is calculated, and when it is detected that the standard method is used (in this case, the value of the ratio is 7.5), the control circuit (8) Signal (r) sent to address generator (7)
Assuming that the smallest integer larger than the ratio of the vertical scanning period and the horizontal scanning period is N (in this case, 18''), the addresses for 8 lines of the storage device are cycled through, and each one of each field of the input video signal is It is controlled by the address generator (7) to sequentially write video signal information for lines.

On the other hand, the read operation of the storage device (2) is performed at T in FIG. (−
Taking the LH) period as an example, this period T. While writing the video signal information for IH (H: 1 horizontal scanning period in interlaced scanning) called C' of the first field existing in the address of one line of the storage device (2), the address of this one line is written. The previous field already written to (
The video signal information for IH b of the second field) is read out at +H in the first half, and subsequently written at the corresponding period T0.
The video signal information ' is read out with the latter sound H. Each reading at this time is performed at twice the writing speed. Since the storage device can be controlled so that such an operation is repeated, for example, No. 18 read in the T1 period becomes b-c'-c-d'-d-e', and has two fields. The signal of each line is read out alternately every +H and compressed on the time axis, so that the field frequency is the same as in the interlaced scanning method and the number of lines is doubled (in other words, the number of lines can be converted) (progressive scanning method) This means that it is possible to obtain two television video signals.

In this way, @the ratio of the direct scanning period and the water motion scanning period is 7.5.
In the case of 21, scan conversion is preferably performed by circulating the storage device with addresses for 8 lines as one cycle period, but the ratio of the vertical scanning period to the horizontal scanning period is 8.5:1.
If such a change occurs, proper scan conversion will not be possible, but the control circuit (8) detects the ratio of the vertical scanning period to the horizontal scanning period based on the vertical synchronizing signal (k) and the horizontal synchronizing signal (1). Then, the fg number (r) is sent to the address generator (7), and the memory device (2) is circulated using nine lines of addresses as one cycle period. FIG. 2 shows a case where the cyclic period is set accordingly, and as in the case of FIG. 1, the signal read out during the T2 period is b-c'-c-
d'-d7e', and it can be seen that scan conversion is performed appropriately.

Incidentally, in the case described above, scan conversion can be performed satisfactorily, but it requires a large storage capacity.6For example, in the current standard NTS C system, one vertical scanning period, The scan period ratio is 262.5
: 1, so 263 plus 12 addresses are required, and if you try to avoid applying it to a non-standard method, you will need more addresses than that, which means that the storage device itself will become larger. Furthermore, the liI[i rating constituting the scan conversion device also becomes high.

Next, another embodiment of a scan conversion device that eliminates such drawbacks will be described with reference to FIGS. 3, 4, and 6. The storage device (2) in FIG. Since the parts other than the configuration of the control circuit (8) and the control circuit (8) are the same, FIG. 5 will be used as is for explanation. And the storage device (
The address 2) is assumed to be capable of storing six lines of video signal information, and the control circuit (8) is configured as shown in FIG. A detailed explanation of the operation of this control circuit will be described later, but the ratio of the vertical scanning period to the horizontal scanning period is counted from the vertical synchronizing signal and the horizontal synchronizing signal, and from this count value, the storage device ff(2 ), and generate a control signal at a timing near the vertical synchronization signal to stop the step operation of the address generator (7) for a predetermined period so as to match this cycle period. It has become.

3 and 4 are diagrams for explaining the operation of the storage device (2) in this embodiment, and in each of these diagrams (a)
v2.2, which is transmitted using the 221 interlaced scanning method. The period H is an upper horizontal scanning period in the interlaced scanning method, the period V is one vertical scanning period, Hs is a horizontal synchronizing signal, and Vs is a vertical synchronizing signal. )
is a diagram showing the operation timing of the storage device, where the solid line shown in bold indicates the write timing of the storage device,
The dashed line indicates the timing of the readout, and the thick solid line drawn parallel to the time axis indicates that the address generator has stopped running and the increment of addresses in the storage device has stopped.

In addition, the ratio of the vertical scanning period to the horizontal scanning period in Figure 3 (a) is 75:1, and the ratio of the vertical scanning period to the horizontal scanning period in Figure 4 (a) is 85:1, which is very small. Although the waveform near the vertical synchronization signal is significantly simplified, it still satisfies the H.221 interlaced scanning condition.

In the following, the case of FIG. 3 will be explained as an operation when a standard format video signal is input, and the case of FIG. 4 will be explained as an operation when a non-standard format video signal is input.

To explain the operation of the control circuit shown in detail in FIG. 6,
The vertical synchronization signal (k) is a toggle flip-flop (T-
FF) (9), and the T-FF (9) generates a pulse (a) having a frame period of the input video signal (g).

This pulse (A) is applied to the first delayed flip-flop (1st D-FF) (10), and the first delayed flip-flop (10)
By being added to the AND gate (11) together with the output signal (B) of F F (10), the frame period "
It is converted into a narrow pulse of tJ.1. This middle pulse is the first pulse.
It is used as a reset signal (c) for the counter (12). The first counter (12) calculates the cycle period (
In other words, it is a counter that counts 12, which is twice the number 162 of horizontal synchronizing signals (1) present in 6H), which is the period in which the address is incrementing in one cycle of the storage device, and is a full count. This is a self-recovery counter that is automatically initialized depending on the state. The first counter (12) of the second counter (12) is reset immediately before the counter (12) is reset by the reset signal (c).
is memorized. Therefore, in the case of the input video signal shown in FIG. 3, there are 15 horizontal synchronizing pulses in one frame period (two vertical scanning periods), so the first counter <12
) counts 12 horizontal synchronizing pulses, the count value becomes 0, and then counts 3 before being reset by the reset signal (c).
) is 13. In addition, in the case of the input video signal shown in Figure 4, there are 17 horizontal synchronizing pulses in one frame period, so the first counter (12) is the point at which 12 horizontal synchronizing pulses have been counted in the same way. The count value becomes 0, and then it counts 5 before being reset by the reset signal (c), so the count value (e) taken into the star (13) is 15. The output from the register (13) is the integer value obtained by dividing the count values "3. and r5." by 2, that is, "1" and "2", which can be input into the second counter (14). Said second counter (14)
is the second delayed flip-flop (second D-
F F ) (15) and a pulse signal (
), the horizontal synchronizing signal (1) is counted until the values 11 and 2 given from the register ('13) are reached, and when they reach 1 and 12, the counting operation is started. When the second counter (14) is counting the horizontal synchronizing signal (1), the second counter (14)
1" (for example, high level), and after the count ends, it outputs "0. (for example, low level).With this operation, the output (g) of the second counter (14) is as shown in FIG. One horizontal scanning period (I
It outputs a pulse having a width of 2H), and also outputs a pulse having a width of 2 horizontal scanning periods (2H) for an input video signal as shown in FIG. These 1H and 2H width pulses output from the second counter (14) are connected to the third day flip-flop (17) and the OR gate (18).
The IH phase period is further extended by 1.
1, 2H and 3H width pulses, respectively, are output from the OR gate (18), and this control signal (H) is applied to the address generator (7) to perform vertical synchronization. In the vicinity of the signal, the address of the storage device is stopped for a 2H period for an input video signal as shown in FIG. 3, and for a 3H period for an input video signal as shown in FIG.
The sidewalk of the address of the period storage device is stopped. By doing this, in the case of Figure 3, the period for 8 lines (
T) is one cycle period, and in the case of FIG. 4, the period (T') for 9 lines is one cycle period, and the memory device t(2) operates, so the desired scan conversion is a memory device with a small storage capacity. You can do it with that.

In Figures 3 and 4, memory storage! ! (For periods other than the period when the sidewalk at address 2> is stopped, video signal information is written and read in the same manner as in FIGS. 1 and 2. For example, period T:l in FIG. 3. The signals read at T4 and C-c'-d-d'-
ee-e' and c'-d -d'-e-e'-
r'', and the signals that can be read out in periods T5 and T8 in FIG. 4 are c-c'-d-d'-ee-e, respectively.
' and C'-d ''-d'-e''-e'
-r'', and it can be seen that the desired scan conversion for combining signals of adjacent fields can be performed.

In addition, there are places where the signal is lost or an abnormality occurs in the read order at the signal or the vicinity when the sidewalk operation of the address of the storage device (2) is stopped, but these are all caused during the vertical retrace period. It is No. 45 in Japan, and the work as video information is worthless.

There is no practical problem.

In this embodiment, the case where one signal series is not processed is explained, but luminance signals such as color television,
When there is a plurality of signal sequences such as color difference signals, the above-described operation may be performed on each of the signal sequences.

(G) Effects of the Invention According to the present invention, an input video signal that is not in the P3(F=')j format can be scan-converted very well and can be performed with a simple configuration.

[Brief explanation of the drawing]

All drawings relate to the present invention. FIGS. 1 and 2 are diagrams for explaining the operation of a storage device in one embodiment of the present invention, and FIGS. 3 and 4 are diagrams for explaining the operation of a storage device in another embodiment of the invention, respectively. FIG. 5 is a circuit block diagram of a scan converter according to the present invention, and FIG. 6 is a block diagram showing an example of a control circuit according to another embodiment of the present invention. (1) A/D converter, (2)...storage device, (3)
・・D/A converter, (4)・Synchronization separation circuit, (5)・P
LL0O path, (6)... Counter, (7) Address generator, (8)... Control circuit.

Claims (1)

[Claims] (1) A storage device that can store at least valid video signal information in one field, and a first storage device that controls this storage device.
comprising a control means and a second control means for detecting a ratio between a vertical scanning period and a horizontal scanning period of an input video signal of an interlaced scanning method and controlling the operation of the first control means according to this ratio, The second control means causes the first control means to cycle through the addresses of the storage device, with N being the smallest integer greater than the value of the ratio obtained by the second control means, and one cycle period being a period of N lines. and the first control means writes valid video signal information present in at least each field of the input video signal to the storage device and writes it to an address for one line of the storage device. The video signal information of the previous field that has been written and the video signal information of the current field that is subsequently written to the address for that one line are read out at twice the writing speed, and each of the video signal information obtained one after another by this reading is A scan conversion device characterized in that a progressive scanning television signal is obtained from video signal information for lines.