JPH0628439B2 - Image storage device control circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a control circuit of a semiconductor image storage device for storing a television video signal, and in particular, it is obtained from a television tuner or a video tape recorder (hereinafter referred to as VTR). The present invention relates to a control circuit for storing an image signal for one field stored in a storage device and reading it from the storage device.

[Technical background of the invention and its problems]

An image storage device has been proposed in which a television image signal for one field is written in a semiconductor storage element (hereinafter referred to as a memory) and repeatedly read out to obtain a still image.

The specific circuit configuration is shown in FIG.

1 is, for example, a television receiver having a tuner,
The analog composite video signal obtained therefrom is sampled by the A / D converter 2 with a sampling pulse that is in phase synchronization with the color subcarrier and has a frequency that is an integral multiple thereof.
Converted to digital quantity. The converted digital data is
One field is written in the RAM 4 via the S / P, P / S (serial / parallel) converter 3. When the writing is completed, the read mode is entered, and the read data is added to the D / A converter 5 via the S / P and P / S converter 3, and is converted into an analog signal by the D / A converter 5 to be displayed on the television. It is supplied to the John receiver 1. Then, it is displayed as a still image on the screen.
The S / P and P / S converters 3 are the A / D converter 2 and the D / A converter 5.
Writing to RAM4, compared to the sampling speed of
When the read cycle is slow, it functions to convert it into parallel data having a low speed, write it, read it, and return it to the serial signal having the original speed. Further, the memory control circuit 6 and the read / write control circuit 7 form a RA.
In addition to outputting the write / read pulse of M4 and controlling the RAM4 by outputting the pulse for setting the address of RAM4, the sampling clock of A / D converter 2 and D / A converter 5, S / P, A series-parallel conversion pulse to be supplied to the P / S converter 3 is generated. Further, the multiplication circuit 8 converts the color subcarrier into a signal having a frequency three times that of the color subcarrier, for example.

It is also possible to display a plurality of images on the screen by compressing a television signal using such an image storage device.

The image storage device as described above can, of course, be combined with a VTR to process the reproduction signal thereof, thereby obtaining a still image with no noise on the screen.

However, in that case, when a plurality of images are inserted in one screen to obtain a multi-screen still image, the respective screens are bent due to the time-axis fluctuation peculiar to the VTR reproduction signal.

Generally, in a domestic VTR, as shown in Japanese Examined Patent Publication No. 57-14074, the carrier of the color signal is frequency-converted into a low frequency band, and then recorded, and then restored to the original frequency during reproduction. However, at this time, the jitter that occurs during playback is removed. However, no measure for jitter is applied to the luminance signal, and the above-described screen bending occurs.

One method of solving this problem is to incorporate a time base correction device (TBC = time base collector) used in a broadcast VTR or the like. In this device, video signal data is written in a memory using a clock that changes according to the jitter of a VTR reproduction signal as a write clock, and data is read from the memory using a clock having a stable frequency as a read clock. In this case, a plurality of memories are prepared, and in consideration of a certain time, one memory is written, the other memory is being read, and the other memories are waiting for writing or reading.

In order to use this TBC for a home VTR, it is necessary to give the color signal a variation corresponding to the temporal variation of the luminance signal.

FIG. 6 shows a configuration example of a VTR equipped with such a TBC.

The luminance signal obtained from the VTR 18 is added by the adder 19 to the color signal supplied via the time base conversion circuit 10 to form a composite video signal. From the composite video signal, the sync / burst signal separation circuit 8 separates the horizontal sync signal, which is supplied to the write reference signal generation circuit 9 to produce a signal phase-synchronized with the horizontal sync signal. This signal is supplied to the time base conversion circuit 10 and is used to give the color signal the same time base fluctuation as the luminance signal. As a result, the burst signal separated by the synchronization / bust signal separation circuit 8 is also subject to fluctuations in the time axis, and the signal obtained by converting the burst signal into a continuous wave is multiplied by, for example, 3 times in the write clock generation circuit 11 to write it. It is added to the write address counter 13 as a clock. This causes the video signal to be written with a clock that fluctuates according to the jitter of the reproduced signal. At this time, a signal synchronized with the horizontal synchronizing signal obtained by the write reference signal generating circuit 9 is divided by the write clear pulse generating circuit 12, for example, to generate a clear pulse for starting and stopping writing, and a write address is generated. Add to the counter.

Further, at the time of reading, the signal output from the read reference signal generating circuit 17 is processed by the read clock generating circuit 15 and the read clear pulse generating circuit 16, and a clock having a stable frequency and a clear pulse are added to the read address counter 14.

As described above, the fluctuation of the time axis is corrected.

In the above TBC, if the capacity of the memory 4 is increased, it is possible to store signals for one screen (one field), but as described above, during writing, reading, and expecting. Each memory requires a memory for one screen, and each requires an address setting circuit and a control circuit, which is unsuitable for a home VTR that requires a small size and a low price.

In terms of function, the TBC always operates so as to supply the signal read from the memory to the television receiver, but the home VTR has a tuner for receiving the television broadcast signal, and the reproduced signal It is better not only to process the signals obtained from the tuner but also to obtain a multi-screen still image.

Therefore, as an image storage device applied to a home VTR, a memory having a capacity capable of storing signals for one screen without having a plurality of memories such as a write memory, a read memory, and a write / read standby memory like the TBC is used. Signals are written to and read from this memory individually.

Therefore, during writing to the memory, the reproduction signal of the VTR or the signal received by the tuner is displayed on the television receiver, and when the reading mode is switched, the signal read from the memory is displayed.

As described above, it is possible to arbitrarily select the above-mentioned three signals as the signal to be supplied to the television receiver, but at this time, it is necessary to prevent the sync signal from becoming discontinuous at the time of switching. is there. Especially when the memory write / read cycle becomes faster, the skew distortion on the screen and the frequency of vertical swaying (vertical rattling) increase and the screen becomes difficult to see, so more strict control is required. It is necessary to.

In order to match the phases of the above-mentioned three signals, it is necessary to take the following means.

That is, when the video signal written in the memory is first read, the read signal must have the form of a television signal, so the horizontal / vertical sync signal frequency must be read so as to be normal. I need to put it out. In other words, this is how to manage the timing of returning the write / read address to the initial point. Specifically, the following means are taken.

(B) When the number of memory address clocks equivalent to the time of one screen (one field) of the television signal (59718 when the initial address is zero and the clock frequency is the NTSC color subcarrier frequency) is detected. Return to the initial point and repeat this.

(B) The vertical synchronizing signal of the VTR reproduction signal (or the signal from the tuner) is detected, and the timing returns to the initial point.

(C) VTR head switching signal (switching pulse)
Return to the initial point with. There are ways.

The VTR and TBC generally have the following characteristics in operation.

(D) The phase of the television signal received by the tuner and the phase of the reproduced video signal of the VTR can be matched by using the vertical synchronizing signal separated from the signal obtained from the tuner as the reference signal of the servo circuit of the VTR.

(E) The reproduced image of the VTR is constantly changing due to phase error and jitter of the servo system.

When writing the video signal to the memory, the above method (b) or (c) is preferable as the method of determining the initial time of the address. The method (a) may be used, but when writing a multi-screen still image in particular, it is difficult to realize it when considering a case where a signal having a time base fluctuation which is a VTR reproduction signal is overlapped.

Therefore, considering together with the operation of (d), (b) is preferable as the method of determining the initial time of the address when writing the signal from the tuner.

In a home-use VTR, usually, two heads are wound around 180 °, and the head is switched 6 to 7 horizontal scanning periods before the vertical synchronizing position of the video signal. Therefore, the VTR reproduction signal is changed at the time of switching the head. Since the sync signal becomes discontinuous (skew distortion on the screen), it is better to use the signal that is written to the memory as a signal obtained by tracing the head half a turn. When writing the VTR playback signal to the memory It is recommended to set the address initial time of the above by the method of (C).

However, the VTR is not always in the reproducing state, and the signal from the tuner is not always given. Even in this state, it is better to normally read the signal previously written in the memory, and in that case, the method (a) is preferable for address initialization.

Therefore, it is necessary to perform address initialization processing that has the functions of (b) and (c), and at the same time has the functions of (b) and (b), but the circuit scale for that is small. There must be.

In addition, when the signals of a plurality of field periods are contracted in the horizontal and vertical directions and written in different positions of the memory address and repeatedly read out as one still image to obtain a multi-screen still image, the circuit of FIG. 6 is used. VT by using
Since the R re-picture signal is subjected to the jitter correction, each image of the multi-screen still image can be realized without being bent (excluding residual jitter).

For example, when it is desired to obtain a half image in each of the horizontal and vertical directions, the color sub-carrier frequency is halved, the luminance signal band is narrowed, and the sampling frequency and the address clock frequency are also 1 /. Write 2 and read at the original address clock frequency.

Hereinafter, an example of obtaining a multi-screen still image with four images as one as described above will be described based on FIG. 7. However, in order to simplify the description, each image shown in FIG. 7 is defined as follows. I'll do it.

Image-5: Indicates an image read from the memory including a multi-screen still image.

Image-1: Write so that it is located at the upper left of the images that make up the multi-screen still image. Or written picture.

Image-2: An image that has been written or has been written so that it is located in the upper right of the images that make up a multi-screen still image.

Image-3: An image that has been written or has been written so that it is located at the lower left of the images that make up a multi-screen still image.

Image-4: An image written or written so as to be located at the lower right of the images forming the multi-screen still image.

Image-0: Image that is written without being compressed, or image that has been written. When writing images 1 to 4, the frequencies of the sampling clock, the address clock, and the color subcarrier are set to 1/2 of those when writing image 0.

When obtaining this multi-screen, multi-plane still image (screen-5), the following points should be noted.

(1) Match the hues of the images from Image-0 to Image-4.

(2) The position of each image from Image-0 to Image-4 should always be constant.

The hue matching problem is that if the burst signal of each image-0 to 4 and the memory address clock are in a constant phase, for example, when image-1 is superimposed on image-0, image-1 is vertical to image-0. Any position may be set in the horizontal direction. This constant phase condition can be processed and satisfied by the time axis conversion circuit.

The alignment problem of (2) above is caused by the above-mentioned VTR playback image,
It contains more detailed problems based on the position (phase) alignment problem of the tuner received image and the memory read image.

In the time chart of the writing and reading process of the multi-screen still image shown in FIG. 7, (a) is the tuner received image, (b) is the VT
R playback image, (c) shows a memory writing / reading image. Further, in FIG. 7, the VTR reproduction image is stored in the memory in multi-screens, and the multi-screen display on the television receiver is based on only the memory readout image.

The initial position of the memory address (S (start) point in FIG. 7 (c)) is synchronized with the head switching pulse of the VTR,
This is the write / read initialization time of screens 0-4 (see FIG. 7).
(S point in (b)). In screen-0, the entire B frame in Fig. 7 (b) is written, and the D, F, H, and J frames are in the vertical direction at every horizontal scanning period except the horizontal and vertical blanking intervals. , And are respectively written as picture-1, picture-4, picture-2, picture-3.

In the writing state, for example, when the D frame is being written in the position of image-1, the address generation clock is halved in the horizontal direction, so the address generation clock has a frequency half that of image 0. is there. Further, since the writing and reading memories are shared, the D frame shown in FIG. 7 (b) is displayed on the screen of the television receiver at this time. When writing is complete,
When the process shifts to reading as 5, the image becomes the image in which the reduced image of D frame-1 is embedded in the upper left of the B frame of image-0 in the case of the E frame of the VTR reproduction image.

In the process of shifting from the writing to the reading, that is, in the process of shifting the signal supplied to the television receiver from the signal of the D frame of the VTR reproduced image to the signal having the D frame at the upper left of the B frame read from the memory. , If vertical / horizontal synchronization phase is not suppressed to a certain value, vertical blur and skew distortion will occur. This is a basic problem of time adjustment, but as a more detailed problem, it is necessary to always write the positions of the D, F, H, and J frames of the VTR reproduced image on the B frame to a fixed address.

A factor that prevents writing to a fixed address is the occurrence of skew distortion at the time of switching VTR reproduction signals (at the time of head switching).

Assuming that the representative time at the start point (the end point of the vertical retrace line period) of each image of D, F, H, and J is B point and the address value at that time in image-0 is the B position, it is used as a write address clock. Uses a frequency-divided output of a phase-locked oscillation signal as a horizontal synchronizing signal of a VTR reproduction television signal, the frequency of the output changes in the portion of skew distortion. Therefore, the skew distortion amount of each frame of the VTR reproduction signal, for example, the B frame and the D frame is different, and the B point and the B frame start from the S point to
The number of address clocks to the point is different. That is, when the movement amount of the images-1 to 4 is determined based on the S position of the memory address, the number of clocks from the S position to the B position (when the image 0 is the B frame and the C frame is ( = Number of addresses) is different. In other words, every time you write image-0, images-1-4
The position of will move.

[Object of the Invention]

In view of the above points, the present invention provides a plurality of reduced VTR reproduction signals as one multi-screen still image, and at that time, the writing position of each image on the multi-screen still image during VTR reproduction. Do not change depending on the amount of skew distortion at the head switching position of. In addition, tuner received signals must be processed in the same way. Further, the memory address can be initialized regardless of the presence or absence of the tuner reception signal or the VTR reproduction signal. Furthermore, the video signal is written at the timing corresponding to the head switching pulse section during VTR reproduction,
It can be read.

An object of the present invention is to provide a control circuit for an image storage device that satisfies the above items.

[Outline of Invention]

The present invention provides a means for generating a write clock that is phase locked to a horizontal synchronizing signal of an input video signal, a horizontal counting circuit that counts the clock and outputs a horizontal synchronizing signal, and a horizontal synchronizing signal that counts the horizontal synchronizing signal. It has a vertical counting circuit that outputs a vertical synchronizing signal, and when the vertical counting circuit is initialized by the vertical synchronizing signal of the input video signal and the count values of the horizontal counting circuit and the vertical counting circuit reach predetermined values, the memory The address is initialized, and writing and reading are performed.

Further, according to the present invention, a video signal of one section of the head switching pulse at the time of reproduction of the VTR, that is, the section corresponding to the head trace is written in the memory, and thereafter the reproduction operation of the VTR is stopped and there is no reproduction signal, and the tuner reception signal If not, the horizontal counting circuit counts the read clock with stable frequency, and the vertical counting circuit initializes with its own predetermined count value, and when the count value of each counting circuit reaches a predetermined value. , The memory address is initialized and read is set.

Furthermore, the present invention provides a VT for obtaining a multi-screen still image.
The memory address is held as a reference at a time when the influence of the frequency fluctuation of the write clock due to the skew distortion at the time of switching the head of the R reproduction video signal is not so much, and each image is written based on the reference address. It has been set.

Example of Invention

Hereinafter, the control device of the image storage circuit according to the present invention will be described in detail.

FIG. 1 is a block diagram showing an embodiment of the image storage device of the present invention. In FIG. 1, the same parts as those in FIG. 5 are designated by the same reference numerals.

The VTR 21 has a tuner unit 22 and a storage / playback unit 23. The tuner unit 22 receives a broadcast signal input from the input terminal 1N, converts it into a composite video signal, and the recording / playback unit 23 performs recording / playback. Regarding the signal processing in the recording / reproducing unit 23,
For example, as described above, the one shown in Japanese Patent Publication No. 57-14074 is applied. That is, at the time of recording, the luminance signal is FM-modulated, the color signal is frequency-converted into the lower band of the luminance signal, and then both signals are added and recorded. At the time of reproducing, both signals are separated and extracted from the reproduced signal. The FM signal is demodulated for the luminance signal, and the chrominance signal is converted back to the original frequency.
At this time, by using an idler signal for frequency conversion that has the same time axis fluctuation as the color signal, the color signal converted to the original frequency has no time axis fluctuation.

The FM demodulated luminance signal is output from terminal Y and is switched.
Directly supplied to 24 terminals n and low-pass filter
It is supplied to the terminal m of the switch 24 via 25. switch
The output of 24 is applied to adder 19. The color signal converted to the original frequency is output from the terminal C of the VTR 21, and the time axis conversion circuit 10 gives the same time axis variation as the luminance signal,
The adder 19 adds the luminance signal to form a composite video signal.
This composite video signal is converted into a digital signal by the A / D converter 2, further converted into a parallel signal by the S / P and P / S converter 3, and written in the memory. At the time of reading, the signal read from the memory is converted into a serial signal by the S / P, P / S converter 3 and D
The signal is converted into an analog signal by the / A converter 5 and supplied to the television receiver 26.

Writing and reading to the memory 4 will be described in detail.

The composite video signal obtained from the adder 19 is the sync separation circuit 27.
And the horizontal synchronizing signal H _D and the vertical synchronizing signal V _D are separated. The horizontal synchronizing signal H _D is supplied to a horizontal phase locked oscillator 28, wherein, in synchronization with the horizontal synchronizing signal H _D, the frequency of 6sc as a reference for making a write clock (sc = color sub-carrier frequency) A signal having is created.

That is, the horizontal phase locked oscillator 28 has a VCO which oscillates at a frequency of 6Sc, by incorporating the VCO to the phase locked loop controlled by the horizontal synchronizing signal H _D (PLL), a horizontal synchronization signal H as its output A signal with the same time axis variation as _D is obtained. This 6sc signal is frequency-divided to a predetermined frequency, led to terminals n and m of the switch 29, switched and selected, and supplied to the time axis conversion circuit 10. In the time-axis conversion circuit 10, for example, an idler signal is created from the signal and a color subcarrier signal synchronized with the phase of the reproduction burst signal supplied from the terminal CW of the VTR 21, and frequency conversion is performed by the idler signal. The signal is given the same time axis variation as the luminance signal. The 6sc signal generated by the horizontal phase locked oscillator 26 is directly supplied to the matrix circuit 30 and Is divided into H (horizontal frequency) signals Hp and supplied to the vertical counting circuit 31.

The vertical counting circuit 31 clears the vertical synchronization signal V _D supplied from the synchronization separation circuit 27 to generate a horizontal phase synchronization oscillator.
The Hp signal of H supplied from 26 is counted and various pulses for determining the timing of writing and reading to the memory 4 are output and supplied to the matrix circuit 30.

The matrix circuit 30 selects a necessary pulse according to a mode setting signal applied from the outside to select a memory control circuit.
Supply to 32.

The memory control circuit 32 includes an address counter and a frequency dividing circuit, sets the address of the memory 4, and supplies a clock to the A / D converter 2, S / P, P / S converter 3, and D / A converter 5. Create and output.

FIG. 2 shows a specific circuit of the horizontal phase locked oscillator circuit 28.

The VCO 35 oscillates at a frequency of about 6 sc, and its output is supplied to the 1/3 frequency divider 37 via the switch 36 and divided into 1/3, and further, via the 1/2 frequency divider 38 to the switch 29. To the n terminal. The output of 1/2 divider 38 is further divided by 1/2 divider 39.
It is divided by 1/2 and led to the m terminal of the switch 29. Therefore, output VCO35 to the n terminal of switch 29.
The signal of sc divided by 1/6 is output, and the 1/12 divided signal of the output of the VCO 35 is output to the m terminal of the switch 29. 1 /
The output of the frequency divider 37 is further supplied to the horizontal counter 40, where it is counted. A constant is preset by the load pulse in the horizontal counter 40, and when the count value reaches a predetermined value, the coincidence circuit 41 detects this. The output of the coincidence circuit 41 is applied to the pulse generation circuit 42, and the pulse generation circuit 42 outputs a load pulse at that timing.

At this time, if the constant preset in the horizontal counter 40 is n, the count value of the horizontal counter 40 when the coincidence output from the coincidence circuit 41 is set to n + 455. That is, the horizontal counter 40, the coincidence circuit 41, and the pulse generation circuit 42 constitute a 1/455 frequency divider. Pulse generation circuit 42 further receives the match output of the coincidence circuit 41 outputs a pulse H _BL showing the inter-pulse Hp and the horizontal retrace blanking of the horizontal frequency. Pulse Hp is converted into a trapezoidal wave trapezoidal wave generating circuit 43 is supplied to the sample hold circuit 44, where it is sampled by the horizontal synchronizing signal H _D. The output of the sample hold circuit 44 is converted to a DC voltage by the loop filter 45, and the VCO
35 is supplied as a control signal. The face lock loop is configured as described above. The switch 36 is a write / read switch, and is controlled by a control signal so that the terminal W is selected in the write mode and the terminal R is selected in the read mode. A stable 6sc signal is supplied to the terminal R from the multiplication circuit 33. Also VCO35
The output of is transmitted to the matrix circuit 30.

FIG. 3 shows a specific circuit configuration of the vertical counting circuit 31 and the matrix circuit 30.

A vertical synchronizing signal V _D is applied to the vertical counting circuit 31 from the sync separation circuit 27, and this is applied to the AND gate 45 pulse shaper 5
0, applied as a clear pulse to the vertical counter 52 via the OR gate 51. As a result, the vertical counter 52 counts the pulse Hp supplied from the horizontal phase locked oscillator 28 from the initial value. The count values of the vertical counter 52 are compared by the comparison circuit 53, and coincidence pulses are output to the 16th, 255th, 262nd, and 263rd thereof. The 16th pulse indicates the end point of the vertical blanking period, and the 255th pulse is the sync separation circuit 2
The detection delay in 7 is 1.5 horizontal scanning period (H), and
7H before the vertical sync signal position of 2.5H, that is, VT
It almost coincides with the timing of the R head switching pulse.

Now, assume that the reproduced image B of the VTR shown in FIG. The 255th pulse output from the comparison circuit 53 at the timing of the VTR head switching pulse is supplied to the AND gate 54 to open the gate. As a result, the signal _HBL indicating the horizontal blanking period applied from the horizontal phase locked oscillator 28 is applied to the flip-flop 55 via the AND gate 54, and the Q output thereof is set to "1". This Q
The output is supplied to the memory control circuit 32 as an initial address setting signal via the pulse shaper 57 and the OR gate 58. At the same time, a mode setting signal designating image 0 inputted from the outside by the Q output is latched in the latch circuit 56. A control signal for writing the image 0 is output from the logic circuit 59 according to the content of the latch of the latch circuit 56. By the control signal, the switch 60 is first switched to select the writing clock supplied from the horizontal phase locked oscillator circuit 28. Further, the NAND gate 61 outputs a write mode signal, and the OR gate 62 outputs a memory mode selection signal indicating that the image to be written is not compressed. The signal from the OR gate 62 controls the switches 24 and 29 shown in FIG.
29 are switched so as to select the terminal n respectively.

Each output signal of the matrix circuit 30 is guided to the memory control circuit 32.

FIG. 4 shows a specific circuit configuration of the memory control circuit 32.

The initial address setting signal supplied from the matrix circuit 30 is applied as a clear pulse to the address registers 76 and 78, whereby the initial setting of the address is performed. This timing is indicated by point S in FIGS. 7 (b) and 7 (c). The 6sc signal obtained from the horizontal phase locked oscillator 28 is applied to the 1/12 shift counter 80, where it is divided. The OR gate 81 is controlled by a memory mode selection signal indicating whether the video signal to be written is compressed or not.
.About.85 and AND gates 86 to 90 are controlled, and the frequency division output suitable for the purpose is obtained from the 1/12 shift counter 80. When the image 0 is written, the memory mode selection signal becomes high level and the AND gates 86 to 90 open, so that the OR gates 81 to 85 are opened.
Outputs a signal having a frequency twice as high as that when each AND gate 86 to 90 is closed. At this time, if the sampling frequency of the A / D converter 2 is set to 3sc and the three sampling data are converted into parallel signals by the S / P, P / S converter 3 and written simultaneously, the write clock frequency becomes
It becomes sc. Therefore, the OR gate 81 outputs the signal of sc, which is supplied to the address register 76 as a clock. The Q output of the address registers 76 and 78 is gate 9
Since it is guided to the adders 92 and 98 via 1,97 and 1 is added and fed back to the data terminal D, the address of the memory 4 is sc
The clock is set sequentially. At this time, a write mode signal, a signal designating images 0 to 4 and a 1/12 shift counter 80
Of the signal necessary for writing, W _E
(Write enable) ▲ ▼ (Column address strobe), ▲ ▼ (Row address strobe)
A signal to be supplied as a clock to the S / P, P / S converter 3 and A / D converter 2 is created. Note that, for example, if one of the address registers 76 and 78 is for a column address, the other is for a row address, and the output of each is switched by the switch 99 and supplied to the memory 4.

As described above, the image 0 starts to be written in the memory 4 at the timing (point S in FIGS. 7 (b) and (c)) in synchronization with the head switching of the VTR 21, and according to the count values of the address registers 76 and 78. It is written in sequence. Image 0 writing progresses, 262
At the H-th time, a signal is obtained from the comparison circuit 53 of the vertical counting circuit 31 at that timing. However, this is because the Q output of the flip-flop 55 is low level and the AND gate 70
Is not transmitted to the vertical counter 52 because it is closed. Next, the vertical synchronizing signal V _D is applied to clear the vertical counter 52 for a while, and then the signal is output from the comparison circuit 53 also at the 263th H, whereby the vertical counter 52 is cleared again and its Hp pulse counting is started from this point. Then, at the 16th hour, a signal is output from the comparison circuit 53 of the vertical counting circuit 31 and is supplied to the AND gate 65 to open this gate. Therefore, the signal H indicating the horizontal blanking period
_BL passes through the AND gate 65, and passes through the pulse shaper 66 and the AND gate 74 to the register 7 of the memory control circuit 32.
Since it is added to 5,78 as a clock, the values of the address registers 76,78 at that time are latched in the registers 75,78.
This point is shown as point B in FIGS. 7 (b) and (c). That is, this point is the end point of the vertical blanking period and the horizontal blanking period when the period from the generation of the vertical synchronization signal to the end of the vertical blanking period is 16 horizontal scanning periods on average. Is the starting point, and is a reference point when writing compressed images 1 to 4 later. Writing continues 255
A signal is output from the comparison circuit 53 of the vertical counting circuit 31 at the timing of the Hth signal, and a signal indicating the horizontal blanking period at the AND gate 54.
It is _ANDed with H _BL and supplied to the flip-flop 55 as a clock. This makes the flip-flop 55
Is inverted, its Q output becomes high level, and is applied as a clear pulse to the address registers 76 and 78 of the memory control circuit 32 via the pulse shaper 63 and the OR gate 58.
The memory address is set to the initial position again. At the same time, the latch circuit 56 of the matrix circuit 30 is cleared, the write mode is released, and the read mode is automatically set.

Although the image 0 is written as described above, the signal obtained at the 255th timing from the comparison circuit 53 of the vertical counting circuit that determines the end of writing is cleared by the vertical counter at the 263th signal. , The timing is not exactly 255th from the timing of generation of the vertical synchronization signal, but is 1 / 2H behind. Therefore, the number of horizontal scanning lines between the preceding 255th signal is 263 instead of 262.5.

Therefore, the video signal for 263H has been written in the memory, but this is alternated for each screen at the time of 262H.
This is because the minute signal and the signal of 263H are read to eliminate the vertical backlash on the screen and the phase disturbance of the burst signal.

Now, the case of writing the image 1 shown by D in FIG. 7 (b) will be described.

In this case, a mode setting signal designating image 1 is input to the latch circuit 56 of the matrix circuit 30. Vertical counting circuit 31
The comparator 53 outputs an output at the timing of the 255th H from the vertical synchronizing signal V _D , which is ANDed with the signal indicating the horizontal blanking period, as in the case of writing the image 0, and the flip-flop 55 And the Q output is made high level. As a result, the mode setting signal is transferred to the matrix circuit 30.
The image 1 write mode is set by the latch circuit 56. At the same timing, the initial address setting signal is output from the OR gate 58 and the flip-flop 67 is set by the output of the NAND gate 64. Further, each gate is controlled by the signal indicating the writing mode of the image 1 output from the logic circuit 59 of the matrix circuit 30,
Although the NAND gate 61 is also open, its input is at low level, the write mode setting signal is not output, and writing is not started. The flip-flop 67 is a comparison circuit.
Because it is reset by the AND output of the signal H _BL indicating the signal and the horizontal retrace period indicating the 16H-th obtained from 53, its Q
The output becomes the signal V _BL indicating the vertical blanking period. Therefore, the output of the NOR gate 68 to which the signal V _BL and the signal H _BL indicating the horizontal blanking period are input becomes high level during the period excluding both blanking periods. Therefore, the output of NOR gate 68 can be used as a write mode setting signal. The output of the NOR gate 68 is added to the NAND gate 69 together with the output signal of the lowest stage of the vertical counter 52 (that is, the signal obtained by dividing the horizontal frequency signal Hp by 1/2) L _SB and the signal indicating the image 1 writing mode. To be Signal from vertical counter 52 L _SB
Is a signal for controlling so that a signal for only one horizontal scanning period is written in the memory 4 in the horizontal direction. The NAND gate 61 is open except when writing the image 0, and the output of the NAND gate 69 is supplied to the memory control circuit 32 as a write mode setting signal. At this time, when the vertical blanking period ends, the AND gate 49 opens and the logic circuit
A signal designating writing of image 1 from 59 is supplied to the memory control circuit 32 as a ROM selection signal. Memory control circuit
In 32, a predetermined constant is read from the ROM 94 and supplied to the adder 92. At the same time, the gates 91 and 97 are closed and the gates 93 and 96 are controlled to open.
The address data at the point B latched in the registers 75 and 77 are supplied to the adder 92 through the gates 93 and 96, and the ROM 9
Added with constant from 4. At the same timing, the memory mode selection signal, which is the output of the OR gate 62, becomes low level, so that the 1/12 shift counter 80 of the memory control circuit 32 is
Each clock obtained from will be half the frequency.
That is, the A / D conversion clock is 3 / 2sc and the address clock is 1 / 2sc. This address clock is added to the address registers 76 and 78, the address registers 76 and 78 read the output of the adder 92 as data, and sequentially count from that value. The write mode setting signal is generated with a horizontal blanking period delayed further from that timing, and the writing of the image 1 is started. At this time, the switches 24 and 29 shown in FIG. 1 are respectively switched to the terminal m side by the signal from the logic circuit 59 of the matrix circuit 30, and the television signal written in the memory 4 is the luminance signal thereof. Is band-limited by the low-pass filter 25, and the color signal is
The time base conversion circuit 10 converts the sub carrier frequency into one having a half and the same time axis fluctuation as the luminance signal.

As described above, the writing of the image 1 is started, and the writing is completed by the 255th pulse obtained from the comparison circuit 53 of the vertical counting circuit 31. After that, it automatically switches to read mode.

When writing screens 2, 3 and 4, the ROM94 constants corresponding to each screen are used.
The same operation can be performed by further reading and shifting the address of the writing start point.

The images 1 to 4 are written as described above. When writing the image 0, the position on the memory (4) of the vertical blanking period end point (point B) is stored and the position is stored. Since the writing start points of the images 1 to 4 are determined on the basis of the reference, the four images are always written at substantially constant positions.

Generally, the reproduced video signal of the VTR is subjected to skew distortion at the time of head switching, and the amount thereof is not constant, so that the response of the horizontal phase synchronous oscillation circuit 28 at the time of head switching is different in each field of the reproduced video signal. The frequency of the 6sc signal obtained also changes accordingly. Therefore, memory 4 from the time of head switching until the end of the vertical blanking period
If the number of address clocks of each image is different between the reproduced video signals and the head switching point is set as a reference point for starting writing of each of the images 1 to 4, the actually written position is not constant and the memory area displayed on the screen There may be a part in which no signal is written, and there is a problem that the image is missing when read. Horizontal phase-locked oscillator circuit due to this skew distortion
Since the disturbance of the response of 28 substantially subsides by the end of the vertical blanking period, the address of the end point (point B) of the vertical blanking period is stored and used as a reference as in the embodiment of the present invention. By writing each of the images 1 to 4 as described above, each of the images 1 to 4 can be always written in a substantially constant position.

In the above description, the case where the reproduction signal from the VTR 21 is written in the memory 4 has been described. However, in a general VTR, the television signal received by the tuner is detected and converted into a composite video signal when not in the reproduction mode. It is set so that it is converted, further divided into a luminance signal and a color signal, subjected to processing for recording respectively, and then subjected to inverse signal processing again to be converted into the original signal form and output. .
Therefore, if a signal of a stable color sub-carrier frequency that is phase-synchronized with the luminance signal, the color signal, and the burst signal of the color signal is output from the terminals Y, C, and CW of FIG. Signals from can be written to the memory 4. In that case, since the luminance signal does not have a time axis fluctuation, the time axis conversion circuit 10 may operate only as a color subcarrier frequency conversion circuit for obtaining a compressed video signal.

Next, the read mode will be described.

When the write mode ends, the read mode is automatically entered, and the switch 60 of the matrix circuit 30 is switched to select the signal for the read clock. This makes VT
The signal of the stable color sub-carrier frequency sc obtained from R21 is converted to the frequency of 6sc by the frequency multiplier circuit 33, and is applied as a clock to the 1/12 shift counter 80 of the memory control circuit 32.

On the other hand, at the end of writing, the address registers 76 and 78 of the memory control circuit 32 are cleared by the initial address setting signal output from the OR gate 58 of the matrix circuit 30 and the sc obtained by the 1/12 shift counter 80
The signal of 1 is sequentially counted from 1. As a result, reading from the memory 4 is started. The switching from the end of writing to the memory 4 to the start of reading is performed in a continuous time flow. When the reading progresses and a pulse indicating the 262th H is output from the comparison circuit of the vertical counting circuit 31, this is the AND gate 70, the OR gate 72, the pulse shaper 73,
It is applied as a clear pulse to the vertical counter 52 through the OR gate 51. Sometimes the AND gate 45 is closed by the Q output of the flip-flop 55 and the vertical synchronizing signal V _D is not used. When the vertical counter 52 counts 255 H _p pulses, an output is output from the comparison circuit 53 and the matrix circuit
The flip-flop 55 of 30 is inverted, the initial address setting signal is output again, and the memory 4 is read from the beginning. After that, the vertical counter 52 is cleared by the vertical synchronizing signal V _D , further cleared by a pulse corresponding to the 263th H, and counts Hp pulses again from the beginning. After that, the process is repeated, and the video signal for 262H per screen and 263
Video signals for H are alternately read.

Therefore, at this time, if the vertical synchronizing signal of the video signal obtained from the tuner unit 22 is used as the reference signal of the servo system of the VTR 21, the video signal supplied to the television receiver 26 is supplied from the tuner unit 22 to the VTR 21. The image is not disturbed even if the reproduction signal and the read signal from the memory are switched.

When the operation of the VTR 21 is completely stopped and no output signal is output, various timing signals are output inside the vertical counting circuit 31 and the reading from the memory 4 is performed without any trouble. Be done. In this case, the multiplication circuit 33
It may be composed of, for example, a crystal oscillator circuit that oscillates freely at a stable frequency of 6 sc.

〔The invention's effect〕

As described above, according to the present invention, even if the source of the video signal supplied to the television receiver is switched between the tuner VTR and the memory, the screen is not disturbed, and the multi-screen is written in the memory. Even in such a case, the control circuit of the image storage device can be provided in which the write position in the memory is substantially constant because it is not affected by the skew distortion at the head switching point, and a good multi-screen still image can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a control circuit of an image storage device according to the present invention, and FIGS. 2 to 4 are circuit configuration diagrams specifically showing the main part of FIG. 1, and FIG. FIG. 6 is a circuit block diagram showing a control circuit of a conventional image storage device, and FIG. 7 is a configuration diagram for explaining a relationship between a video screen written in a memory and a video screen read from the video screen. is there. 21 …… VTR, 25 …… Low pass filter.

Claims (3)

[Claims] 1. A means for generating a first signal phase-synchronized with a horizontal synchronizing signal of a video signal; a horizontal counting means for counting the first signal and outputting a second signal of a horizontal frequency; Vertical counting means initialized by a vertical synchronizing signal of a video signal or a signal based on a counting value indicating vertical synchronization generated by itself, counting the second signal; and a counting value of the horizontal counting means and the vertical counting means. Address setting means that is initialized when the count values reach predetermined values and counts the first signal to set an address; and the video signal to the address set by the address setting means of the storage element. A control circuit for an image storage device, comprising: a writing unit. 2. When writing a plurality of video signals to the storage element, the time when the respective video signals are aligned is set to the time when the horizontal counting means and the vertical counting means each count the predetermined value. A control circuit for an image storage device according to claim 1. 3. When writing a plurality of video signals to the storage element, the address setting means outputs a binary adder, a first address register holding a result of the addition, and an output of the first address register. Corresponding to each video signal, a second address register for holding and a switch for selectively switching either one of the outputs of the first and second address registers to one addition input of the adder, Has a means for generating a binary constant to be supplied to the other addition input of this selected adder, and the value of the first address register is set to a second value at the alignment time of the video signal to be written first. Of the video signal to be reduced and written by adding the selected binary constant value to the second address register value at the alignment time of the video signal to be reduced and written. The control circuit of the image storage device of claims the first term of which is characterized in that so as to set the address position or the second Claims.