JPS6174368A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6174368A JPS6174368A JP59197303A JP19730384A JPS6174368A JP S6174368 A JPS6174368 A JP S6174368A JP 59197303 A JP59197303 A JP 59197303A JP 19730384 A JP19730384 A JP 19730384A JP S6174368 A JPS6174368 A JP S6174368A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semi
- semiconductor device
- semiconductor
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 239000000969 carrier Substances 0.000 claims description 6
- 230000003321 amplification Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
- H10D62/184—Base regions of bipolar transistors, e.g. BJTs or IGBTs of lateral BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/60—Lateral BJTs
Landscapes
- Bipolar Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、バイポーラトランジスタ動作をなさしめる特
殊な構成による半導体装置、特に高出力動作に適した半
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a special configuration that allows bipolar transistor operation, and particularly to a semiconductor device suitable for high-output operation.
半導体集積回路の回路素子としてのバイポーラトランジ
スタは、製造の簡易化、配線パターンの簡易化から、エ
ミッタ、ベース、コレクタの各領域が平面的に配置され
た、いわゆるラテラル構造が採られる。しかし、このラ
テラル構造のバイポーラトランジスタは、一般に電流増
幅率βが小さい。A bipolar transistor as a circuit element of a semiconductor integrated circuit has a so-called lateral structure in which the emitter, base, and collector regions are arranged in a planar manner for the purpose of simplifying manufacturing and wiring patterns. However, this lateral structure bipolar transistor generally has a small current amplification factor β.
一方、本出願人は、先に特願昭58−224841号に
おいて、ラテラル構造をとり、しかも電流増幅率が大き
いバイポーラトランジスタ動作をなす半導体装置を提案
した。この半導体装置は第4図及び第5図にネオように
、半絶縁性の半導体基体(1)の−主面に例えばn型の
エミッタ領域となる第1領域(2)及びコレクタ領域と
なる第2領域(3)と、p型の第3領域(4)とを設け
、夫々の領域(2)、 (3)及び(4)にエミッタ電
極(5)、コレクタ電極(6)及びベース電極(7)を
形成して構成される。そして、第1及び第3領域(2)
及び(4)間に順バイアス電圧を与えることによって、
第1及び第3領域(2)及び(4)間の半絶縁性半導体
(1)に第3領域(4)からの正札が面濃度に注入され
て仮想ベース領域(8)が形成され、第1領域□(2)
から注入された電子が仮想ベース領域(8)を通じて正
にバイアスされている第2領域(3)に達し、n−p−
n型のバイポーラトランジスタ動作がなされる。On the other hand, the present applicant previously proposed in Japanese Patent Application No. 58-224841 a semiconductor device which has a lateral structure and operates as a bipolar transistor with a large current amplification factor. As shown in FIGS. 4 and 5, this semiconductor device has, for example, a first region (2) serving as an n-type emitter region and a second region serving as a collector region on the main surface of a semi-insulating semiconductor substrate (1). A second region (3) and a p-type third region (4) are provided, and an emitter electrode (5), a collector electrode (6) and a base electrode ( 7). And the first and third areas (2)
and (4) by applying a forward bias voltage between
The genuine tag from the third region (4) is injected into the semi-insulating semiconductor (1) between the first and third regions (2) and (4) to form a virtual base region (8), and the 1 area □ (2)
The electrons injected from the virtual base region (8) reach the positively biased second region (3), and the n-p-
An n-type bipolar transistor operation is performed.
ところで、このような半導体装置において、第1、第2
及び第3領域12)、 +31及び(4)が互いに平行
配列されている構成では、第5図に丞ずように第1領域
(2)及び・第3領域(4)間に形成される仮想ベース
領域(8)が平面パターンの端から外に拡がる性質があ
る。このため、有効でないベース電流が増え(電流が端
部に集中する傾向があり)、西出力動作に通さないこと
、また素子を微小化していったときに隣の素子間の分離
が不完全になる等の問題点を有していた。By the way, in such a semiconductor device, the first and second
In a configuration in which the and third regions 12), +31, and (4) are arranged in parallel to each other, a virtual space formed between the first region (2) and the third region (4) as shown in FIG. The base region (8) has the property of expanding outward from the edge of the planar pattern. As a result, the ineffective base current increases (the current tends to concentrate at the ends), which prevents it from passing through the west output operation, and when devices are miniaturized, the isolation between adjacent devices becomes incomplete. It had some problems, such as:
本発明は、この様なバイポーラトランジスタ動作をなさ
しめる特殊な構成の半導体装置において、上述の点を改
善した半導体装置を提供するものである。The present invention provides a semiconductor device having a special structure that allows such a bipolar transistor operation to be performed, and which improves the above-mentioned points.
本発明は、半絶縁性の半導体(11)に、1導電型のエ
ミッタ領域となる第1領域(12)とコレクタ領域とな
る第2領域(13)とを所要の間隔を保[)シて配置す
ると共に、これら第1及び第2領砲(12)及び(13
)間に他の導電型の第3領域(14)を設ける。そして
第3領域(14)と第1領域(12)との間に順バイア
ス電圧を与えてこの第3領域(14)からその多数キャ
リアを第3領域(14)と第1領域(12)間の半絶縁
性の半導体領域(18)に注入し、この領域(18)に
仮想ベース領域(19)を形成してバイポーラトランジ
スタ動作をなさしめるものであるが、特に本発明におい
ては、第1領域(12)、第2領域(13) 、第3領
域(I4)を平面的にみて、同心的に順次取り囲むよう
に配置形成する。The present invention provides a semi-insulating semiconductor (11) in which a first region (12) serving as an emitter region of one conductivity type and a second region (13) serving as a collector region are kept at a required distance. At the same time, these first and second territorial guns (12) and (13)
) is provided with a third region (14) of another conductivity type. Then, by applying a forward bias voltage between the third region (14) and the first region (12), the majority carriers are transferred from the third region (14) between the third region (14) and the first region (12). is implanted into a semi-insulating semiconductor region (18) to form a virtual base region (19) in this region (18) to operate as a bipolar transistor. In particular, in the present invention, the first region (12), the second region (13), and the third region (I4) are arranged and formed so as to concentrically surround them in a plan view.
半絶縁性半導体(11)内に仮想ベース領域(19)が
形成されることによって第1領域(12)から注入され
た多数キャリアが仮想ベース領域(19)を通じて第2
領域(13)に達し、バイポーラトランジスタ動作がな
される。By forming a virtual base region (19) in the semi-insulating semiconductor (11), majority carriers injected from the first region (12) are transferred to the second region through the virtual base region (19).
The region (13) is reached and bipolar transistor operation is performed.
そして、このとき、第1、第2及び第3領域(12)、
(13)及び(14)が同心的に順次取り囲む様に形成
されているので、仮想ベース領域(19)は素子内に閉
じ込まれ、ベース電流、コレクタ電流が均一に流れる。At this time, the first, second and third areas (12),
Since (13) and (14) are formed so as to concentrically surround each other, the virtual base region (19) is confined within the element, and the base current and collector current flow uniformly.
これが為にdli出力動作が得られ、また微小素子を構
成しても、素子間分離が完全となる。For this reason, dli output operation can be obtained, and even if minute elements are configured, isolation between elements is perfect.
第1図及び第2図を参照して本発明による半導体装置の
一例を説明する。半絶縁性、すなわち実質的に電流坦体
濃度が少なく、高抵抗例えば106Ω■以上を呈するI
II−V族化合物半導体基体例えばGaAs−或いは半
導体5(11)を設け、これの一平面(lla)に臨ん
で例えばn型のエミッタ領域となる高不純物濃度の第1
領域(12)とこれを取り囲む様に所要の間隔を保して
n型のコレクタ領域となる高不純物濃度の第2領域(1
3)を、例えばイオン注入法、拡散法等によって形成す
る。そして、これら第1及び第2の領域(12)及び(
I3)間に第1領域(12)を取り囲むように一生面(
lla )に臨んで例えばp型の高不純物濃度の第3領
域(14)を、イオン注入法、拡散法等によって形成す
る。即ら、これら第1、第2及び第3領域(12)。An example of a semiconductor device according to the present invention will be described with reference to FIGS. 1 and 2. I that is semi-insulating, that is, has a substantially low current carrier concentration and exhibits a high resistance, e.g., 106 Ω or more.
A II-V compound semiconductor substrate, for example, GaAs, or a semiconductor 5 (11) is provided, and facing one plane (lla) of the substrate is a first layer with a high impurity concentration, which will become, for example, an n-type emitter region.
A second region (12) with a high impurity concentration that becomes an n-type collector region is formed surrounding the region (12) at a required distance.
3) is formed by, for example, an ion implantation method, a diffusion method, or the like. Then, these first and second areas (12) and (
I3) so as to surround the first area (12) between the two surfaces (
For example, a p-type third region (14) having a high impurity concentration is formed by ion implantation, diffusion, or the like, facing the region lla). namely, these first, second and third regions (12).
(13)及び(I4)は、第1領域(12)を中心とし
た所謂同心円状に形成する。第3領@(14)は第1及
び第2領域(12)及び(13)より浅い深さに形成さ
れる。第1、第2及び第3領域(12)。(13) and (I4) are formed in a so-called concentric circle shape centered on the first region (12). The third region @ (14) is formed at a shallower depth than the first and second regions (12) and (13). first, second and third regions (12);
(13)及び(14)には夫々エミッタ、コレクタ及び
ベース各電極(15ン、(I6ン及び(17)がオーミ
ックに被着される。E、C及びBは夫々エミッタ、コレ
クタ及びベースの各端子を示す。(13) and (14) are respectively ohmically coated with emitter, collector and base electrodes (15, (I6) and (17). E, C and B are emitter, collector and base electrodes, respectively. Indicates terminal.
そして、第1及び第3領域(12)及び(14)間に順
バイアス電圧を、第3及び第2領域(14)及び(12
)間に逆バイアス電圧を与える。このようにすると、第
3領域(14)から多数キャリアの正孔が第1領域(1
2)と第3領域(14)間及び第3領域(14)下の半
絶縁性半導体Pi(11)による高抵抗領域(lli)
に注入され、ここに仮想ベース領域(19)を生成し、
これによって第1領域(12)の多数キャリアの電子の
注入を促し、これが仮想ベース領域(19)を通じて第
2領域(13)に達せしめてラテラル構造のn−p−n
型のバイポーラトランジスタ動作をなさしめる。Then, a forward bias voltage is applied between the first and third regions (12) and (14), and the third and second regions (14) and (12
) Apply a reverse bias voltage between the In this way, the holes of majority carriers are transferred from the third region (14) to the first region (14).
2) and a high resistance region (lli) made of semi-insulating semiconductor Pi (11) between and under the third region (14)
to generate a virtual base area (19) here,
This promotes the injection of majority carrier electrons in the first region (12), which reach the second region (13) through the virtual base region (19), forming the n-p-n structure of the lateral structure.
This type of bipolar transistor operates.
尚、第2図では半絶縁性の半導体(11)の−主面に臨
んで、第11第3及び第2領域(12)。In addition, in FIG. 2, the 11th third and second regions (12) face the -main surface of the semi-insulating semiconductor (11).
(14)及び(13)を互いに同心円状に形成したが、
第3図に示すように第1.第3及び第2領域(12)
。(14) and (13) were formed concentrically with each other,
As shown in FIG. Third and second areas (12)
.
(14)及び(13)を、正方形成いは矩形等の形状を
もって互いに同心的に取り囲む様に形成してもよい。(14) and (13) may be formed in a square or rectangular shape so as to surround each other concentrically.
また、上側では第1、第2及び第3領域(12)。Also, on the upper side are first, second and third regions (12).
(13)及び(14)をエミッタ領域となる第1領域(
12)が中心となる様に同心的に配したが、コレクタ領
域となる第2領域(13)が中心となる様に同心的に配
することもできる。(13) and (14) are used as the first region (
Although they are arranged concentrically so that the second region (12) is at the center, they can also be arranged concentrically so that the second region (13) serving as the collector region is at the center.
上述した本発明による半導体装置によれば、ラテラル構
造をとるものであるが、それにもかかわらず、その電流
増幅率βが大にできるという利益がある。すなわち、実
質的にベース領域、すなわらLIE人キャリアによる電
流路を商不純物濃度を有する第3領域(14)外の半絶
縁性の領域(11)に形成するようにしたので、注入キ
ャリアの拡散長が極めて長く、また半導体表面の再結合
速度の大きい部分の影響を受けにくいこと、更にまた第
3領域(14)中に流れずに、半絶縁性領域(11)の
ポテンシャルバリアが低く平坦でコレクタ電圧の影響を
受けにくい部分を流れるなどが、相俟って電流増幅率の
高いバイポーラトランジスタ動作がなされる半導体装置
を構成できるものである。Although the semiconductor device according to the present invention described above has a lateral structure, it nevertheless has the advantage that its current amplification factor β can be increased. That is, since the base region, that is, the current path by the LIE carriers is substantially formed in the semi-insulating region (11) outside the third region (14) having a commercial impurity concentration, the injected carriers are The diffusion length is extremely long, and it is not easily affected by the high recombination rate of the semiconductor surface.Furthermore, the potential barrier of the semi-insulating region (11) is low and flat without flowing into the third region (14). When the current flows through a portion that is not easily affected by the collector voltage, it is possible to construct a semiconductor device that operates as a bipolar transistor with a high current amplification factor.
また特に化合物半導体によって構成するときは、更に高
速動作にすぐれた半導体装置を得ることができる。Further, especially when constructed from a compound semiconductor, it is possible to obtain a semiconductor device with even better high-speed operation.
更にまた、この特性は、その実質的ベース領域が半絶縁
性の半導体中に形成されるので、第3領i&(14)の
深さ、特性等のばらつきによって受ける影響が小さく、
これがため安定した均一な特性の半導体装置を容易に製
造することができる。Furthermore, since the substantial base region is formed in a semi-insulating semiconductor, this characteristic is less affected by variations in the depth, characteristics, etc. of the third region i&(14).
Therefore, a semiconductor device with stable and uniform characteristics can be easily manufactured.
またラテラル構造をとるので、その電極とり出し、配線
が容易となり、集積回路を構成する場合に有利となる。Further, since it has a lateral structure, electrode extraction and wiring are easy, which is advantageous when constructing an integrated circuit.
また半絶縁性半導体に構成するので、集積回路−に通用
した場合、素子間のアイソレーションが簡単化される利
益がある。Furthermore, since it is constructed as a semi-insulating semiconductor, there is the advantage that isolation between elements can be simplified when used in integrated circuits.
そして、本発明半導体装置においては、特に第1、第2
及び第3領域(12) 、 (13)及び(14)を
同心的に順次取り囲むように配置形成したので、ベース
電流、コレクタ電流、仮想ベース領域(19)が例えば
第2領域(13)の内側に閉じ込められ、素子内で一様
となる。従って、電流が均一に流れるため高電流、高出
力動作をしたときの素子の破壊が生じに<<、高出力、
ρ1周波用に適した半導体装置が得られる。また、素子
を微小化しても素子間の分離が完全に行なわれ、畠密度
の集積回路に適するものである。In the semiconductor device of the present invention, especially the first and second
and the third region (12), (13), and (14) are arranged concentrically and sequentially surrounding the base current, the collector current, and the virtual base region (19), for example, inside the second region (13). is confined within the element and becomes uniform within the element. Therefore, since the current flows uniformly, the element may be destroyed when operating at high current and high output.
A semiconductor device suitable for the ρ1 frequency can be obtained. Furthermore, even if the elements are miniaturized, the elements can be completely isolated, making it suitable for high-density integrated circuits.
第1図は本発明による半導体装置の一例をボず路線的断
面図、第2図はその路線的な平面図、第3図は本発明の
半導体装置の他の例をネオ路線的平面図、第4図は本発
明の説明に供する半導体装置の路線的断面図、第5図は
その路線的平面図である。
(1■)は半絶縁性半導体、(12) (13)及び
(14)は第11第2及び第3領域、(19)は仮想ベ
ース領域である。
第1図
第2図
113・1FIG. 1 is a cross-sectional view of an example of the semiconductor device according to the present invention, FIG. 2 is a plan view of the same, and FIG. 3 is a plan view of another example of the semiconductor device of the present invention. FIG. 4 is a cross-sectional view of a semiconductor device used for explaining the present invention, and FIG. 5 is a plan view thereof. (1) is a semi-insulating semiconductor, (12), (13) and (14) are the eleventh second and third regions, and (19) is a virtual base region. Figure 1 Figure 2 113.1
Claims (1)
域とコレクタ領域となる第2領域とを所要の間隔を保持
して配置し、該第1及び第2領域間に他の導電型の第3
領域を設け、該第3領域と上記第1領域との間に順バイ
アス電圧を与えて上記第3領域からのその多数キャリア
の注入による仮想ベース領域を上記第3領域及び上記第
1領域間の上記半絶縁性の半導体に形成してバイポーラ
トランジスタ動作を行わしめるようになし、上記第1領
域、第2領域、第3領域が同心的に順次取り囲むように
配置形成されて成る半導体装置。A first region serving as an emitter region of one conductivity type and a second region serving as a collector region are arranged in a semi-insulating semiconductor with a required distance between them, and a conductivity type of another conductivity type is disposed between the first and second regions. Third
A forward bias voltage is applied between the third region and the first region to create a virtual base region between the third region and the first region by injecting majority carriers from the third region. A semiconductor device formed on the semi-insulating semiconductor to perform bipolar transistor operation, and comprising the first region, second region, and third region concentrically surrounding each other in sequence.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59197303A JPS6174368A (en) | 1984-09-20 | 1984-09-20 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59197303A JPS6174368A (en) | 1984-09-20 | 1984-09-20 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6174368A true JPS6174368A (en) | 1986-04-16 |
Family
ID=16372215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59197303A Pending JPS6174368A (en) | 1984-09-20 | 1984-09-20 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6174368A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6611043B2 (en) | 2000-03-15 | 2003-08-26 | Nec Corporation | Bipolar transistor and semiconductor device having the same |
-
1984
- 1984-09-20 JP JP59197303A patent/JPS6174368A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6611043B2 (en) | 2000-03-15 | 2003-08-26 | Nec Corporation | Bipolar transistor and semiconductor device having the same |
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