JPS6159872A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar I-run raster. The present invention relates to a semiconductor device with a special configuration that allows it to operate, particularly to a semiconductor device that is designed to operate at the same speed.

[Conventional technology]

A bipolar transistor as a circuit element of a semiconductor integrated circuit has a so-called lateral structure in which the emitter, base, and collector regions are arranged in a planar manner for the purpose of simplifying manufacturing and wiring patterns. However, this lateral structure bipolar transistor generally has a small current amplification factor β.

[Problem that the invention seeks to solve]

On the other hand, the present applicant previously proposed in Japanese Patent Application No. 58-224841 a semiconductor device which has a lateral structure and operates as a bipolar transistor with a large current amplification factor. As shown in FIG. 3, this semiconductor device has a first region (2) serving as an h-type emitter region and a second region (3) serving as a collector region on the main surface of a semi-insulating semiconductor substrate (1). ) and a P-type third region (4), and an emitter electrode (5), a collector region (6), and a base electrode (7) are formed in each region (2), (3), and (4). It is composed of By applying a forward bias voltage between the first and third regions (2) and (4), the first region (2)
Holes from the third region (4) are injected at a high concentration into the semi-insulating semiconductor substrate +11 between the third region (4) and the third region (4) to form a virtual base region (+1), and the holes are injected from the first region (2). The electrons are attracted by the collector electric field and reach the positively biased second region (3) through the virtual base region (8), thereby performing an npn type bipolar transistor operation.

By the way, in such a configuration, since the collector electric field widely spreads between the virtual base region (8) and the collector electrode (6), electrons also spread and flow inside the semi-insulating semiconductor substrate (1). Therefore, the number of electrons having a long collector transit time increases, which deteriorates the crystal frequency performance of the semiconductor device. In addition, since the electric field is weak inside the semi-insulating semiconductor substrate +1), a phenomenon occurs in which electrons trapped in the electron traps within the semi-insulating semiconductor substrate 11) remain for a long time, resulting in drift and instability of electrical characteristics. It was causing this.

The present invention improves the above-mentioned points in a semiconductor device having a special structure that enables such a bipolar transistor operation, and provides a semiconductor device with improved commercial operation.

Means for Solving Problem c] The present invention provides a semi-insulating semiconductor (13) with a first flJliJ region (14) which becomes an emitter region of one conductivity type and a second region (15) which becomes a collector region. are arranged 61 while maintaining the required spacing, and these first and second areas (14
) and (15), a third region (16) of another conductivity type is provided. Then, by applying a forward bias voltage between the third region (+6) and the first region (step 4), the majority carriers are transferred from the third region (16) to the third region (16) and the first region (14).
The semi-insulating semiconductor region (20) between is implanted, and the region (
A virtual base region (21) is formed in the 11th second and third regions (14) in the present invention to perform bipolar transistor operation.
, 3i (
14) A semiconductor #J region (I2) having a larger energy gap than the semi-insulating semiconductor (13) is provided across (15) and (16). Here, as the semi-insulating semiconductor (13), an m-v group compound semiconductor or a semiconductor having a substantially low current carrier concentration and a high resistance, for example, 10'00 or more, can be used.

[Effect]

half! (!! Extramarginal semiconductor 13) has a virtual base region (2
1), majority carriers injected from the first region (14) reach the second region (15) through the virtual base region (21), and a bipolar transistor operation is performed.

At this time, the 11th second and third areas (14), (1
5) and (16) below the semi-insulating semiconductor (
13) Semiconductor region with larger energy gap (1
2) confines the flow of carriers in the region (13) and prevents them from flowing into the interior of the substrate (if). Therefore, the carrier is the third and second territory JIi (16
), (15), the commercial operation is increased and the electrical characteristics are stabilized. Furthermore, the rate at which carriers reach the collector increases, and the current amplification factor increases.

〔Example〕

An example of a semiconductor device according to the present invention will be described with reference to FIG. In this example, a semi-insulating GaΔ,S semiconductor substrate (11) is provided, and a semiconductor 1d having a larger energy gap than GaAs, for example, I×Ga1−, which is not doped with impurities, is formed by epitaxial growth on the main surface of the semi-insulating GaΔ,S semiconductor substrate (11).
×8! ! A layer (12) (0<x≦1) is formed on the layer (12) by epitaxial growth to make it semi-insulating, that is, the current carrier concentration is substantially low, and the resistance is high, for example, 1ObΩc.
GaAs1i (13) with a thickness of an or more is formed to a required thickness. This semi-insulating GaAs layer (13) - main surface (1
3a), the first and second regions (14
) and (15) are arranged and formed in a plane at a required depth while maintaining a required interval by, for example, an ion implantation method, a diffusion method, or the like. Then, between these first and second regions (14) and (15), a third region (16) having a p-type impurity concentration, for example, is formed by ion implantation, diffusion, etc.
14) It is formed so that it faces the main surface (13a) facing (15) and is juxtaposed with these in a co-Hi plane, and at a shallower depth than these regions (14) and (15). First,
Second and third areas (14), (15) and (1
6) have emitter, collector and base electrodes (1
7), (18) and (19) are ohmically deposited. E, C and B indicate emitter, collector and base terminals, respectively.

In such a configuration, the first and third regions (1
A forward bias voltage is applied between 4) and (16), and a reverse bias voltage is applied between the third and second regions (16) and (15).

In this way, the majority carrier stopper from the third region (16) is transferred to the first region (14) and the third region jli3i (16).
) and under the third region (16).
) is implanted into the crystal resistive region (20) to create a virtual base region (21) there, thereby causing the first region (1
4), the injection of majority carrier electrons is promoted, and these electrons reach the second region (15) through the virtual base region (21), thereby operating an n-p-n type bipolar transistor with a lateral structure.

In this case, the first layer under the semi-insulating GaAsJi (13)
Second and third areas (14), (15) and (16
), the AlGaAs layer (13) has a larger energy gap than the GaAs layer (13) or the AlGaAs layer (13).
(12) is formed, so the flow of electrons is
Confined within the s-layer (13), the flow of electrons into the interior of the substrate (11) is blocked.

In addition, in Fig. 1, it is placed on a semi-insulating GaAs substrate (11).
1)<Gat-×As layer (12) was formed, and semi-insulating GaAs1i (13) was further formed on it, but G
Skip the aAs substrate (11) and connect directly to AIX Gat-x
An As substrate is provided, and semi-insulating GaAs1-
(13) may be formed.

In the example shown in Figure 1, AIX Ga1 with a larger energy gap is placed below semi-insulating GaAs1W (13).
-×As layer (12) is provided, but as shown in FIG.
<In addition to providing the As layer (12), GaAs1W (
13), i.e., the − main surface (13a), is similarly not doped with impurities.
) can also be formed, for example, by heteroepitaxial growth. In this case, the invalid base current on the surface is suppressed.

〔Effect of the invention〕

Although the semiconductor device according to the present invention described above has a lateral structure, it nevertheless has the advantage that its current amplification factor β can be increased. That is, since the base region, that is, the current path by the injected carriers is substantially formed in the semi-insulating region (20) outside the third region (16) having the west impurity concentration, the diffusion of the injected carriers is prevented. It has an extremely long length and is not easily affected by the high recombination rate portion of the semiconductor surface, and furthermore, it does not flow into the third region (16) and the potential barrier of the semi-insulating region (20) is low and flat. This makes it possible to construct a semiconductor device that operates as a bipolar transistor with a high current amplification factor due to the fact that the current flows through a portion that is not easily affected by the collector voltage.

Further, especially when constructed from a compound semiconductor, it is possible to obtain a semiconductor device with even better high-speed operation.

Furthermore, since the substantial base region is formed in a semi-insulating semiconductor, this characteristic is less affected by variations in the depth, characteristics, etc. of the third region (16). A semiconductor device with uniform characteristics can be easily manufactured.

In addition, the first and second areas (16) are
Since 4) and (15) are symmetrical, a transistor can be constructed in which the emitter and collector are symmetrical.

Furthermore, since it has a lateral structure, it is easy to take out the electrodes and wire them, which is advantageous when constructing an integrated circuit. Furthermore, since it is constructed as a semi-insulating semiconductor, there is the advantage that isolation between elements can be simplified when used in integrated circuits.

In the semiconductor device of the present invention, - especially the first, second and third regions (14), (15) and (16)
In (1), a semiconductor region (12) having a larger energy cap than the semi-insulating semiconductor (13) was formed so as to span each of these regions (14), (15), and (1G).
The flow of carriers injected from the region (14) is confined within the semi-insulating semiconductor region (13) and
The flow of Gi and Tria into the interior is stopped.

Therefore, the carrier is in the third and second regions (16).

As the maximum Mhli distance approaches (15), the carrier travel time to the collector becomes shorter and high-speed operability increases.
A semiconductor device with excellent high frequency performance can be obtained. Moreover, the phenomenon in which carriers trapped inside the base body (11) remain for a long time is avoided, and the electrical characteristics are stabilized. Furthermore, the rate at which carriers reach the collector is increased, and the current amplification factor is further improved. Moreover, as shown in FIG. 2, a similar semiconductor region (22
), the ineffective base current at the surface is suppressed and the current amplification factor can be further increased.

[Brief explanation of the drawing]

FIG. 1 is a horizontally enlarged front view of an example of the semiconductor device iII' according to the present invention, and FIG. FIG. 3 is an enlarged cross-sectional view of a semiconductor device used to explain the present invention. (11) is a semi-insulating GaAs substrate, (12) is AI×
S layer to Gat-x, (13) is semi-insulating Ga layer,
(14), (15). (16) are the first, second, and third regions. Agent Italy) 1t Ki Tei 7γ・1. . Between MatsullI! ! Hidemori・'-':”, 1゜Figure 1
“ Figure 2 Figure 3

Claims (1)

[Claims] A first layer that becomes an emitter region of one conductivity type in a semi-insulating semiconductor.
A third region of another conductivity type is provided between the first and second regions, the third region and the first region A forward bias voltage is applied between the third region and the majority carriers injected from the third region to form a virtual base region in the semi-insulating semiconductor between the third region and the first region to operate a bipolar transistor. In order to ensure that the
. A semiconductor device comprising a semiconductor region having a larger energy gap than the semi-insulating semiconductor above and extending over the second and third regions.