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JPS6173302A - Method of producing resistor or circuit board with resistor - Google Patents

Method of producing resistor or circuit board with resistor

Info

Publication number
JPS6173302A
JPS6173302A JP19645684A JP19645684A JPS6173302A JP S6173302 A JPS6173302 A JP S6173302A JP 19645684 A JP19645684 A JP 19645684A JP 19645684 A JP19645684 A JP 19645684A JP S6173302 A JPS6173302 A JP S6173302A
Authority
JP
Japan
Prior art keywords
resistor
electroless
thin film
circuit board
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19645684A
Other languages
Japanese (ja)
Inventor
角橋 武
徹 白木
丹 通雄
保則 杉原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Electric Industrial Co Ltd filed Critical Nitto Electric Industrial Co Ltd
Priority to JP19645684A priority Critical patent/JPS6173302A/en
Publication of JPS6173302A publication Critical patent/JPS6173302A/en
Pending legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は抵抗体又は抵抗体付き回路板の製造方法の改良
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in a method for manufacturing a resistor or a circuit board with a resistor.

先行技術と問題点 第2図Eは抵抗体付き回路板の一例を示し、1′は絶縁
基板を、3′は抵抗層を R/は抵抗体部分を、5′は
回路用導体部分を、4′は絶縁被覆をそれぞれ示してい
る。
Prior Art and Problems Figure 2 E shows an example of a circuit board with a resistor, where 1' is an insulating substrate, 3' is a resistor layer, R/ is a resistor part, 5' is a circuit conductor part, 4' indicates an insulating coating.

従来、かかる抵抗体付き回路板の製造方法として次の方
法が公知である。
Conventionally, the following method is known as a method for manufacturing such a circuit board with a resistor.

まず、第2図Aに示すように絶縁基板1′の表面に無電
解メッキの触媒たるパラジウムを含有するペースト2′
を全面に塗布し、そのうえに、抵抗膜としてニッケルを
主成分とする無電解メッキ薄膜3′を設ける。次に、回
路用導体とすべき部分以外の箇所(第2図已におけるA
′部分)にメツキレシスト4′として耐酸又は耐アルカ
リ性インクを印刷により塗布し、非塗布の露出部分に無
電解メッキ又は電解メッキにより回路用導体部分5′を
形成しく第2図B)、更に、上記メツキレシスト4′を
剥離しく第2図C)、その露出した抵抗膜の抵抗体とす
べき部分(第2図EKおけるR/、 87部分)に耐熱
性インク4/、 a/を印刷により塗布し、これを永久
的被膜にし、而るのち、第2図Eに示すように露出せる
2抵抗膜の不要部分をエツチングにより除去する。
First, as shown in FIG. 2A, a paste 2' containing palladium, which is a catalyst for electroless plating, is applied to the surface of an insulating substrate 1'.
is coated on the entire surface, and an electroless plated thin film 3' mainly composed of nickel is provided thereon as a resistive film. Next, place the parts other than those that should be used as circuit conductors (A in Figure 2).
Acid-resistant or alkali-resistant ink is applied by printing as a mesh resist 4' on the non-applied exposed area (Fig. 2B), and a circuit conductor part 5' is formed by electroless plating or electrolytic plating. Peel off the mesh resist 4' (Fig. 2 C), and apply heat-resistant ink 4/, a/ to the exposed portion of the resistive film that should be used as a resistor (R/, 87 portion in Fig. 2 EK) by printing. This is made into a permanent coating, and then the exposed unnecessary portions of the two-resistance film are removed by etching as shown in FIG. 2E.

しかしながら、この方法により得た抵抗体付き回路板に
おいては、抵抗膜をエツチングして露出させた絶縁基板
表面の絶縁抵抗が相当に低く、抵抗パターン間、回路導
体パターン間等の絶縁性が不十分である。また、メツキ
レシスト4′の剥離の際、剥離液により抵抗膜3′が浸
食され、抵抗値特性が悪化するおそれもある。
However, in circuit boards with resistors obtained by this method, the insulation resistance of the insulating substrate surface exposed by etching the resistive film is considerably low, and the insulation between resistor patterns and circuit conductor patterns is insufficient. It is. Furthermore, when the mesh resist 4' is peeled off, the resistive film 3' may be eroded by the stripping liquid and the resistance value characteristics may deteriorate.

発明の目的 本発明の目的は絶縁基板表面の絶縁抵抗を充分に高く保
持して、抵抗値特性、導体密着強度、耐熱特性、耐湿特
性等の諸特性に秀れた抵抗体付き回路板を製造し得る方
法を提供することにある0 本発明は所定形状の抵抗体部分と電極部分とからなる抵
抗体の製造も包含しており、以下、回路用導体部分とは
電極部分をも含んでいる。
Purpose of the Invention The purpose of the present invention is to manufacture a circuit board with a resistor that maintains sufficiently high insulation resistance on the surface of an insulating substrate and has excellent properties such as resistance value characteristics, conductor adhesion strength, heat resistance characteristics, and moisture resistance characteristics. The present invention also includes the production of a resistor consisting of a resistor part of a predetermined shape and an electrode part, and hereinafter, the term "circuit conductor part" also includes the electrode part. .

発明の構成 本発明に係る抵抗体又は抵抗体付き回路板の製造方法は
、抵抗体部分と回路用導体部分を所定のパターンで絶縁
基板上に形成する抵抗体又は抵抗体付き回路板の製法に
おいて、絶縁基板上に、無電解メッキ触媒を含むペース
トを上記所定のパターン状に印刷し、該ペーストを硬化
後、絶縁基板を無電解メッキ浴中に浸漬して上記所定の
パターン状に無電解メッキの抵抗体薄膜を形成し、該無
電解メッキ薄膜パターンのうち、抵抗体部分を絶縁材料
でカバーコートし、抵抗体部分以外の露出せる無電解メ
ッキ薄膜パターン上に無電解又は電解メッキを行い、上
記の電極部分または回路用導体部分を形成することを特
徴とする方法である。
Structure of the Invention A method for manufacturing a resistor or a circuit board with a resistor according to the present invention is a method for manufacturing a resistor or a circuit board with a resistor in which a resistor portion and a circuit conductor portion are formed in a predetermined pattern on an insulating substrate. , a paste containing an electroless plating catalyst is printed in the predetermined pattern on the insulating substrate, and after curing the paste, the insulating substrate is immersed in an electroless plating bath to perform electroless plating in the predetermined pattern. forming a resistor thin film, cover-coating the resistor part of the electroless plated thin film pattern with an insulating material, and performing electroless or electrolytic plating on the exposed electroless plated thin film pattern other than the resistor part, This method is characterized by forming the above electrode portion or circuit conductor portion.

実施例の説明 以下、図面により本発明を説明する。Description of examples The present invention will be explained below with reference to the drawings.

第1図Aにおいて、1は絶縁基板、2は抵抗体部分と回
路用導体部分との合体パターンであり、本発明を実施す
るには、まず、絶縁基板lの表面に、無電解メッキの触
媒たるパラジウムを含有するペーストを上記の合体パタ
ーン2で印刷により塗布し、このペーストの硬化後、基
板ヲニッケル系の無電解メッキ浴に浸漬し、第1図Bに
示すようにパターン状にニッケル系無電解メッキ薄膜を
成長させる。
In FIG. 1A, 1 is an insulating substrate, and 2 is a combined pattern of a resistor portion and a circuit conductor portion. After the paste is cured, the substrate is immersed in a nickel-based electroless plating bath and coated with nickel-based non-nickel in a pattern as shown in Figure 1B. Growing electrolytically plated thin films.

次に、この合体パターンのうち、第1図Cに示すように
抵抗体相当箇所(回路抵抗体とすべき箇所)K−耐熱性
の絶縁性インク4を印刷まだはフォトプロセス・により
塗布して永久被覆する。
Next, as shown in FIG. 1C in this combined pattern, heat-resistant insulating ink 4 is applied to the resistor-equivalent portions (the portions that should be used as circuit resistors) by a photo process. Permanently cover.

この被覆膜は、薄膜抵抗体のカバーコートと共に次工程
である回路用導体部分を形成するだめの銅メッキのメツ
キレシストを兼ねるものである。
This coating film serves as a cover coat for the thin film resistor as well as a resist for the copper plating that will form the circuit conductor portion in the next step.

絶縁性インクの永久被覆を設けたのちは、基板を希塩酸
水に室内で数分間浸漬して薄膜パターン表面の酸化膜を
除去したのち、無電解銅メッキ浴に浸しガルバニックな
処理を行い露出している薄膜パターンの表面に第1図り
に示すように無電解銅メッキ膜で回路用導体部分5を形
成する。
After applying a permanent coating of insulating ink, the board was immersed indoors in dilute hydrochloric acid for several minutes to remove the oxide film on the surface of the thin film pattern, and then immersed in an electroless copper plating bath for galvanic treatment and exposed. A circuit conductor portion 5 is formed on the surface of the thin film pattern using an electroless copper plating film as shown in the first diagram.

上記酸化膜の除去後、パラジウム−塩酸系希釈液に浸漬
し、薄膜パターンの表面のみを活性化し、而るのち、上
記の無電解銅メッキを行うようにしてもよい。このパラ
ジウムによる活性化処理は、パラジウム液の濃度をある
濃度範囲以下に保つことにより選択的に薄膜パターン上
にのみ無電解銅を析出させ得る。パラジウム液のパラジ
ウム原子濃度範囲は1.4 X 10−′自主4.2X
 10−’ atom /lである。
After the oxide film is removed, only the surface of the thin film pattern may be activated by immersing it in a palladium-hydrochloric acid diluted solution, and then the electroless copper plating described above may be performed. This activation treatment with palladium can selectively deposit electroless copper only on the thin film pattern by keeping the concentration of the palladium solution below a certain concentration range. The palladium atom concentration range of palladium liquid is 1.4 x 10-' independent 4.2 x
10-' atoms/l.

上記無電解メッキ法に代え、薄膜パターンに直接、電解
銅メッキを施すこともでき、上記の無電解銅メッキを行
ったのち、更に、その上に電解銅メッキを行いメッキ厚
みを増大させることもできる。回路導体に比較的大きな
電流を流す必要のある用途においては、電解銅メッキに
よる膜厚の厚い回路導体を用いることが望ましい。ただ
し、パラジウムによる活性化処理の無電解メッキによる
以外のメッキ法においては、導体の各パターンを何んら
かの方法で互に電気的に連絡してメッキを行うので、メ
ッキ後、ドリル穴あけ、金型パンチング等により不要部
分の連絡を断つ必要がある。
Instead of the electroless plating method described above, it is also possible to apply electrolytic copper plating directly to the thin film pattern, and after performing the above electroless copper plating, it is also possible to further increase the plating thickness by performing electrolytic copper plating on top of it. can. In applications that require a relatively large current to flow through a circuit conductor, it is desirable to use a thick circuit conductor formed by electrolytic copper plating. However, in plating methods other than electroless plating activated by palladium, plating is performed by electrically connecting each pattern of the conductor to each other in some way, so after plating, drilling, drilling, etc. It is necessary to disconnect unnecessary parts by punching the mold or the like.

なお、第1図りのe −e断面を示す第1図Eから明ら
かなように回路用導体部分5とカバーコート4とは突合
せ状態で接合している。この突合せ箇所を覆うように第
1図Fに示すように第2のカバーコート6を施せば、抵
抗体をより完全に被覆できる。第1図E並びに第1図F
において、lは絶縁基板、2は無電解メッキ触媒を含む
ペーストの印刷層、3は無電解メッキ薄膜の抵抗体であ
る。
As is clear from FIG. 1E, which shows the e-e cross section of the first diagram, the circuit conductor portion 5 and the cover coat 4 are joined in a butt state. By applying a second cover coat 6 as shown in FIG. 1F to cover this abutment location, the resistor can be more completely covered. Figure 1 E and Figure 1 F
In the figure, l is an insulating substrate, 2 is a printed layer of paste containing an electroless plating catalyst, and 3 is a resistor made of an electroless plated thin film.

上記において絶縁基板には紙−フェノール樹脂基板、紙
−エポキシ樹脂基板、ガラス−エポキシ樹脂基板、金属
支持体−合成樹脂表面被覆基板、及びセラミックス基板
等を用いることができる。
In the above, the insulating substrate may be a paper-phenol resin substrate, a paper-epoxy resin substrate, a glass-epoxy resin substrate, a metal support-synthetic resin surface-coated substrate, a ceramic substrate, or the like.

上記パラジウム含有ペーストの組成とし、ては、例えば
、 アクリロニトリルブタジェンゴム     100部フ
ェノール−フォルムアルデヒド樹脂50 〃ジルコニウ
ムンリケイト    20〃ソ           
 リ             カ         
    5 〃の樹脂組成に対し、パラジウム元素換算
で1乃至7重量%の範囲で金属Pd、 Pdcl、、、
 PdI、、 Pd(N”3)2及びPdoを含み、固
形分0度が35乃至40重量%になるようセロンルプア
セテートを含むものが適している〇 薄膜用の無電解メッキ浴としては、N1−P、N1−C
o−P    N1−Fe−P    Ni−3n−P
   N1−Zn−P、 N1−W−P、 Ni−Cr
、 N1−B等のニッケル系浴を使用できる。メンキレ
ジストを兼ねる薄膜抵抗体のカバーコート材料としては
、エポキシ−イミダゾール系等のエポキシ系ンルダーペ
ーストを使用できる。
The composition of the palladium-containing paste is, for example, 100 parts of acrylonitrile butadiene rubber, 50 parts of phenol-formaldehyde resin, 20 parts of zirconium silicate, and 100 parts of acrylonitrile butadiene rubber.
Rika
5 Metallic Pd, Pdcl, etc. in a range of 1 to 7% by weight in terms of palladium element with respect to the resin composition
A bath containing PdI, Pd(N"3)2, and Pdo, and containing selonlupe acetate so that the solid content is 35 to 40% by weight is suitable. As an electroless plating bath for thin films, N1 -P, N1-C
o-P N1-Fe-P Ni-3n-P
N1-Zn-P, N1-W-P, Ni-Cr
, N1-B, or other nickel-based baths can be used. As a cover coat material for the thin film resistor that also serves as a Menki resist, an epoxy-based resin paste such as epoxy-imidazole can be used.

メツキレシストを塗布後露出している薄膜パターン上に
行う無電解銅メッキのガルバニックなメッキ開始法とし
ては、薄膜パターンの一部を鉄片で接触するか、電池又
は整流器により瞬間的て電解を行うことにより行われる
。メツキレシスト塗布後の薄膜パターンの選択的なパラ
ジウムによる活性処理法としては、下記処決の液に Pd c120.1〜0.31 37%Hcl    1oml 水              41 室温で10秒間浸漬すればよい。これ以上のPdCl2
の濃度では、メツキレシスト上にも銅メッキが生成する
ことがあり適当でない。薄膜パターンへの直接の、又は
無電解銅メッキ膜への電解銅メッキの浴としては、通常
の硫酸銅浴を使用できる。
To start galvanic electroless copper plating on the exposed thin film pattern after applying Metsukiresist, contact a part of the thin film pattern with an iron piece, or perform instantaneous electrolysis using a battery or rectifier. It will be done. As a method of selectively activating the thin film pattern with palladium after coating the metskiresist, it may be immersed in the following treatment solution for 10 seconds at room temperature: Pd c120.1-0.31 37% HCl 1 oml Water 41. No more PdCl2
At a concentration of , copper plating may also be formed on the metal resist, which is not appropriate. A normal copper sulfate bath can be used as a bath for electrolytic copper plating directly on a thin film pattern or on an electroless copper plating film.

次に、本発明の実施例について説明する。Next, examples of the present invention will be described.

実施例1 ガラス−エポキシ樹脂基板の片面に、下記配合のパラジ
ウム含有インクを合体パターンにスクリーン印刷したの
ち、170°C960分間加熱硬化した。
Example 1 A palladium-containing ink having the following composition was screen-printed in a combined pattern on one side of a glass-epoxy resin substrate, and then cured by heating at 170° C. for 960 minutes.

アクリロニトリルブタジェンゴム     100部フ
ェノール−フォルムアルデヒドm1lFr      
 50 gジルコニウムシリケイ)     201シ
           リ            カ
            5 〃金  属  パ  ラ
   ジ  ウ  ム          9Iセロソ
ルブアセテート   340〃 この基板を下記配合の無電解メッキ浴に浸し、下記条件
でメッキを行いパターン化したインク上に薄膜を生成さ
せたのち水洗し乾燥した。
Acrylonitrile butadiene rubber 100 parts phenol-formaldehyde ml Fr
50 g zirconium silica) 201 Silica 5 Metal Palladium 9I cellosolve acetate 340 This substrate was immersed in an electroless plating bath with the following composition, and plated under the following conditions to form a thin film on the patterned ink. was formed, then washed with water and dried.

塩化ニッケル、6水和物     :xor/gヒドロ
キシ酢酸   39〃 水 酸 化 す  ト  リ  ウ  ム      
      20  〃次亜リン酸ナトリウム    
 10  pPH4,4〜4.8(20℃) 温度         60℃ メッキ時間      60秒 得られた薄膜の成分は、リン含量10%の1゛1〕−P
であった。
Nickel chloride, hexahydrate: xor/g hydroxyacetic acid 39〃 Water oxide Thorium
20 Sodium hypophosphite
10 pPH 4.4 to 4.8 (20℃) Temperature 60℃ Plating time 60 seconds The components of the obtained thin film were 1゛1〕-P with a phosphorus content of 10%.
Met.

次に、得られだN i −P薄膜パターンのうち、抵抗
体相当個所にエポキシ系の絶縁性インク(フォトサーキ
ット社製pc4ol)をスクリーン印刷し、カバーした
のち130℃、60分間加熱硬化した。更にこの基板を
10%の塩酸水に、25℃で、60秒間浸漬後水洗した
のち、下記配合の無電解銅メッキ浴に浸し、下記条件で
メッキを行い、露出しているN1−Pパターンの表面に
無電解銅メッキ膜を生成させたのち水洗し、乾燥した。
Next, an epoxy-based insulating ink (PC4OL manufactured by Photocircuit Co., Ltd.) was screen printed on the portions of the obtained N i -P thin film pattern corresponding to the resistor, covered, and then heated and cured at 130° C. for 60 minutes. Further, this board was immersed in 10% hydrochloric acid water at 25°C for 60 seconds and then washed with water, and then immersed in an electroless copper plating bath with the following composition and plated under the following conditions to remove the exposed N1-P pattern. After forming an electroless copper plating film on the surface, it was washed with water and dried.

硫     酸     銅        3oP#
炭酸水素ナトリウム     30 l酒石酸ナトリウ
ム    1001 水酸化ナトリウム    50〃 37%ホルマリン液     30rrLl/lPH1
1,5(25℃) 温度        25℃ メッキ時間     50秒 尚、メッキの開始は、外部電源によるガルバニック処理
によった。
Sulfuric acid copper 3oP#
Sodium hydrogen carbonate 30 l Sodium tartrate 1001 Sodium hydroxide 50 37% formalin solution 30rrLl/lPH1
1.5 (25° C.) Temperature: 25° C. Plating time: 50 seconds The plating was started by galvanic treatment using an external power source.

更に、上記と同様のエポキシ絶縁インクを、抵抗体と電
極境界部をカバーするように重ねてスクリーン印刷し、
同様に加熱硬化し、更に170℃、60分加熱して抵抗
体の特性を安定化後基板周辺の不要部分を金型で切断除
去して薄膜抵抗体付き回路板が完成した。
Furthermore, the same epoxy insulating ink as above was layered and screen printed to cover the resistor and electrode boundary.
After curing by heating in the same manner and further heating at 170° C. for 60 minutes to stabilize the characteristics of the resistor, unnecessary portions around the substrate were cut and removed using a mold to complete a circuit board with a thin film resistor.

得られた抵抗体の特性は下表の通りであり、絶縁基板の
露出表面の絶縁抵抗は5 X I O13〜5X 10
”Ωであった。これに対し、既述の従来法では5 X 
I O”Ωであった。
The properties of the obtained resistor are as shown in the table below, and the insulation resistance of the exposed surface of the insulating substrate is 5X I O13 to 5X 10
”Ω.On the other hand, in the conventional method described above, 5
It was IO”Ω.

第1表 シート抵抗値         3QOΩ/口抵抗温度
係数(−55℃〜+120℃) + 70 ppm7℃
耐熱特性(70℃、無負荷、500hr後の抵抗変化率
)0.5%耐湿特性(40℃、相当湿度95%、無負荷
、 24Ohr後の抵抗変化率)0.5% 半田耐熱(260℃、20秒間浸漬後の抵抗変化率) 
   0.3’?6導体密着強度         6
00  ?/an実施例2 アルミ板の表面に厚み約50μのエポキシ系塗料を塗布
して製作した基板の片面に実施例1と同様のパラジウム
含有インクをスクリーン印刷し、抵抗体、回路導体の合
体パターンを形成し、同様の条件で加熱硬化した。この
基板を下記の配合の無電解メッキ浴に浸し、同様にパタ
ーン化したインク状に薄膜を生成させ、水洗し乾燥した
Table 1 Sheet resistance value 3QOΩ/mouth resistance temperature coefficient (-55℃~+120℃) + 70 ppm 7℃
Heat resistance (70℃, no load, resistance change rate after 500 hours) 0.5% Moisture resistance (40℃, equivalent humidity 95%, no load, resistance change rate after 24Ohr) 0.5% Solder heat resistance (260℃) , resistance change rate after immersion for 20 seconds)
0.3'? 6 Conductor adhesion strength 6
00? /an Example 2 The same palladium-containing ink as in Example 1 was screen printed on one side of a board made by applying epoxy paint to a thickness of about 50 μm on the surface of an aluminum plate to form a combined pattern of resistors and circuit conductors. It was formed and heat-cured under the same conditions. This substrate was immersed in an electroless plating bath having the following composition to form a similarly patterned ink-like thin film, which was washed with water and dried.

硫  酸  第   1  鉄       40 グ
/l硫酸ニッケル・6水和物     26 Iクエン
酸ナトリウム・2水和物      741次亜リン酸
ナトリウム    21 1硼           
   酸        30   !PM(9,0(
25℃) 温度        90℃ メッキ時間     15分 得られた薄膜の成分はN1−Fe−Pでbった。
Sulfuric acid Ferrous 40 g/l Nickel sulfate hexahydrate 26 I Sodium citrate dihydrate 741 Sodium hypophosphite 21 1 Boron
Acid 30! PM(9,0(
25°C) Temperature: 90°C Plating time: 15 minutes The composition of the obtained thin film was N1-Fe-P.

次に実施例1と同様に、抵抗体相当個所に、絶縁性イン
クを印刷し、加熱硬化し、薄膜パターンの露出部分に同
様の無電解銅メッキを5分間行った。尚、無電解銅メッ
キの開始処理としては、下記の配合及び条件によるパラ
ジウム活性処理を採用した。
Next, in the same manner as in Example 1, an insulating ink was printed on the portion corresponding to the resistor and cured by heating, and the exposed portion of the thin film pattern was similarly electroless copper plated for 5 minutes. In addition, as a starting treatment for electroless copper plating, palladium activation treatment according to the following formulation and conditions was adopted.

塩化パラジウム         0.2 ?/l塩 
  酸         101 水                4g温     
   度          25 ℃浸  漬  時
  間          10 秒次に、更にこの無
電解銅メッキ膜上に、硫酸銅系のメッキ浴を用いて電解
銅メッキを行い、導体の厚みを20μにした。次に前述
のエポキシ絶縁インクを重ねてスクリーン印刷し、抵抗
体と導体境界部もカバーし、基板周辺の不要部分を金型
で切断除去して抵抗体付き回路板が完成した。
Palladium chloride 0.2? /l salt
Acid 101 Water 4g warm
Next, electrolytic copper plating was performed on the electroless copper plating film using a copper sulfate-based plating bath to give a conductor thickness of 20 μm. Next, the aforementioned epoxy insulating ink was layered and screen printed to cover the boundary between the resistor and the conductor, and unnecessary parts around the board were cut and removed using a mold to complete the circuit board with the resistor.

得られた抵抗体の特性は下記の通りであり、絶縁基板の
露出表面の絶縁抵抗は5×1013〜5X 10”Ωで
あった。
The characteristics of the obtained resistor were as follows, and the insulation resistance of the exposed surface of the insulating substrate was 5×10 13 to 5×10”Ω.

第2表 シート抵抗値         400  Ω/口抵抗
温度係数(−55℃〜+120℃) + 70 ppm
7℃耐熱特性(70℃、 :aWatt/c++!抵抗
体面積、500hr後の抵抗変化率)        
    0・3 %耐湿特性(40℃、相当湿度95%
無負荷24Ohr後の抵抗変化率)0.5  % 半田耐熱(260℃、20秒間浸漬後の抵抗変化率)0
.3 % 導体密着強度           600 f/an
発明の効果 上述した通9本発明に係る抵抗体又は抵抗体付き回路板
の製造方法によれば、絶縁基板の露出表面の絶縁抵抗を
高く保持し得、かつ導体密着強度に秀れた抵抗体又は抵
抗体付き回路板を製造できる。また、剥離液を使用しな
くても済むから、剥離液による抵抗膜の浸食を排除でき
、良好な抵抗特性を確保できる。
Table 2 Sheet resistance value 400 Ω/mouth resistance temperature coefficient (-55℃~+120℃) + 70 ppm
7℃ heat resistance characteristics (70℃, :aWatt/c++!Resistor area, resistance change rate after 500hr)
0.3% moisture resistance (40℃, equivalent humidity 95%)
Resistance change rate after 24 Ohr with no load) 0.5% Soldering heat resistance (resistance change rate after immersion at 260°C for 20 seconds) 0
.. 3% Conductor adhesion strength 600 f/an
Effects of the Invention As mentioned above, according to the method for manufacturing a resistor or a circuit board with a resistor according to the present invention, the resistor can maintain high insulation resistance on the exposed surface of an insulating substrate and has excellent conductor adhesion strength. Alternatively, a circuit board with a resistor can be manufactured. Furthermore, since there is no need to use a stripping solution, erosion of the resistive film by the stripping solution can be eliminated, and good resistance characteristics can be ensured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A1第1図B1第1図C並びに第1図りは本発明
に係る抵抗体又は抵抗体付き回路板の製造方法の作業手
順を示す説明図、第1図Eは第1図りにおけるe−e断
面説明図、第1図Fは本発明の別実施例を示すだめの説
明図、第2図A1第2図81第2図01第2図り並びに
第2図Eは従来の抵抗体付き回路板の製造方法の作業手
順を示す説明図である。 図において、1は絶縁基板、2はペースト印刷層、3は
無電解メッキの抵抗薄膜、4はカバーコート、5はメッ
キ導体層である。 rノ(Br 0       Li2 ミ     陶
Figure 1 A1 Figure 1 B1 Figure 1 C and the first diagram are explanatory diagrams showing the working procedure of the method for manufacturing a resistor or a circuit board with a resistor according to the present invention, and Figure 1 E is e in the first diagram. -e cross-sectional explanatory diagram, Fig. 1 F is an explanatory diagram showing another embodiment of the present invention, Fig. 2 A1 Fig. 2 81 Fig. 2 01 Fig. 2 and Fig. 2 E are conventional resistor-equipped diagrams. FIG. 3 is an explanatory diagram showing a working procedure of a method for manufacturing a circuit board. In the figure, 1 is an insulating substrate, 2 is a paste printing layer, 3 is an electroless plated resistive thin film, 4 is a cover coat, and 5 is a plated conductor layer. rノ(Br 0 Li2 Mi Sue

Claims (1)

【特許請求の範囲】[Claims] 抵抗体部分と抵抗体の電極部分又は回路用導体部分を所
定のパターンで絶縁基板上に形成する抵抗体又は抵抗体
付き回路板の製法において、絶縁基板上に、無電解メッ
キ触媒を含むペーストを上記所定のパターン状に印刷し
、該ペーストを硬化後、絶縁基板を無電解メッキ洛中に
浸漬して上記所定のパターン状に無電解メッキの抵抗体
薄膜を形成し、該無電解メッキ薄膜パターンのうち抵抗
体部分を絶縁材料でカバーコートし、抵抗体部分以外の
露出せる無電解メッキ薄膜パターン上に無電解又は電解
メッキを行い、上記の電極部分または回路用導体部分を
形成することを特徴とする抵抗体又は抵抗体付き回路板
の製造方法。
In a method for manufacturing a resistor or a circuit board with a resistor in which a resistor part and an electrode part of the resistor or a circuit conductor part are formed on an insulating substrate in a predetermined pattern, a paste containing an electroless plating catalyst is applied on the insulating substrate. After printing the paste in the predetermined pattern and curing the paste, the insulating substrate is immersed in an electroless plating solution to form an electroless plated resistor thin film in the predetermined pattern. The resistor part is cover-coated with an insulating material, and electroless or electrolytic plating is performed on the exposed electroless plating thin film pattern other than the resistor part to form the above-mentioned electrode part or circuit conductor part. A method for manufacturing a resistor or a circuit board with a resistor.
JP19645684A 1984-09-18 1984-09-18 Method of producing resistor or circuit board with resistor Pending JPS6173302A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19645684A JPS6173302A (en) 1984-09-18 1984-09-18 Method of producing resistor or circuit board with resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19645684A JPS6173302A (en) 1984-09-18 1984-09-18 Method of producing resistor or circuit board with resistor

Publications (1)

Publication Number Publication Date
JPS6173302A true JPS6173302A (en) 1986-04-15

Family

ID=16358109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19645684A Pending JPS6173302A (en) 1984-09-18 1984-09-18 Method of producing resistor or circuit board with resistor

Country Status (1)

Country Link
JP (1) JPS6173302A (en)

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