JPS6163062A - field effect transistor - Google Patents

Abstract

PURPOSE:To contrive to reduce the gate resistance and the capacity between the source and the gate by a method wherein one electrode pad is disposed on the surface of a recessed part, by which the active layer is isolated on both sides of the right and left, and plural gate electrodes are respectively disposed toward each active layer on both sides of the right and left from this pad. CONSTITUTION:A buffer layer 2 with a low carrier concentration is deposited on a semiconductor substrate 1 and an active layer 3 is deposited thereon. Each recessed part 7 is one that makes the layer 3 isolate on both sides of the left and right and the recessed parts 7 are provided in such a way as to reach the layer 2. gate electrodes 51a and 52a are both disposed on a region of the layer 3, where are held between a source electrode 4a and a drain electrode 6a, and the electrodes 51a and 52a are both connected to one bonding pad 9 for gate electrode, which is arranged on the surface of the layer 2 in the recessed part 7. This pad 9 is connected to gate electrodes 51b and 52b, which are provided on an active layer 3b on the right side of the pad 9, in the same manner. The plural gate electrodes are respectively disposed in an isolated condition on both sides of the right and left to the pad 9 in such a way, and at the same time, the pad 9 is disposed on the layer 2 with a low carrier concentration only one in number. As a result, the gate resistance and the capacity between the source and the gate can be reduced.

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a compound semi-integrated MInBFET (Metal!8
emiconductor F'ie,'d Effe(
This relates to the '4 field effect transistor of Jt Transiator) 4.

(0) Conventional technology This type of field effect transistor, especially ()aAsFET
The minimum noise figure (NFmin) of is expressed by the following formula.

NFm1n-1++-f-OyRp completion/1) ynHere, Kl is the fixed frequency, f is the operating frequency a%ays is the gate frequency.
Source-to-source objective, F# is gate metal resistance, R8 is source-to-source
The inter-gate resistance of 1 gm is mutual conductance. Ra
Miorowa by ymond S, Pen/eeJy
ve Pie/d-Effect Transisto
r-TheOr7+DeSIPn and AppI!
10ations'(RE8RROH8TUDI18
PRFi88゜1982q (H:@) One of the process and pattern designs for reducing the gate resistance is configuring two or more gates (for example, four) in order to reduce the gate resistance Rf. It is known. FIGS. 3 and 4 show a typical conventional field effect transistor in a plane and a B-B'iMt plane 7. On the photo-insulating substrate (0), which is a compound semiconductor material (G to As), there is a buffer layer (with a gear 1) with a small concentration of mesa (with a mesa 4 structure) through a buffer layer (Bl). On the surface of the operation j threat TEI, VC is divided into three source electrodes (r81) (S2) (35) and four gate electrodes (G+) (G2) (Gs) which are divided into four.
(G4) and the drain electrode (D+ 1
(Dg). Two gate electrodes (G1)
(Gt) and [G5) (Oa) are the buffer layer (
Two bonding pads (PI 1
When the source, gate, and drain electrodes, which are connected to (Pz ) and are separately discussed, are combined into one source, gate, and drain lead in the casing, the gate metal resistance Ry is is divided into four parts and placed in parallel with the input signal, making it smaller. Therefore, the minimum noise figure can be reduced. Another important thing in gate pattern formation is the idea of reducing the gate/source question 30Ps.

Therefore, it is important to shorten the gate length (width of gate 1 m in the direction connecting the source and drain) to 1 micron or less, and this has already been done. Furthermore, this capacitance CIs is
This phenomenon occurs both in the sheet gate electrode region formed in the active layer between the drains and in the bonding pad region for the gate electrode formed on the region (buffer layer) from which the active layer is removed. Generally, this capacitance fIkCps is determined by the area of the gate electrode or pad region t, the area of the metal constituting it, and the carrier concentration under the metal.When the 0 area is small and the carrier concentration is low, this gate-source capacitance 0fsf
Can be made smaller. The carrier concentration of the capacitive component in the pad region is at least 3 to 4 orders of magnitude lower than that of the active layer, so it does not reach a value much larger than 0.0.
Since it is about 10 to 0.20 pF, it does not pose a problem if the gate electrode has a large area and the capacitance component under the electrode is large. However, the gate length is sufficiently small (e.g. α5 μm)
(below) and the area of the gate electrode becomes smaller, the capacitance component below the gate becomes significantly smaller (for example, when the carrier concentration in the active layer is 2 m, it becomes approximately [1) 5 pF'), and approaches the capacitance component of the pad region. Therefore.

In order to further reduce the minimum noise figure, it is necessary to further reduce the capacitive component of this pad area. The minimum area of the pad area is limited by bonding conditions and is currently approximately 5 oxso.
It is μ〃l.

C1 Invention 7: Problems trying to resolve J column γ In the conventional example described above, the gate electrode is divided into four parts, which can contribute to reducing the gate total bending resistance Ry, but on the other hand, the bonding pad area for the gate quadrupole There was a limit to reducing the gate-source capacitance Oy3 because it required dispersion of the gate-source capacitance Oy3 in two locations.1 The present invention uses a new electric field configuration that reduces the gate metal resistance Rf and the gate-to-saune response rate by nine times. Means for Solving the Problems of Effect Transistor T-Means for Solving the Problems The present invention provides an electrode pad disposed on the surface of a recess that separates the active layer into left and right sides, and Each of the above operations td
This is a single field effect transistor in which a plurality of gate electrodes are arranged in each direction.

The active layer is formed on a semi-insulating substrate (resistivity P-~10Ω-1) made of a compound semiconductor material (GaA3) and a buffer layer having a carrier concentration of 5XiQ"3-' or less. In addition, the plurality of gate poles is composed of four gate poles, two for each of the left and right active layers.The active layer is made of GaAs with a carrier concentration of 1 to 3×10 -5, and the gate electrode is the gate electrode. It is characterized by its electrode characteristics being of the Schottkyparian type.

(E) Function The present invention differs from the MESF'ET by dividing the gate 4 into a plurality of parts, so that the gate metal resistance R2 can be reduced, contributing to a reduction in the minimum noise figure. In addition, it is sufficient to provide only one bonding cap for the gate terminal for the subsequent gate VC for each of these gates on the layer 2) with a small carrier intensity, so the gate Source 91 Toda Cps gold can be made smaller, and the minimum frequency index gold A can be made much smaller.

N-A Example: X1E is a partial plan view of a single field effect transistor of the present invention, and Figure J2 is a cross-sectional view taken at A- in Figure G1. In the figure, (1) is a 4-dimensional substrate, (2) a buffer r, 1.
+31rj motion 1 乍ノ3. (41 (51t) (31r) are the source, gate, and drain electrodes, respectively.

The semi-insulating substrate +1) is made of an aAs compound semiconductor (with a resistivity of up to about 10 Ω1). Buffer Jf2) has carrier 7.5rl fnl on this semi-insulating substrate (1).
It is formed by depositing a small amount of GaAs (tl) to a thickness of 2 to 3 μm. The active layer 1.1) has a carrier Ia degree (nl is 1 to 3x
caxss with a thickness of 10 n and a thickness tl) of 0.
Lay it out so that it has a shoulder height of 15 to 150 μm! It will be constructed and contributed. Apart from this example and V, there is a VC on this operating layer -7
Even if the carrier concentration is lXiQ18f:'18-s-b17)n+AJt.

Each deposition method includes two-phase epitaxial growth method,
An ion implantation method such as a 1 molecule 4 electron injection method (!14Bg) can be used.

The recess (7) divides the operation iT4+ (I into left and right parts), and the recess (7) is provided so as to touch the buffer layer (2) as shown in the figure. A recess 81 (81) is provided outside the right active layer (3b) to separate the source and drain, and this recess is also configured to reach the buffer ta (2). The gate and drain two poles (,41+51+61 are arranged symmetrically on the left and right active layers (3a) and (5b). Let's explain about yoi (subscript a is added. Subscript s indicates the corresponding point on the right side).The source 1 pole (4a) is in the recess (8)
It is formed in a C-shape surrounding the source αi (41a), (a2a) and the Johannian movement period (5a).
They are arranged opposite each other at the upper and lower positions of the upper and lower positions. The drain 4 poles (6a) are connected to this lip (41pi) (A2pl)
F! As shown in the figure, there is an opening facing the source electrode (4a) @(61al(,6
2a) f7I: Arranged to hold. Source'I
ll (Aa) and drain (6a) are active layer (3
a) Gold 4, which exhibits ohmic properties with respect to K, for example, Au-
It is made of Cu8 alloy.

Gate: Il, pole (51a) (52a) LisofLsofL'/-"R,% (A a I FIL and Dray: /1jiJ (6a) Each gate 1 (51a) (52a) is connected to one gate electrode bonding pad 19) arranged on the surface of the para-edge layer (2) in the recess (7). - The positive electrodes (51a) and (52a) are made of, for example, AI!, in which the conductive metal element exhibits a Schottky barrier property with respect to the active layer (3a).

The above pad (9) is placed on the right side active layer (3b).
To the gate 4 (51b1 (52b) are both exposed, one pad (9) is attached to each of the left and right operating layers (5a) (5b).
A plurality of (two in the embodiment) gate electrodes are provided respectively toward the gate electrode A.

Left and right movement 1/I: The source and drain electrodes on the layer (Sa) (3b) are respectively 5i 1). , and pad (91 is the gate lead,
Aa and packaged.

The above description has been made with reference to the example of CkaAak158BFET, but since the present invention has a special feature in the gate electrode pattern on the semiconductor surface, it can also be applied to MESFET using t- other than Ga^S, for example. Engineering nP+InGa
It is obvious that the present invention can also be applied to a Li-V group compound semiconductor such as As.

()) The field effect transistor of the present invention has a gate electrode divided into a plurality of electrodes (for example, four electrodes), and a bonding pad for relaying each gate 41 to an external gate lead. Since it is configured so that only one is placed on the small h buffer Pjij, the gate metal is 1f.
Both the i-resistance R9 and the source-to-gate gQcPs can be made small, and as a result, the minimum noise figure can be made small.

[Brief explanation of the drawing]

FIG. 1 is a partial plan view of a field effect transistor of the present invention;
The second area is a sectional view taken along the line Ap in FIG. 1, and FIG. 3 is a partial plan view of a typical conventional MISFET. No. 41 is the BB' cross section (■) in FIG. C3) - Operating layer, (9) - 400 million pads, (4)
(51 (63-... source, gate, drain electrode,
+71...Four parts, (2)...Buffano■

Claims (5)

[Claims] (1) A field effect transistor in which one electrode pad is arranged on the surface of a recess that separates the active layer into left and right parts, and a plurality of gate electrodes are arranged from the electrode pad toward each of the active layers. (2) The field effect transistor according to claim (1), wherein the surface of the recess is formed of a buffer layer on a semi-insulating substrate made of a compound semiconductor material. (3) The buffer layer has a carrier concentration of 5×10^1^
The field effect transistor according to claim 2, which has a layer thickness of 5 cm^-^3 or less and a layer thickness of 2 to 3 μm. (4) The field effect transistor according to claim (1), wherein the plurality of gate electrodes are comprised of four gate electrodes, two for each left and right active layer. (5) The field effect transistor according to claim (1), wherein the active layer is a GaAs layer, and the gate electrode has Schottky barrier type electrode characteristics.