JPS60137071A - Schottky gate field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a Schottky gate field effect transistor suitable for ultra-high speed and ultra-high frequency operation.

[Background technology]

Schottky gate field effect transistor (MESF)
[abbreviated as ET] has been praised as an excellent amplification or oscillation element, especially at ultra-high frequencies. It is also well known that it is an excellent basic component for integrated circuits operating at ultra-high speeds.

The structure of the MESFET most commonly used in the past is as shown in FIG.

Here, 1 is a high resistivity or semi-insulating semiconductor crystal substrate, 2
is a conductive semiconductor crystal layer called a normal operation layer.

5 is a Schottky gate electrode, and 3 and 4 are a drain electrode and a source electrode, respectively, having ohmic characteristics.

One of the drawbacks of the conventional structure as shown in FIG. Its value is such that it cannot be ignored.

When the ME S FET is used in an actual amplifier circuit or logic circuit, due to the well-known Miller effect, when viewed from the input circuit side, this Cgd becomes a value that is effectively multiplied by the amplification gain, which increases the high speed and high frequency of the circuit. impede movement. For this reason, it is desirable to make Cgd as small as possible.

Next, FIGS. 2 and 3 show examples in which Cgd is the main term that determines the characteristics of a very commonly used circuit.

FIG. 2 shows a source follower amplifier circuit.

FIG. 3 shows a level shift circuit having a constant current source constituted by a MESFET 36 and a diode 31.

Both the circuit of FIG. 2 and the circuit of FIG. 3 are used not only as individual circuits but also extremely widely as basic constituent circuits of integrated circuits.

Further, the high frequency gain, band, input impedance, or operating speed as a logic circuit of the circuit shown in FIGS. 2 and 3 as an amplifier circuit are determined by the current gain and Cgd of the MESFET. Therefore, reducing the Cgd of the MESFET is very effective in improving the characteristics of these circuits.

One way to reduce the Cgd of a MESFET is to modify the external circuit of a dual gate type MESFET used for gain control amplifiers and mixers and use it as a single gate MESFET with a small Cgd. .

Dual gate type M commonly used in Figure 4
A structural diagram of the ESFET is shown. Dual gate type M
The ESFET has two Schottky gate electrodes 6.7 between the source electrode 4 and the drain electrode 50.

In order to use the dual gate quip MESFET for the above purpose, the gates 1-6 on the train side and the source 4 are shorted by an external circuit, and a signal is input only to the gate 7 on the source side. In this case, the Cgd between the gate 7 and the drain 3 becomes a fraction of the normal value or less due to the principle described later. However, in such a circuit, actual division becomes a new problem that cannot be ignored, such as the parasitic inductance and stray capacitance present in the external circuit, making it impossible to achieve good high-speed and high-frequency characteristics.

[Disclosure of the invention]

The present invention provides a new Cg
This provides a MESFET with extremely small d.

The MESFET of the present invention has a source follower circuit, etc.
For circuits where gd is a particularly important issue, "C" is optimal and can achieve good ultra-high frequency characteristics and ultra-high speed logic operation.

Further, the MESFET of the present invention can be manufactured easily and with high yield by a normal semiconductor device manufacturing method.

The present invention will be explained below based on the drawings.

An example of the MESFET of the present invention is shown in FIG.

Here, 1 is a high resistivity or semi-insulating semiconductor crystal substrate, 2
3 and 4 are a conductive semiconductor crystal layer called an active layer, and 3 and 4 are a drain electrode and a source electrode, respectively, having ohmic characteristics.

The ME S FET of the present invention has two Schottky gate electrodes 8.9 between the drain electrode 3 and the source electrode 4, and the Schottky gate electrode 8 on the drain side is connected to the source electrode 4.
It is characterized by being electrically connected to.

Next, an equivalent circuit of the MESFET of the present invention is shown in FIG.

23 corresponds to the drain electrode 3, 24 corresponds to the race electrode 4, and 29 corresponds to the Schottky gate electrode 9 on the source side.

In the MESFET of the present invention, firstly, the source-side gate 9 (hereinafter referred to as the signal gate) for signal input is electrostatically shielded by the drain-side gate 8 fixed at the same potential as the source; Second, as is clear from the equivalent circuit, the Cg between the signal gate 9 and the drain electrode 3 is
d can be reduced to a fraction of that of a MESFET with a normal structure.

Further, in the MESFET of the present invention, since the gate electrode 8 on the drain side is connected to the source electrode 4 on the chip, the parasitic inductance and parasitic capacitance caused by this wiring can be completely ignored. Therefore, good characteristics can be stably achieved even in ultra-high speed and ultra-high frequency operation.

Furthermore, it is sufficient that the gate length of the Schottky gate electrode 8 on the drain side, which is necessary for reducing Cgd, is equal to or less than that of the Schottky gate metal 9 on the source side.

The MESFET of the present invention designed in this way is similar to the ordinary MESFET.
Assuming the pinch-off voltage of SFET (approximately 2 to 3 V), the increase in channel resistance due to the fact that the gate electrode 8 is always biased to the same potential as the source electrode 4 is slight, and is different from that of a MESFET with a normal structure. Equivalent current gain can be obtained.

For manufacturing the MESFET of the present invention, a conventional M
By applying the ESFET manufacturing method, it can be manufactured easily and with high yield.

When implementing the MESFET of the present invention, the packaging of the chip, the method of incorporating it into the circuit, etc. are the same as those of ordinary MES.
It can be handled in exactly the same way as an FET.

[Industrial applicability]

According to the Schottky gate field effect transistor of the present invention, the gate-drain capacitance can be reduced to a fraction of that of the conventional technology, and therefore good ultra-high frequency operation and ultra-high speed operation can be stably realized.

The above features are ideal for various widely used circuits such as source follower circuits and level shift circuits.The Schottky gate field effect transistor of the present invention can not only be incorporated into a circuit as a single L transistor, but also
It is extremely useful as a basic component of integrated circuits.

Furthermore, the Schottky gate field effect transistor of the present invention can be manufactured using conventional techniques for chip packaging, circuit mounting, etc., and can be manufactured easily and with high yield using ordinary semiconductor device manufacturing methods. The industrial value is extremely large.

[Brief explanation of drawings]

FIG. 1 is a structural diagram of a conventional Schottky gate field effect transistor. FIGS. 2 and 3 are examples of circuits using Schottky gate field effect transistors. FIG. 4 is a structural diagram of a conventional dual-gate quib Schottky gate field effect transistor. FIG. 5 is a structural diagram of a Schottky gate field effect transistor according to the present invention, and FIG. 6 is an equivalent circuit diagram thereof. l --- Semiconductor substrate 2 ・-Active layer 3 ・-- ・ Drain electrode 4 ・ ・ ・
・ Source electrode 5, 6.7.8.9 Schottky gate electrode 23, 14
．． 34 ・ ・ Drain 24, 13.33 ・ Source 29, 15.35 Gate

Claims (1)

[Claims] (1) A semi-insulating semiconductor substrate, comprising an active layer formed on the surface of the semiconductor substrate, and a source electrode and a drain electrode formed on the active layer, with the source electrode being close to the source electrode between the source electrode and the drain electrode. The Schottky gate electrode has a second Schottky gate electrode close to the first Schottky gate electrode and the drain electrode, and the second Schottky gate electrode and the source electrode are electrically connected on the chip. Gate field effect transistor.