JPS58201375A - Field effect transistor - Google Patents

Abstract

PURPOSE:To obtain the multi-gate Schottky barrier FET enabled to perform high speed logic operation by a method wherein gate electrodes of two pieces or more are provided between electrodes of a source and a drain, and the more the gate electrode approaches the drain electrode from the source electrode, the more the gate width is broadened. CONSTITUTION:Si ions are implanted to a semiinsulating GaAS substrate to provide an N type active layer 10, and width thereof is made to have the trapezoid type extending toward the drain electrode 14 from the source electrode 13. The AuGeNi source electrode 13 is formed at the upside thereof, the drain electrode 14 of the same is formed at the downside, the parallel two lines type Al Schottky electrodes 11, 12 are formed between them, and the electrode 12 is made longer than the electrode 11. Otherwise, an island type ohmic electrode 15 is inserted between the gates 11, 12, and to make the series type FET's having different gate width is also favorable. By changing gate width like this, the difference between source series resistances according to the gate electrodes is compensated, the difference between transmission delay times according to the positions of the gate electrodes is reduced, apparent gm of each electrode is made the same, and the multigate FET having high maximum operating frequency and moreover having stable operation can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schott-pariah gate type '1 field effect transistor, 5 (ME 8 W -
ET), and in particular multi-gate Mg8FETs with multiple gate electrodes to enable associated logic operations.

Schottky barrier gate field effect transistor (M
In particular, the GaAsM18FET, which uses jaAs as the active layer, exceeds the performance limits of conventional bipolar transistors using 81, and is being considered as a device for future ultra-high-speed digital signal processing. .

A basic NAND circuit in a GaAs Mg8FET logic circuit uses a multi-gate MgSFET having a large number of gate electrodes, as shown in FIG.

Figure 1 shows a two-person NAND circuit with two input quadruplets (
It is composed of a twin gate pg'r 3 having gate electrodes) l and 2 and a load 4, and output is taken out from a terminal 5.

Load 2 is depression type (normally on type) FgT
The load has a constant current characteristic in which the gate electrode is connected to the source electrode, but a simple constant resistor may be used.

Incidentally, if the twin gate Fg'l' 3 is an enhancement II (normally off type), the output terminal 5 can be directly connected to the gate input of the next stage. On the other hand, in the case of deplane, m (normally on type), PET
In order to match the output potential to the input potential, a level shift circuit is required to lower the potential as shown in FIG. The transmission delay time tpd of this circuit is amazing.) Let the mutual conductance of FFI:T be gllll, and the capacitive load 6 consisting of each input sound of the next stage and the wiring capacitance be CJ! Then, as a rough approximation, it can be expressed as t tpd knee (1)-.

Here, we will clearly discuss the problems with the conventional Suge-1-MESFET used in the NAND circuit shown in FIG.

The structure of a conventional twin-gate FET is basically shown in Figure 3 (a).
), As shown in (b), there is an n-type movable outer layer region 10 on the surface of the semi-insulating GaAs substrate, and on top of this there are two linear Schottky gates with the same length.
1.degree. 12, and source and drain ohmic electrodes 13 and 14 were formed to sandwich this. There is also a type in which an island-shaped ohmic electrode 15 is inserted between the gate electrodes 11 and 12, and two single gate FETs are connected in series, as shown in FIGS. 4(a) and 4(b). Ta.

By the way, in FET, when there is a source series resistance rs between the gate and the source, the apparent mutual conductance gm' of the PI (T element as a whole, where gl is the true mutual conductance, becomes), and the mutual conductance of the whole FgT gm
' becomes smaller than the true transconductance gsn'.

Source series resistance r in GaAs ME8FET
s depends on the active layer resistance between the gate electrode and the source electrode and the contact resistance between the source electrode and the GaAs active layer.

In the dual-gate FETs shown in Figures 3 and 4, the source series resistance of the first gate near the source is almost as small as that of a single-gate FET, but the second gate is lower than the second gate from below the first gate. Due to the addition of the resistance of the operating layer up to
The source series resistance increases and the transconductance gl
nt becomes smaller.

Therefore, from equation (1), tpd for the first gate and
A difference occurs in tpd for the gate, resulting in logic operation (NAND
operation) may become unstable.

The present invention has been made in view of the above-mentioned drawbacks of conventional multi-gate FITs.
The idea is to compensate for the difference in source series resistance ra due to one pole by changing the gate width Wg of each gate electrode, and to make the apparent mutual conductance gm' of each gate electrode the same.

Next, a multi-gate FET according to the present invention will be explained using a twin-gate FB'l'' as an example.

FIG. 4 shows the MESFET of the present invention. This can be achieved by implanting, for example, Si into a semi-insulating GaAs substrate to achieve a carrier concentration of 2.0 XIO"61+1
', 1000 thick! As shown in the figure, the width of the n-type active layer region 10 is from the source electrode 12 side to the drain electrode 13@
It is formed into a trapezoidal shape that expands toward
() A source electrode 13 made of eNi and a drain electrode 14 are provided at the bottom, and two linear A1 lines are connected in parallel between them.
A first gate electrode 11 and a second gate electrode 12 are provided as symmetry gate electrodes. Here, the gate width is the line length of the gate electrode in contact with the active layer region, and since the active layer region is trapezoidal, the second gate electrode 1
2 is longer than the first gate 4-pole 11.

In addition, as shown in Fig. 95, an island-shaped ohmic pole 15 is inserted between the conduit 1-1-11 and the second gate 12,
It may be as if two kETs with different gate widths are connected in series. Here, 1! ! I-shaped ohmic property-
The electrode 15 is not limited to metal such as AuGeNi, but can be made of 1. The active layer may be thick or the carrier concentration may be high.

fs4 figure, figure 5 throat (in a twin gate Fbi'' where the gate widths of the first gate and the second gate are different, the gate width of the second gate is changed from 30 μm to 40 μm lc in order to correct the mutual conductance of the second gate. By increasing about 30 inches, the gl of the first gate becomes 1.8 mS,
The gm @ of the second gate was almost 1.75m5. That is, the appropriate gate width ratio for both dates was about 1:1.3.

In addition, when we prototyped an edge-trigger type % frequency divider circuit using six NAND circuits as shown in Figure 2, we found that
When using a dual-gate PET with the same gate width, the operating frequency was 2.8 GHz, but with the gate width ratio of 1:1.3 as shown in FIG. The maximum operating frequency was 3.9αIz, approximately 40% higher, and the transient characteristics of the frequency-divided waveform were also improved. In this way, in a multi-gate F-Net (Suge-1-NET), by increasing the width of the gate far from the source electrode and making the mutual conductance of each gate electrode equal, the maximum operating frequency can be increased. The effect of the present invention is clear from the fact that it is stable.

[Brief explanation of drawings]

Figure 1 shows a basic NA-ND using Suge-1-FET.
Circuit, Figure 2 is a NANDM with a level shift circuit
Figures 3 and 4 show a conventional twin-gate FET, and Figures 5 and 6 show an embodiment of the present invention.
It is T. 10 is an active layer region, 11 is a first gate electrode,
1 is a striped gate electrode, 13 is a source Ill electrode, 14 is a drain electrode, and 15 is an island-like ohmic electrode. Key 1 Diagram 2 Diagram (a) (α) (b)
(b) Toru 5 figure

Claims (1)

[Claims] 1. A Schottky barrier gate type characterized in that two or more gate electrodes are provided between a source electrode and a drain electrode, and the gate width of the gate electrode is set to be wider as it approaches the source electrode and the drain electrode. Field effect transistor.