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JPS6156613B2 - - Google Patents

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Publication number
JPS6156613B2
JPS6156613B2 JP4051377A JP4051377A JPS6156613B2 JP S6156613 B2 JPS6156613 B2 JP S6156613B2 JP 4051377 A JP4051377 A JP 4051377A JP 4051377 A JP4051377 A JP 4051377A JP S6156613 B2 JPS6156613 B2 JP S6156613B2
Authority
JP
Japan
Prior art keywords
electronic device
oxide layer
mask
mesa
gaas wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4051377A
Other languages
Japanese (ja)
Other versions
JPS53125768A (en
Inventor
Tsutomu Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP4051377A priority Critical patent/JPS53125768A/en
Publication of JPS53125768A publication Critical patent/JPS53125768A/en
Publication of JPS6156613B2 publication Critical patent/JPS6156613B2/ja
Granted legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 本発明は、幅/高さの比が大きい多数個の階段
からなるメサ側面を有する電子装置における階段
形メサ構造の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a stepped mesa structure in an electronic device having a mesa side surface consisting of multiple steps with a large width/height ratio.

一般に金属もしくは半導体などの電子装置材料
表面にメサを形成する方法は、第1図に示すよう
に金属もしくは半導体などの電子装置材料11の
表面にフオトレジストなどのマスク12を形成
し、該マスク12を用いて前記電子材料11表面
を化学的に選択エツチングしてメサを形成してい
る〔第1図a〕。このような従来方法によるメサ
側面の勾配は大きく、したがつて従来構造のメサ
を有する電子装置において、メサ側面を縦断する
ように配線13をおこなうと、急勾配のメサ側面
で断線を生じる問題〔第1図b〕があつた。
In general, a method for forming a mesa on the surface of an electronic device material such as a metal or a semiconductor is as shown in FIG. A mesa is formed by chemically selectively etching the surface of the electronic material 11 using a method [FIG. 1a]. The slope of the mesa side surface according to such a conventional method is large, and therefore, in an electronic device having a mesa of the conventional structure, when wiring 13 is run vertically across the mesa side surface, there is a problem that wire breakage occurs on the steeply sloped mesa side surface. Figure 1b] was found.

本発明は、上記の如き従来構造で生じる問題点
を除去するためになされたもので、その目的は、
メサ側面を幅/高さの比が大きい多数個の階段か
らなる構造にして、メサ側面の勾配を緩くせし
め、メサ側面における断線を防止せしめる電子装
置における階段形メサ構造の形成方法を提供する
ことにある。
The present invention was made in order to eliminate the problems that occur with the conventional structure as described above, and its purpose is to:
To provide a method for forming a stepped mesa structure in an electronic device, in which the mesa side surface is made into a structure consisting of a large number of steps with a large width/height ratio, the slope of the mesa side surface is made gentle, and disconnection on the mesa side surface is prevented. It is in.

本発明によれば、金属もしくは半導体などの電
子装置材料に対する密着力が小さな被膜をマスク
として、前記電子装置材料表面に、陽極酸化法に
より選択的に酸化層を形成し、次に形成された該
酸化層を全て除去する酸化・除去の工程を多数回
繰り返すことを特徴とする電子装置における階段
形メサ構造の形成方法が得られる。
According to the present invention, an oxide layer is selectively formed on the surface of the electronic device material by an anodic oxidation method using a film having low adhesion to an electronic device material such as a metal or a semiconductor as a mask, and then the formed oxidized layer is A method for forming a stepped mesa structure in an electronic device is obtained, which is characterized by repeating the oxidation/removal process many times to remove all the oxide layer.

以下、本発明について電子装置材料として
GaAsを使用した一例を図面を用いて説明する。
第2図は本発明の一実施例について説明するため
の図である。まず80℃で30分間、加熱された
GaAsウエーハ21上に通常に用いられるスピン
ナによりフオトレジストOMR―30CP(商品名)
を回転速度3000r.p.m,20秒間の回転条件下で塗
布し、通常の露光方法により露光現像し、150℃
で1時間焼結してマスク22を形成する〔第2図
a〕。次に陽極酸化法により、フオトレジストで
一部マスクされたGaAsウエーハ21を陽極とし
て、GaAs露出部分表面に酸化層23を形成す
る。このとき陽極酸化のための電解液は前記マス
ク22端とGaAsウエーハ21との界面に浸入す
るから、電解液と接するマスク22下のGaAsウ
エーハ21表面にも酸化層13が形成され、これ
とともに酸化層23の厚さは消耗されたGaAsウ
エーハの深さの約1.5倍に増加するから、GaAsウ
エーハ21に対する密着力が小さなマスク22は
酸化層23の成長とともに隆起し、その結果該酸
化層近傍の前記界面に隙間を生じ、前記電解液は
マスタ22とGaAsウエーハ21の界面の該隙間
にさらに侵入し、そこのGaAsウエーハ21表面
にも酸化層を形成〔第2図b〕する。以上のよう
にGaAsウエハー表面に選択的に形成された酸化
層は、たとえばHCl水溶液で、GaAsをエツチン
グすることなく容易に除去される〔第2図c〕。
次に上記のマスク22を用いて再度陽極酸化をお
こない〔第2図d〕、酸化層23を除去する〔第
2図e〕。このように酸化および除去の工程を繰
り返しおこない、次にマスク22を除去すること
によりGaAsウエーハ21表面に幅/高さの比が
大きい多数個の階段からなるメサを設けること
〔第2図f〕ができる。次に真空蒸着法により、
このようなメサ側面を縦断するように配線金属2
4を被着〔第3図g〕しても断線は全く生じな
い。なお、酸化・除去の1工程で形成される階段
の幅/高さの比は4.6〜4.7倍となるが、この階段
の幅/高さの比はマスクの形成条件によつて任意
に変えることができ、たとえば前記のOMR―
30CPを2度塗布してマスクの厚さを2倍に大き
くすると前記の比は4.1〜4.2に変えることができ
る。
The present invention will be described below as an electronic device material.
An example using GaAs will be explained with reference to the drawings.
FIG. 2 is a diagram for explaining one embodiment of the present invention. First, it was heated at 80℃ for 30 minutes.
Photoresist OMR-30CP (product name) is deposited on the GaAs wafer 21 using a commonly used spinner.
was applied at a rotational speed of 3000rpm for 20 seconds, exposed and developed using a normal exposure method, and then exposed to 150°C.
The mask 22 is formed by sintering for one hour (FIG. 2a). Next, by anodic oxidation, an oxide layer 23 is formed on the exposed GaAs surface using the GaAs wafer 21 partially masked with photoresist as an anode. At this time, the electrolytic solution for anodic oxidation enters the interface between the end of the mask 22 and the GaAs wafer 21, so an oxide layer 13 is also formed on the surface of the GaAs wafer 21 under the mask 22 that is in contact with the electrolytic solution, and along with this, the oxidized layer 13 is Since the thickness of the layer 23 increases to about 1.5 times the depth of the consumed GaAs wafer, the mask 22, which has a small adhesion to the GaAs wafer 21, rises as the oxide layer 23 grows, and as a result, the area near the oxide layer increases. A gap is created at the interface, and the electrolytic solution further penetrates into the gap at the interface between the master 22 and the GaAs wafer 21, forming an oxide layer on the surface of the GaAs wafer 21 there as well (FIG. 2b). The oxide layer selectively formed on the surface of the GaAs wafer as described above can be easily removed using, for example, an aqueous HCl solution without etching the GaAs (FIG. 2c).
Next, anodic oxidation is performed again using the above mask 22 [FIG. 2 d], and the oxide layer 23 is removed [FIG. 2 e]. By repeating the oxidation and removal steps as described above and then removing the mask 22, a mesa consisting of a large number of steps with a large width/height ratio is provided on the surface of the GaAs wafer 21 [FIG. 2 f] I can do it. Next, by vacuum evaporation method,
The wiring metal 2 is placed vertically across the side of the mesa.
4 (Fig. 3g) does not cause any disconnection. Note that the width/height ratio of the steps formed in one step of oxidation and removal is 4.6 to 4.7 times, but the width/height ratio of the steps can be changed arbitrarily depending on the mask formation conditions. For example, the above OMR
By applying two coats of 30CP and doubling the mask thickness, this ratio can be changed to 4.1-4.2.

以上説明したごとく本発明の構造を有する電子
装置は配線断線を除去することができる。またこ
の発明の思想は断線対策のみならず、幅が広く高
さが低い階段を必要とする電子装置に有効であ
る。なお、実施例においては、GaAsについて説
明したが陽極酸化される他の電子装置材料である
Al,Ta,Siなどにおいても同様の効果を得るこ
とは言うまでもなく、さらにマスクとしてフオト
レジスタOMR―30CPを用いたが、他の類以の被
膜を用いても同様の効果を得ることは言うまでも
ない。
As explained above, the electronic device having the structure of the present invention can eliminate wiring breaks. Further, the idea of the present invention is effective not only for measures against wire breakage, but also for electronic devices that require stairs that are wide and low in height. Although GaAs was explained in the examples, other electronic device materials that can be anodized may also be used.
It goes without saying that the same effect can be obtained with Al, Ta, Si, etc., and although we used photoresist OMR-30CP as a mask, it goes without saying that the same effect can be obtained with other similar films. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のメサ構造と該製造方法を説明す
るための断面図で、第2図は本発明の一実施例を
説明するための図で各主要工程の断面図である。 図において11は電子装置材料、12はマス
ク、13は配線金属、21はGaAsウエーハ、2
2はフオトレジスト膜、23は酸化層、および2
4は配線金属を示す。
FIG. 1 is a sectional view for explaining a conventional mesa structure and its manufacturing method, and FIG. 2 is a sectional view for explaining an embodiment of the present invention, showing each main process. In the figure, 11 is an electronic device material, 12 is a mask, 13 is a wiring metal, 21 is a GaAs wafer, 2
2 is a photoresist film, 23 is an oxide layer, and 2
4 indicates wiring metal.

Claims (1)

【特許請求の範囲】[Claims] 1 金属もしくは半導体などの電子装置材料表面
に該電子装置材料に対する密着力が小さな被膜を
マスクとして、陽極酸化法により前記電子材料表
面に酸化層を選択的に形成し、次に形成された該
酸化層を除去する酸化・除去の工程を多数回繰り
返すことを特徴とする電子装置における階段形メ
サ構造の形成方法。
1. An oxide layer is selectively formed on the surface of an electronic device material such as a metal or a semiconductor by an anodic oxidation method using a film with low adhesion to the electronic device material as a mask, and then the formed oxide layer is A method for forming a stepped mesa structure in an electronic device, characterized by repeating an oxidation/removal process for removing layers many times.
JP4051377A 1977-04-08 1977-04-08 Forning method of step type mesa construction in electronic device Granted JPS53125768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4051377A JPS53125768A (en) 1977-04-08 1977-04-08 Forning method of step type mesa construction in electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4051377A JPS53125768A (en) 1977-04-08 1977-04-08 Forning method of step type mesa construction in electronic device

Publications (2)

Publication Number Publication Date
JPS53125768A JPS53125768A (en) 1978-11-02
JPS6156613B2 true JPS6156613B2 (en) 1986-12-03

Family

ID=12582609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4051377A Granted JPS53125768A (en) 1977-04-08 1977-04-08 Forning method of step type mesa construction in electronic device

Country Status (1)

Country Link
JP (1) JPS53125768A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63155114U (en) * 1987-03-30 1988-10-12
JPH0224834U (en) * 1988-08-02 1990-02-19
JPH02132321U (en) * 1989-03-31 1990-11-02
WO2019194201A1 (en) 2018-04-02 2019-10-10 日本製鉄株式会社 Metal plate, method for manufacturing metal plate, method for manufacturing metal plate-molded article, and metal plate-molded article

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63155114U (en) * 1987-03-30 1988-10-12
JPH0224834U (en) * 1988-08-02 1990-02-19
JPH02132321U (en) * 1989-03-31 1990-11-02
WO2019194201A1 (en) 2018-04-02 2019-10-10 日本製鉄株式会社 Metal plate, method for manufacturing metal plate, method for manufacturing metal plate-molded article, and metal plate-molded article
KR20200124309A (en) 2018-04-02 2020-11-02 닛폰세이테츠 가부시키가이샤 Metal plate, method of manufacturing a metal plate, method of manufacturing a molded article of a metal plate, and a molded article of a metal plate

Also Published As

Publication number Publication date
JPS53125768A (en) 1978-11-02

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