JPS6156539B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal processing device having a self-fault searching function.

With the recent development of large-scale integrated circuit technology and advances in digital processing technology, digital signal processing devices that achieve advanced signal processing that was previously considered impossible have come into practical use. However, digital signal processing equipment for such advanced signal processing generally includes multiple complex signal processing functions and executes complex control while exchanging signals. When a failure occurs in equipment, the more complex the equipment, the more difficult it is to locate the failure unless an engineer is familiar with the equipment, making it extremely difficult to maintain and operate the equipment. There is.

An object of the present invention is to provide a digital signal processing device that eliminates the above-mentioned drawbacks.

The processing device of the present invention includes a test signal generation circuit that supplies a test signal for fault detection of the signal processing block to each signal processing block included in the digital signal processing device, and a test signal generation circuit that supplies a test signal for searching for a fault in the signal processing block to each signal processing block included in the digital signal processing device. The signal generation circuit and the verification circuit can be used to verify whether or not each signal processing block is abnormal.

According to the present invention, since it is possible to verify the presence or absence of an abnormality in each signal processing block of a digital signal processing device, the location of a failure can be easily found even in a complex digital signal processing device, and maintenance and operation of the device is facilitated. becomes.

Next, the present invention will be explained in detail with reference to the drawings.

In the following, the present invention will be explained in detail by exemplifying an interframe coding/decoding device for highly efficient coding of a television signal as a digital signal processing device.
A known interframe coding/decoding device includes an analog/digital converter (A/D) 1 that converts an analog color television signal into a PCM signal, and a digitized color television signal that is separated into a luminance signal and a color signal. The transmission color signal processing section 2 converts the time division multiplexed color television signal into a time division multiplexed color television signal, the interframe encoding processing section 3 performs interframe encoding of the time division multiplexed color television signal, and the interframe encoding processing section 3 performs processing. A transmitting section consisting of a variable length encoding processing section 4 that performs variable length encoding on the interframe prediction error signal obtained, a D/A conversion section 5, and a received color signal processing section 6.
, an interframe decoding processing section 7, and a receiving section having a variable length decoding processing section 8.
For details on the interframe coding/decoding device, please refer to the document published on July 29, 1979 at the Communication Method Study Group sponsored by the Institute of Electronics and Communication Engineers.
CS79-73 “Interframe coding device for video conferencing
NETEC-6/3'', so details are omitted.

As a failure detection method for a device that performs complex signal processing such as the above-mentioned interframe coding/decoding device,
A method is known in which a test signal most suitable for verifying the presence or absence of an abnormality in each signal processing block is applied, and the signal processing results at that time are verified.

A configuration shown in FIG. 2 can be considered as a means for implementing such a fault search method. In Figure 2,
Reference numeral 9 is a test signal generation circuit, reference numeral 10 is a test signal verification circuit, and reference numerals 11 to 24 are switch circuits. With the configuration shown in FIG. 2, the fault search is performed by transmitting digital test signals supplied from the test signal generation circuit 9 to the switch circuits 11 to 13 and 18 to 21.
Select which signal processing block is to be supplied to the test signal verification circuit 10 by operating the switch, select which signal processing block's output signal is to be supplied to the test signal verification circuit 10 by operating the switches 14 to 17 and 22 to 24, This can be done by verifying the signal processing results of the signal processing block to be verified using the test signal verification circuit 10 to determine whether or not there is a fault in the signal processing block. For example, when determining whether or not there is a failure in the transmission color signal processing section 2, the switch circuit 11 on the input terminal side of the transmission color signal processing section 2 is set such that the output of the test signal generation circuit 9 is selected. In order to supply the output of the transmission color signal processing section 2 to the test signal verification circuit 10, the switch circuit 15 is operated so that the output of the transmission color signal processing section 2 is selected, and the remaining switch circuits are 16,1
Switches 7, 22, 23 and 24 are operated so that the outputs of switch circuits 15, 16, 17, 22 and 23 are selected, respectively.

As is clear from the above explanation, the presence or absence of a fault in each signal processing block can be verified with the configuration shown in FIG. This method requires a signal line to supply the output of 9 to each signal processing block and a signal line to supply the output of each signal processing block to the test signal verification circuit, making the overall configuration of the device very complex. be. Particularly, in a device such as a television signal encoding/decoding device that operates at high speed and can only process parallel data, an increase in the number of signal lines and switch circuits significantly increases the size of the device.

An embodiment of the present invention shown in FIG. 3 includes a processing device divided into a plurality of signal processing blocks 1 to 8;
a test signal generation circuit 9 that generates a diagnostic test signal for checking the presence or absence of a fault in the signal processing blocks 1 to 8; and a test signal diagnostic circuit that verifies the test signal output of the signal processing block that has received the test signal. 10, and switch circuits 11 to 18 are provided at the output terminals of each of the signal processing blocks to supply the test signal to the signal processing block to be tested among the signal processing blocks and to control the test signal from the signal processing block to be tested. The output is supplied to the diagnostic circuit by selectively switching the switch circuit.

When searching for a fault in the decoding device, the switch circuit 11 selects the output of the test signal generation circuit 9, and the switch circuits 12 to 18 perform switch operations determined by which signal processing function the test signal is supplied to. . For example, the interframe decoding processing unit 7
When checking whether the switch circuit 1 is normal or not,
A switch 2 is operated so that the input signal of the transmission color signal processing section 2, that is, the output of the test signal generation circuit 9, is selected, and a switch circuit 13 is operated so that the input signal of the interframe encoding processing section 3 is selected. By operating the switches so that the input signal of the variable length encoding processing section 4 is selected, the switch circuit 15 and the switch circuit 16 select the input signal of the variable length decoding processing section 8, respectively, the interframe decoding processing section is selected. The output signal of the test signal generating circuit 9 is supplied to the test signal generating circuit 7. Interframe decoding processing The processing result of the signal processing in the decoding processing section 7 is supplied to the test signal verification circuit 10 by selecting the output signal of the interframe decoding processing section 7 in the switch circuit 17, It is determined whether the processing section is operating normally. Similarly, the switch circuits 11 to 1
By operating the switch 8, it is possible to determine whether each signal processing block is operating normally.

As described above, according to the present invention, fault detection in a digital signal processing device can be realized by adding one switch circuit and a small amount of signal lines for each signal processing function for which fault detection is to be performed. can be simplified.

Although this embodiment has been described using an interframe coding/decoding device as an example of a digital signal processing device, the present invention is not limited to the interframe coding/decoding device and can be applied to other digital signal processing devices. It is also possible to do so.

[Brief explanation of the drawing]

1 and 2 are block diagrams for explaining the present invention, and FIG. 3 is a block diagram showing one embodiment of the present invention. In FIG. 3, 1...A/D converter, 2...
Transmission color signal processing section, 3... Interframe coding processing section, 4... Variable length coding processing section, 5... D/
A conversion section, 6... Reception color signal processing section, 7...
Interframe decoding processing unit, 8...Variable length decoding processing unit, 11-18...Switch circuit.

Claims (1)

[Claims] 1. A processing device divided into a plurality of signal processing blocks, a test signal generation circuit that generates a diagnostic test signal for checking the presence or absence of a fault in the signal processing block, and a processing block that receives the test signal. In a digital signal processing device having a self-diagnosis function and comprising a test signal diagnostic circuit for verifying test signal output, a switch circuit is provided at each output terminal of the signal processing block, and a switch circuit is provided at the output terminal of each of the signal processing blocks to perform the test. A digital signal having a self-diagnosis function, characterized in that the test signal is supplied to the signal processing block and the test signal output from the signal processing block to be tested is supplied to the diagnostic circuit by selectively switching the switch circuit. Processing equipment.