JPS614242A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS614242A JPS614242A JP59125851A JP12585184A JPS614242A JP S614242 A JPS614242 A JP S614242A JP 59125851 A JP59125851 A JP 59125851A JP 12585184 A JP12585184 A JP 12585184A JP S614242 A JPS614242 A JP S614242A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- circuit
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/903—Masterslice integrated circuits comprising field effect technology
- H10D84/907—CMOS gate arrays
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体集積回路装置における回路構成に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a circuit configuration in a semiconductor integrated circuit device.
従来、半導体集積回路装置は、例えば記憶（ロ）路装置
、ゲート・アレー装置、マイクロ・コンピュータ装置の
如く、単一機能を一つの半導体基板上に形成するのが通
例であった。Conventionally, semiconductor integrated circuit devices, such as memory circuit devices, gate array devices, and microcomputer devices, have typically had a single function formed on one semiconductor substrate.
本発明は、半導体集積回路装置に於て、２つの機能を集
積し、回路機能の多機能化を計ることを目的とする。An object of the present invention is to integrate two functions in a semiconductor integrated circuit device, thereby increasing the number of circuit functions.
上記目的を達成するための本発明の基本的な構成は、半
導体集積回路装置に於て、１つの半導体基板上には電気
的書き込み消去可能な読み出し専用記憶装置とゲート・
アレー装置とが一体となって形成されて成る事を特徴と
する。The basic structure of the present invention for achieving the above object is that in a semiconductor integrated circuit device, an electrically programmable and erasable read-only memory device and a gate
It is characterized by being formed integrally with the array device.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示す回路ブロック図である
。すなわち、半導体基板１上には、ゲート・アレー回路
装置（Ｇ、Ａ、） ２と、電気的書き込み消去可能な読
み出し専用記憶装置（ＫＦｉＦＲＯＭ ） ９とが形成
されて成る。仁の場合％ｌＥｉＦＲＯＭｇには、Ｇ、Ａ
、２を選択して駆動させる回路構成に必要な情報が電気
的に書き込まれ、（工”Ｌ伝送線４によって、該情報が
Ｇ、Ａ、２部へ伝送され、 Ｇ、Ａ、２の回路構成が定
められ、該Ｇ、Ａ、２０回路構成によって入力信号（Ｉ
Ｎ）Ｋ対する出力信号（ＯＵＴ ）の成り立ちが変化す
ることになる。FIG. 1 is a circuit block diagram showing one embodiment of the present invention. That is, a gate array circuit device (G, A,) 2 and an electrically programmable and erasable read-only memory device (KFiFROM) 9 are formed on a semiconductor substrate 1. In the case of Jin, %lEiFROMg contains G, A
, 2 is electrically written into the circuit configuration that selects and drives the circuits of G, A, and 2. The configuration is determined, and the input signal (I
N) The configuration of the output signal (OUT) for K will change.
第２図は、本発明の他の実施例を示す回路ブロック図で
ある。すなわち、半導体基板１上には、単位セルから成
るロジック回路部（Ｕ、Ｃ） １２とＥＥＰＲＯＭ部１
３とが一つのユニットとして構成され、各ユニットのＥ
ＥＦＲＯＭ釦よす、各ユニットのロジックの成り立ちを
決定し、全体としてゲント、アレーとしての回路を決定
するという方式本発明の如く、１つの半導体基板上に’
ＢＢＰＲＯＭとＧ、Ａｃ（ゲート・アレー）とが一体と
なって構成されることにより、１つの半導体集積回路装
置により、機能の異なる回路装置、例えば演算回路装置
、マイクロ、プロセッサー装置、マイクロ争コンピュー
ター装置、更にはランダムアクセス−・メモリ装置さえ
も、外部からのＢ Ｅｆ Ｐ ＲＯＭ ｗの情報書き込
みのみで形成でき、更には、ＥＩＩＰＲＯＭの書き替え
により、他の回路構成へと容易に変更できＦｌ ’１４
Ｐ Ａ ’Ｌ （Ｗｌｅ６ｔｒｉｃａｌｌｙ ＩＣｒ
ａｓａｂｌｅＰｒｏｇｒａｍ Ａｖａｉｌａｂｌｅ Ｌ
ｏｇｉｇ ）効果がある。FIG. 2 is a circuit block diagram showing another embodiment of the present invention. That is, on the semiconductor substrate 1, there are a logic circuit section (U, C) 12 consisting of unit cells and an EEPROM section 1.
3 are configured as one unit, and each unit's E
The EFROM button determines the logic structure of each unit and determines the circuit as an array as a whole.
By integrating BBPROM, G, and Ac (gate array), one semiconductor integrated circuit device can be used as circuit devices with different functions, such as arithmetic circuit devices, microprocessor devices, and microcomputer devices. , and even a random access memory device can be formed by simply writing information into the BEf PROM w from the outside, and furthermore, it can be easily changed to other circuit configurations by rewriting the EIIPROM.Fl '14
P A 'L (Wle6trically ICr
availableProgram Available L
ogig) is effective.
第１図及び第２図は本発明の実施例を示す半導体集積回
路装置のブロック図である。
１．１１−−半導体基板（チップ）、２．１２−−ロジ
ック回路部、 ８ 、１３・・ＢＥＰＲＯＭ部、４・拳
伝送線。
以 上1 and 2 are block diagrams of a semiconductor integrated circuit device showing an embodiment of the present invention. 1.11--Semiconductor substrate (chip), 2.12--Logic circuit section, 8, 13...BEPROM section, 4. Fist transmission line. that's all
Claims (1)
出し専用記憶装置とゲート・アレー装置とが一体となっ
て形成されて成る事を特徴とする半導体集積回路装置。A semiconductor integrated circuit device comprising an electrically programmable and erasable read-only storage device and a gate array device integrally formed on one semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59125851A JPS614242A (en) | 1984-06-19 | 1984-06-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59125851A JPS614242A (en) | 1984-06-19 | 1984-06-19 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS614242A true JPS614242A (en) | 1986-01-10 |
Family
ID=14920507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59125851A Pending JPS614242A (en) | 1984-06-19 | 1984-06-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS614242A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115844A (en) * | 1985-09-11 | 1987-05-27 | ピルキントン マイクロ−エレクトロニクス リミテツド | semiconductor integrated circuit |
| JPH01107135U (en) * | 1988-01-08 | 1989-07-19 | ||
| JPH02177364A (en) * | 1988-10-14 | 1990-07-10 | Nec Corp | Semiconductor integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5827370A (en) * | 1981-08-11 | 1983-02-18 | Toshiba Corp | Non-volatile semiconductor memory |
| JPS5887644A (en) * | 1981-11-06 | 1983-05-25 | テキサス・インスツルメンツ・インコ−ポレイテツド | Programmable digital information processing system |
-
1984
- 1984-06-19 JP JP59125851A patent/JPS614242A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5827370A (en) * | 1981-08-11 | 1983-02-18 | Toshiba Corp | Non-volatile semiconductor memory |
| JPS5887644A (en) * | 1981-11-06 | 1983-05-25 | テキサス・インスツルメンツ・インコ−ポレイテツド | Programmable digital information processing system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115844A (en) * | 1985-09-11 | 1987-05-27 | ピルキントン マイクロ−エレクトロニクス リミテツド | semiconductor integrated circuit |
| JPH01107135U (en) * | 1988-01-08 | 1989-07-19 | ||
| JPH02177364A (en) * | 1988-10-14 | 1990-07-10 | Nec Corp | Semiconductor integrated circuit |
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