JPH01155588A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To highly densify the mounting of a memory by providing plural sets of an address lead wire, a selecting lead wire, and a data lead wire, connecting a transistor for the memory to each set independently, and making the memory accessible from plural processor. CONSTITUTION:Processors 35 and 36 are respectively connected to a semiconductor memory 10 through address lead wires 20 and 21, selecting lead wires 24 and 25, and data lead wires 28 and 29. When the semiconductor memory 10 is activated with the processors 35 and 36, address signals A0-A9 and B0-B9 are outputted through the respective address lead wires 20 and 21, and simultaneously with this, reading selecting signals A10 and B10 are sent through the selecting lead wires 24 and 25. Thereupon, the contents of the memory 10 instructed from the processors 35 and 36 are sent through the data lead wires 28 and 29 to the processors 35 and 36, and the processors 35 and 36 read these. Thus, the mounting density of the memory can be made higher.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory that is provided on one chip and can be accessed by multiple processors, thereby achieving high packaging density. Regarding semiconductor memory.

[Conventional technology]

Semiconductor memory made on one chip is generally used exclusively by one processor, and multiple processors
Generally speaking, it is not possible to share two semiconductor memories.

FIG. 4 is a block diagram showing the internal structure of a conventional semiconductor memory (mask ROM).

In FIG. 4, reference numeral 1 is an address signal A. It is an address lead wire that can transmit ~A, and is an address lead wire 1.
is connected to a processor (not shown). 2 is a lead wire for the read select signal A1°, and this lead wire 2 is connected to the processor. The address lead wire 1 and the lead wire 2 are connected to an address decoder circuit 3.

The semiconductor memory includes this address decoder circuit 3, data lead wires 4 for data D0 to D, a MOS transistor 5 indicating an ON state, a MOS transistor 5 indicating an OFF state, and each transistor. 5.6
Direct current (+5V) is applied to the data lead wire 4 connected to the terminal of
■ For supplying. . terminal 7, and an address line 8 connected to the address decoder circuit 3 and the gate of each ON MO3) transistor, and the necessary number of transistors 5 and 6 are provided, and the other terminals of the transistors 5 and 6 are grounded. It is structured based on the following.

Such a semiconductor memory supplies power to the vno terminal 7,
It can be used by grounding the ground terminal and connecting it to the processor as described above.

The operation of such a device will be explained.

Address signal A from the processor via address lead 1. -A, these enter the address decoder circuit 3. Here, address line 8 is selected by inputting read select signal A1o from the processor. Depending on the state of the MOS transistor 5.6 at the cross section between the selected address line 8 and the data lead line 4, the data can be sent to the address line 8 as the contents of the ROM.

In this case, the semiconductor memory for one processor is
They will be connected and controlled on a one-to-one basis.

FIG. 5 shows MOS transistor 5. of the semiconductor memory described above.
FIG. 6 is an explanatory diagram showing a configuration example of No. 6;

In a semiconductor memory, a thin oxide film transistor structure 9Δ is used to configure the MOS transistor 5;
) To constitute a transistor, a thick oxide film transistor structure 9B may be used.

With such a structure, the thin oxide film transistor structure 9A turns on, and the MOS transistor 5A turns on.
The drain output of is "0".

On the other hand, in the case of the thick oxide film transistor structure 9B, it is turned off, and the drain output of the MOS transistor becomes "1". Which part of the oxide film should be made thinner depends on the content of the write command.

In the case of this ROM, once written, the contents cannot be changed.

[Problem that the invention seeks to solve]

In the case of the above semiconductor memory, for one processor,
Since there is a one-to-one correspondence, there is a problem in that when high-density mounting is attempted, each device occupies the mounting area, making it impossible to reduce the mounting area.

In addition, for example, when two processors are used, there is a problem in that two chips of semiconductor memory must be mounted even if the capacity of the semiconductor memory is small.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor memory that can be accessed by a plurality of processors and has a gradual reduction in packaging density.

[Means for solving problems]

The semiconductor memory of the present invention is an l-chip semiconductor memory that includes a plurality of address lead lines for specifying addresses, a plurality of select lead lines for read select signals, and a plurality of data leads for taking out read signals. wire, and the address lead wire, select lead wire,
The device is characterized in that a plurality of sets of data lead lines are provided, and a memory transistor is independently connected to each set.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory according to the present invention.

In FIG. 1, a semiconductor memory 1 formed on an l chip is shown.
0 is configured as follows. That is, address signal A is used to specify an address. ~As,Bo~
A plurality of address leads 20.21 carrying B, are connected to address decoder circuits 22.23. Similarly, the address decoder circuits 22, 23! However, a plurality of D-select lead wires 24 and 25 for read select signals Δlo+BIQ are connected. 2) Address lines are independently output from the address decoder circuits 22 and 23. The address decoder circuit 22゜2
The gates of MOS transistors 26 and 27, which constitute memory cells independently, are connected to the address lines 3 and 3 respectively. One terminal of the MOS transistors 26 and 27 that constitute these memory cells is
Read signals I) Ao to DA7. Dmo～Dllf
A plurality of data lead wires 28 and 29 from which f is taken out are connected. Independent memory transistors 26.27 are connected, and a Vll11 terminal 30 for supplying direct current (+5V) is connected to a data IJ-domain line 28.29 connected to a terminal of each transistor 26.27. The required number of transistors 26 and 27 are provided, and the other terminals of the transistors 26 and 27 are grounded. Note that when this embodiment is used as a ROM, the on/off operation of the MOS (MOS) transistor of the memory cell may be performed in the same manner as in the prior art.

The address lead wire 20, the select lead wire 24, and the data lead wire 28 are made into a set, and the address lead wire 2
The select lead wire 25 and the data lead wire 29 are made into one set, and can be accessed by a plurality of processors.

A semiconductor memory having such a configuration is used as shown in FIGS. 2 and 3.

FIG. 2 is a block diagram showing an example of a configuration when a semiconductor memory is accessed by a plurality of processors. In FIG. 2, 35 and 36 are processors. processor 3
5 is an address lead wire 20, a select lead wire 24,
They are connected to each other via data lead wires 28.

The processor 36 is connected via an address lead wire 21, a select lead wire 25, and a data lead wire 29, respectively.

According to this embodiment, when the semiconductor memory 10 is activated by the processor 35, the address lead wire 20
The address signal A o ” A s is outputted through the select lead line 24, and at the same time, the read select signal A1° is sent via the select lead line 24. Then, the contents of the semiconductor memory 10 instructed by the processor 35 at this point are read as data. It is sent via line 28 to processor 35, where it can be read.

The above-described operations can be performed by the processor 36 as well.

FIG. 3 is a block diagram showing an example of a configuration when a semiconductor memory is accessed by one processor.

In FIG. 3, the semiconductor memory 10 of the present invention has address lead lines 20 and 21 connected in common, data lead lines 28 and 29 connected in common, and select lead lines 24 and 25 independently connected. Just keep it. The processor 50 is connected to the address leads 20.21 by a common connection line 51 and to the data leads 28.29 by a common connection line 52, respectively.

The processor 50 further includes a select lead wire 24°2.
5 are connected independently.

According to this embodiment, by selecting the read select signal AIO*BIO output from the processor 50, the signals DAO to DAT on the address lead line 20 side of the semiconductor memory 10 or the natres lead Signals D0 to D11 on the line 21 side. You will be able to choose which.

The above-mentioned two modes of use are possible, namely, a mode of use in which a plurality of processors 35 and 36 access one chip of the semiconductor memory 10, or a mode of use in which one processor 50 accesses a plurality of memory areas of the one chip of semiconductor memory IO. This makes it possible to use the semiconductor memory 10 in a manner such as accessing the semiconductor memory 10, thereby making it possible to increase the packaging density of the semiconductor memory 10.

〔Effect of the invention〕

As described above, the present invention has the effect of increasing the density of semiconductor memory packaging by making the semiconductor memory accessible from a plurality of processors.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing a circuit using the same embodiment, and FIG.
The figure is a circuit diagram showing a conventional semiconductor memory, and FIG. 5 is an explanatory diagram showing the structure of a memory element of the semiconductor memory. 10...Semiconductor memory, 20.21...Address lead wire, 24.25
...Select lead wire, 28.29...
・Data lead wire. Applicant: NEC Corporation Representative

Claims (1)

[Claims] A one-chip semiconductor memory has a plurality of address lead lines for specifying addresses, a plurality of select lead lines for read select signals, and a plurality of data lead lines for taking out read signals, 1. A semiconductor memory comprising a plurality of sets of address lead wires, select lead wires, and data lead wires, and a memory transistor connected to each set independently.