JPS6132572A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the heat deterioration of an ohmic electrode even through heat treatment for a prolonged term at a high temperature of 400 deg.C or higher by using a laminate, in which an Au-Ge layer, a W layer, an Ni layer and an Au layer are laminated in succession, as the ohmic electrode to an N type conductive layer formed to a gallium-arsenic crystal substrate. CONSTITUTION:N<+> layers 2 and an N layer 3 are formed onto a semi-insulating GaAs substrate 1 while using Si as an ion source. SiO2 films 4 are employed as surface protective films, and the N<+> layers 2 and the N layer 3 are activated in a H2 gas atmosphere. Ohmic electrode holes are shaped, the SiO2 films 4 are removed, and first layer AuGe layers 5, second layer W layers 6, third layer Ni layers 7 and fourth layer Au layers 8 are formed continuously. Ohmic electrode patterns are shaped, and ohmic contacts are obtained to the N<+> layers 2 through heat treatment in a N2 gas atmosphere. A gate electrode 9 is formed, a FET is manufactured, a PSG film 10 is applied as an inter-layer insulating film, contact holes are bored to the PSG film 10, and wiring metals 11 are formed.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a method for forming an ohmic electrode on a GaAs substrate having a TI type electrically conductive layer, particularly for GaAs IC+GaA, 5, which requires a highly heat-resistant ohmic electrode.
The present invention relates to ohmic electrodes for LSII.

[Background of the invention]

■As an ohmic electrode for a GaAs substrate having a type 1 conductive layer, use Hero as the first layer and N as the second layer.
Alternatively, a three-layer electrode structure composed of Cr and Au as the third layer is known (for example, Japanese Patent Publication No. 51-32
No. 533) 6 Generally GaAs1C.

When producing GaAsLS'I, F)! :'r(
After forming the ohmic electrode and the Schottky electrode constituting the field effect transistor, an interlayer insulating film deposition process and a wiring full bending process are required. Normally, a PSG film (phosphorus glass) is used as this interlayer insulating film, but the PSG film is processed using a thermal decomposition CVD method (Chemical CVD method).
cal vapor deposj, tion)
When forming the ohmic electrode, the ohmic electrode undergoes a high-temperature process at a temperature of 400° C. to 500° C. for at least 20 minutes.

In the conventional Au/Nj, /AuGe ohmic electrode structure, the flatness of the electrode surface is significantly impaired, and as a result, the ohmic electrode breaks the interlayer insulation film and causes a short circuit failure with the top layer wiring metal. Occur. Furthermore, when the ohmic electrode undergoes such a high-temperature process, the contact resistance of the ohmic electrode increases significantly.

[Purpose of the invention]

An object of the present invention is to provide a novel ohmic electrode for a GaAs crystal substrate, and more specifically, to provide a novel ohmic electrode for a GaAs crystal substrate.
Even after going through a high-temperature process between 0℃ and 500℃,
The object of the present invention is to provide a highly heat-resistant ohmic electrode with good flatness on the electrode surface and almost no thermal deterioration of contact resistance.

[Summary of the invention]

Conventional electrode lit ifi A u/N”/A
In u G e, the first JOAuG is
The upper limit temperature that can prevent Q's ball up (teal) is about 450 degrees Celsius, and 1
As for the time, it is about 1.E5 minutes, 3 prongs, 400℃
Long 11. After applying the +4 fl old;5 treatment, significant thermal deterioration of the flatness and contact resistance of the ohmic electrode was observed. / wl n △II In the r+ stack, first, the first layer A u G e layer; Due to the double layer of the third Ni layer, Ba11. The structure prevents oxidation of the third mNi layer from the second AU layer number knee.

[Embodiments of the invention]

The present invention will now be described in detail based on examples.

FIG. 1 is a sectional view showing a typical structure of a GaAsFET.

First, an n+ layer 2 and an 0 layer 3 are formed on a semi-insulating GaAs substrate 1 using Sl as an ion source. Next, using the 5i02 film 4 as a surface protective film, the n+ layer 2 and the 11 layer 3 are activated in a +-12 gas atmosphere.

Furthermore, after forming ohmic electrode holes by a well-known photolithography method and removing the 5i02 film 4, the first layer A
500 uGc (Ga4%) layer 5, 2nd layer W layer 6
100 people, 3rd layer Nj layer 7 tooλ, 4th layer Δ
A film of 1,000 layers thick is continuously formed by vacuum evaporation without breaking the vacuum. Next, an ohmic electrode pattern is formed by lift-off method, and /100
By performing heat treatment at .degree. C. for 3 minutes in a N2 gas atmosphere, ohmic contact is obtained with nt WJ2.

Furthermore, the gate electrode 9 is formed by a lift-off method similar to the ohmic electrode forming method. As above, FE
After manufacturing T, 43
I) SG (phosphorus glass) film 10 is deposited as an interlayer insulation film to a thickness of 7000Δ for 30 minutes at a temperature of 0°C. Contacts 1 to 1 holes are made on the PSG film, and wiring metal all is formed. In step 1' above, in step (1) where ohmic contact was obtained and step (2) where contact 6 was opened, contact 8! When we investigated the II resistance ρ6 and the unevenness (11) of the ohmic electrode surface, we found that (1) /l, <+x+o−'Ω·cm2. H<10
0λ(2) ρ, <lXl0-' Ω ・c
m2, II<500s, and despite undergoing a high-temperature process, almost no deterioration as an ohmic electrode was observed. In Example 1-, the ohmic electrode is A11 (+, 000λ)/Nj (100λ)/W
(100 people)/AuGe ((Ge8wl;%, 500 people) was taken as an example, but the following ranges are good for the film thickness range of each layer.

1st P'fJ; AuGc(Ge: 4-1.2
%1t%)>300λ (layer for obtaining ohmic contact of n+GaAs layer l\) 2nd u; 5 cores<W<200λ
(AuGe Ba1lup suppression layer) 3rd layer; 50λ<N
j<200λ (Due to the double film with the second layer W, the B of AuGe
a11. layer for suppressing up) 4th M; A
u > 200A (Layer for preventing oxidation of third layer N) An electrode of Au/Ni/W/ΔυGe 4-layer structure was deposited in the above film thickness range, and 4 layers were applied in an N2 gas or N2 gas atmosphere.
After obtaining ohmic contact at a temperature of 00-450℃ for a short time of 3-5 minutes, at a temperature of 400-460℃, 0.5~
Even after heat treatment in an N2 gas atmosphere for 2 hours, ρ, <
2X]0Ω・cm'.

As H<toooi, almost no deterioration of the ohmic electrode was observed.

〔Effect of the invention〕

According to the present invention, it is possible to make the ohmic electrode highly heat resistant, so that it is effective in preventing thermal deterioration of the ohmic electrode even after heat treatment at a high temperature of 400° C. or higher and for a longer time than before. The contact resistance and the unevenness of the electrode surface have been quantitatively demonstrated in Examples. The present invention is particularly effective when applied to source/drain electrodes of GaAs1G and GaAsLSI, which require Wi fine processing technology and require high-temperature processes.

Figures 1 and 1 of the drawings are cross-sectional views showing the structure of the FET portion applied to Gr+Δ5■C.

■...Semi-insulating GaAs substrate, 2...n layer, 3...
...n layer, 4...S i O2 film, 5...A u
G e layer, 6...W layer.

Claims (1)

[Claims] A semiconductor device characterized in that a laminate in which an Au-Ge layer, a W layer, a Ni layer, and an Au layer are sequentially laminated is used as an ohmic electrode to an n-type conductive layer provided on a gallium-arsenide crystal substrate.