JPS6132540A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6132540A JPS6132540A JP15434584A JP15434584A JPS6132540A JP S6132540 A JPS6132540 A JP S6132540A JP 15434584 A JP15434584 A JP 15434584A JP 15434584 A JP15434584 A JP 15434584A JP S6132540 A JPS6132540 A JP S6132540A
- Authority
- JP
- Japan
- Prior art keywords
- film
- opening
- etching
- oxide film
- oxidation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 19
- 229910052710 silicon Inorganic materials 0.000 abstract description 19
- 239000010703 silicon Substances 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 15
- 238000001312 dry etching Methods 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明ａ半導体装置特に高密度・高速度化を図った半導
体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device, particularly a method for manufacturing a semiconductor device with high density and high speed.
従来例の構成とその問題点
半導体装置の高密度・高速化を図るため、絶縁分離ろる
イｉｊ Ｓ ＯＳ （５ｉｌｉｃｏｎ ｏｎ Ｓ＆
ｐｈｉｒ６）の研究が活発に行なわれている。Conventional configurations and their problems In order to increase the density and speed of semiconductor devices, insulating isolation technology has been developed.
phir6) is currently being actively researched.
本発明者らは、バイポーラ、ＭＯＳを問わず島領域の側
面及び底面も絶縁物化する方法をすでに提案している。The present inventors have already proposed a method in which the side and bottom surfaces of the island region are also insulated, regardless of bipolar or MOS.
その一つの実施例を第１図＆ −、＝ ｆに示す。第１
図ａにおいて、１にたとえばｐ型１１１シリコン基板、
２に熱酸化膜、３は耐酸化性被膜たとえば窒化ケイ素膜
（５１５Ｎ４膜）である。４に分離領婢となる所を選択
的に開口しそこからシリコン基板をエツチングした開口
部である。One embodiment thereof is shown in FIG. 1st
In Figure a, 1 is, for example, a p-type 111 silicon substrate,
2 is a thermal oxide film, and 3 is an oxidation-resistant film such as a silicon nitride film (515N4 film). 4 is an opening formed by selectively opening a portion that will become a separation region and etching the silicon substrate from there.
このエツチングの方法は異方性の強いドライエヮチング
法たとえば反応性イオンエツチング（ＲＩＥ）を用いて
行ない、垂直にｐ型シリコン基板１を所定量工・フチン
グしている。その後、開口部の表面に熱酸化膜５を形成
して、それから全面［Ｓｉ３Ｎ４膜６を形成している（
第１図ｂ）。This etching method is carried out using a highly anisotropic dry etching method such as reactive ion etching (RIE), and the p-type silicon substrate 1 is vertically etched and edged by a predetermined amount. After that, a thermal oxide film 5 is formed on the surface of the opening, and then a Si3N4 film 6 is formed on the entire surface (
Figure 1 b).
第１図Ｃにおいてに、異方性の強いドライエツチング法
でＳｉ３Ｎ４膜３上に形成されたＳｉ３Ｎ４膜６及び開
口部４の底面に形成された熱酸化膜６、Ｓｉ３Ｎ４膜６
をエツチングして、開口部４の側面ＩＣのみ熱酸化膜５
．３５Ｎ４膜６を自己整合的に残している。その後、等
方的ｌ工、、チング法たとえばウェットエツチングを用
いてｐ型シリコン基板１をエツチングして横方向に開口
部７を形成する（第１図ｄ）。In FIG. 1C, a Si3N4 film 6 formed on the Si3N4 film 3 by a highly anisotropic dry etching method, a thermal oxide film 6 formed on the bottom surface of the opening 4, and a Si3N4 film 6 are shown.
The thermal oxide film 5 is etched only on the side IC of the opening 4.
．． The 35N4 film 6 is left in a self-aligned manner. Thereafter, the p-type silicon substrate 1 is etched using an isotropic etching method, such as wet etching, to form openings 7 in the lateral direction (FIG. 1d).
第１図ｅにおいてに、ｐ型シリコン基板１を選択酸化し
て熱酸化膜８．ぎを形成している。この熱酸化膜８．８
′σ島領域（図中ａで示す部分）が狭いと完全にくっつ
いて、島領域９の底面を完全に覆うことになる。その後
、開口部４を絶縁物たとえばＣＶＤで形成された５ｉ０
２膜１ｏで充てんすることにより島領域９は完全に絶縁
物８．ぎ。In FIG. 1e, p-type silicon substrate 1 is selectively oxidized to form a thermal oxide film 8. It forms a ridge. This thermal oxide film8.8
If the 'σ island region (the part indicated by a in the figure) is narrow, it will completely stick together and completely cover the bottom surface of the island region 9. Thereafter, the opening 4 is filled with an insulating material such as 5i0 formed by CVD.
The island region 9 is completely filled with the insulator 8.2 film 1o. Gi.
１ｏで覆われる（第１図ｆ）。1o (Fig. 1f).
このように本発明者らが提案した方法を用いると島領域
に側面及び底面両方とも絶縁物で囲まれ、完全に絶縁分
離することができる。しかしながら、この方法にも欠点
かめる。それに第１図６において、熱酸化膜８，８′を
形成する際、体積膨張により、５ｉ５Ｎ４膜６が上方向
に持ち上げられ、酸化膜８．８′が上方向にも形成され
てしまうことである（図中１１で示す部分ン。この上方
向に形成された酸化膜げ島領域９の深さに不均一性を生
じさせ特に島領域９の端部において浅くなり、この島領
域に形成されるデバイスの特性たとえば耐圧等を劣化さ
せる原因となってしまう。In this manner, when the method proposed by the present inventors is used, both the side and bottom surfaces of the island region are surrounded by an insulating material, and complete insulation isolation can be achieved. However, this method also has drawbacks. In addition, in FIG. 1, when forming the thermal oxide films 8, 8', the 5i5N4 film 6 is lifted upward due to volumetric expansion, and the oxide film 8.8' is also formed upward. (The part indicated by 11 in the figure) causes non-uniformity in the depth of the oxidized film island region 9 formed in the upward direction, and becomes shallower especially at the end of the island region 9. This may cause deterioration of the characteristics of the device, such as withstand voltage.
発明の目的
本発明にこのような問題に鑑み、第１図の方法によって
生じた上方向への酸化を防ぎ、島領域の深さの不均一性
特に島領域端部での不均一性を少なくする半導体装置の
製造方法を提供するものである。Purpose of the Invention In view of these problems, the present invention aims to prevent the upward oxidation caused by the method shown in FIG. The present invention provides a method for manufacturing a semiconductor device.
発明の構成
本発明はシリコン基板を側口部上部より開口部下部が広
い逆テーパ状に開口した開口部の側面及び底面の一部に
熱酸化膜、５ｉ５Ｎ４膜を残した後、シリコン基板を等
方的にエツチング、熱酸化することにより、Ｅ３１５Ｎ
４膜の上方向への持ち上がりを防ぎ、均一な深さの島領
域を形成して、島領域の側面及び底面もすべて酸化膜で
覆うことを可能とするものである。Structure of the Invention The present invention involves leaving a thermal oxide film, a 5i5N4 film, on a part of the side and bottom surfaces of a reverse tapered opening where the lower part of the opening is wider than the upper part of the side opening, and then the silicon substrate is removed. By directional etching and thermal oxidation, E315N
This prevents the four films from lifting upward, forms island regions of uniform depth, and makes it possible to cover all the side and bottom surfaces of the island regions with an oxide film.
実施倒の説明
第２図ａ −、、ｆとともに本発明の一実施例にかかる
製造方法を示す。第２図乙において、２Ｉｉｐ型１１１
シリコン基板、２２σ熱酸化膜、２３に酸素を通過しな
い３５Ｎ４膜であり、２４に分離領域となる所の５ｉ５
Ｎ４２３．熱酸化膜２２をエツチングした後、シリコン
基板２１を側口部上部より開口部下部が広い逆テーパ状
に工・フチングして開口した開口部でるる。この逆テー
パ状の開口部汀反応性イオンエツチングでガスの種類、
真空度を変えることにより形成することができる。DESCRIPTION OF EMBODIMENTS FIG. 2 shows a manufacturing method according to an embodiment of the present invention together with FIGS. In Figure 2 O, 2Iip type 111
Silicon substrate, 22σ thermal oxide film, 23 is a 35N4 film that does not pass oxygen, and 24 is a 5i5 film that will become an isolation region.
N423. After etching the thermal oxide film 22, the silicon substrate 21 is machined and edged into a reverse tapered shape where the lower part of the opening is wider than the upper part of the side opening to form an opening. This reverse tapered opening allows for reactive ion etching to determine the type of gas.
It can be formed by changing the degree of vacuum.
その後、開口部の表面に熱酸化膜２５を６００人形成し
、全面に、５ｉ３Ｎ＝２６を１２００人形成する（第２
図ｂ）。第３図Ｃにおいては、異方性の強いドライエツ
チング法で５ｉ３Ｎ４１１１Ｅ２３上に形成されたＳλ
ＳＮ４膜２６及びシリコン基板の開口部の底面に形成さ
れた１３５Ｎ４膜２６．熱酸化膜２５をエツチングする
。このときのドライエツチングに異方性の強いドライエ
ツチング法で行っているので、シリコン基板の逆−テー
パ状の開口部２４の側面及びＳｉ３Ｎ４膜２３のパター
ンよりも内側に形成されている底面上のｓｉ ３Ｎ ４
膜２６（図中２７で示す部分）に自己整合的に残ること
になる。この開口部２４の底面の所定領域にも５ｉＳＮ
４膜２６を残しておくことが本発明の特徴である。After that, 600 layers of thermal oxide film 25 are formed on the surface of the opening, and 1200 layers of 5i3N=26 are formed on the entire surface (second
Figure b). In FIG. 3C, the Sλ
The SN4 film 26 and the 135N4 film 26 formed on the bottom surface of the opening in the silicon substrate. The thermal oxide film 25 is etched. Since this dry etching is performed using a highly anisotropic dry etching method, etching is performed on the side surfaces of the reverse-tapered opening 24 of the silicon substrate and the bottom surface formed inside the pattern of the Si3N4 film 23. si 3N 4
It remains in the film 26 (portion indicated by 27 in the figure) in a self-aligned manner. 5iSN is also applied to a predetermined area on the bottom of this opening 24.
A feature of the present invention is that four films 26 are left.
その後、等方的なエツチングたとえばウェットエツチン
グでシリコン基板２１を横方向に。、５〜１．５μｍエ
ツチングして開口部２８を形成する（第２図ｄ）。第２
図ｅにおいては、選択酸化により酸化膜２９と２９′が
くっつくよう（（シて、島領域３０を形成する。Thereafter, the silicon substrate 21 is laterally etched by isotropic etching, for example, wet etching. , 5 to 1.5 μm to form an opening 28 (FIG. 2d). Second
In FIG. e, the oxide films 29 and 29' are brought together by selective oxidation to form an island region 30.
このとき、本発明の特徴である逆テーパ状に開口した開
口部の底面の所定領域２７にもＳｉ３Ｎ４膜２６が形成
されているので、酸化膜形成時に酸化にほとんど横方向
に進み、体積膨張によるＳ ｉ ５Ｎ４膜２６の上方向
への持ち上がりにほとんどなく、島領域３ｏの端部にお
いて酸化膜２９ 、２．９’［上方向へはほとんど形成
されない。それ故、島領域３ｏが端部で浅くなることａ
′ｆｘく、島領域３０の深さの均一性げ大幅に改善され
ることになる。At this time, since the Si3N4 film 26 is also formed in the predetermined region 27 on the bottom surface of the inversely tapered opening, which is a feature of the present invention, when the oxide film is formed, the oxidation progresses mostly in the horizontal direction, resulting in volume expansion. There is almost no upward lifting of the Si5N4 film 26, and the oxide films 29, 2.9' are hardly formed upward at the ends of the island region 3o. Therefore, the island region 3o becomes shallower at the end a
As a result, the uniformity of the depth of the island region 30 is greatly improved.
また、シリコン基板を逆テーパ状に開口しているため、
選択酸化により酸化膜２９と２９′をくっつけて島領域
３０を形成するのに要する時間が短くでき、プロセスを
簡単にするとともに結晶欠陥の発生を少くすることもで
きる。In addition, since the silicon substrate has an inverted tapered opening,
By selective oxidation, the time required to bond the oxide films 29 and 29' together to form the island region 30 can be shortened, simplifying the process, and reducing the occurrence of crystal defects.
その後、埋込法によって開口部２４にＣｖＤＳｉＯ２膜
３１を充てんする（第２図ｆ）。これで、島領域３０に
側面及び底面もすべて酸化膜で覆われ、完全に絶縁物で
分離され、島領域の深さも端部で浅くなるということも
なくなる。Thereafter, the opening 24 is filled with a CvDSiO2 film 31 by a filling method (FIG. 2f). As a result, the side and bottom surfaces of the island region 30 are all covered with the oxide film, completely isolated by the insulator, and the depth of the island region does not become shallow at the ends.
この島領域にバイポーラＴｒあるい［ＭＯ５Ｔｒを形成
すればデバイスが完成する。A device is completed by forming a bipolar transistor or [MO5Tr] in this island region.
ナオ、開口部２４ｖＣＯｖＤ Ｓｉｎ、、Ｃｚを充て
んする前にＳｉ ３Ｎ 、膜２３．２６を除去してから
ＣＶＤ５ｉ０２を充てんしても別に構わなＶ−１，。Nao, before filling the opening 24vCOvD Sin,, V-1, it is okay to remove Si 3N and the film 23.26 and then fill with CVD5i02.
以上述べてきたように本発明＋ｒＪシリコン基板を逆テ
ーパ状を開口し、この開口部の側面及び底面の所定領域
にＳｉ３Ｎ４膜を残してから、シリコン基板を等方向に
エツチング、酸化する際、逆テーパ状の開口部の側面及
び底面の所定領域に５ｉ５Ｎ。As described above, the present invention+rJ silicon substrate is opened in a reverse tapered shape, and after leaving a Si3N4 film on a predetermined area on the side and bottom surfaces of this opening, the silicon substrate is etched and oxidized in the same direction. 5i5N in specified areas on the side and bottom surfaces of the tapered opening.
膜が形成されているため、酸化にほとんど横方向に進み
、体積膨張によるＳｉ３Ｎ４膜の上方向への持ち上がり
にほとんどなく、酸化膜も上方向へはほとんど形成され
ない。それ故、島領域の端部において深場が浅くなるこ
ともなく、この島領域に形成されるデバイスの特性等が
劣化することもない０
発明の効果
以上のように１本発明げ島領域の側面及び底面も絶縁物
で酸化することにより、デバイスの寄生容量を極力小さ
くすることができ、島領域の端部で深さが浅くなること
もすく、デバイスの特性等を安定させることかできるの
で、高密度・高速化を図った半導体装置の製造方法に大
きく寄与し、また工業的にも非常に価値の高いものであ
る。Since the film is formed, oxidation proceeds mostly in the horizontal direction, and there is almost no upward lifting of the Si3N4 film due to volume expansion, and the oxide film is hardly formed upward. Therefore, the deep field does not become shallow at the end of the island region, and the characteristics of devices formed in this island region do not deteriorate. By oxidizing the side and bottom surfaces with an insulator, the parasitic capacitance of the device can be minimized, and the depth at the end of the island region is less likely to become shallow, making it possible to stabilize the characteristics of the device. It has greatly contributed to the manufacturing method of semiconductor devices with high density and high speed, and is also of great industrial value.
第１図ａ−ｆげ本発明者らが別に提案した分離方法を用
いた半導体装置の要部製造工程断面図、第２図ａ Ｎｆ
げ本発明の一実施例にかかる半導体装置の要部製造工程
断面図である。
２１・・・・・・シリコン基板、２４・・・・・・シリ
コン基板を逆テーパ状にエツチングした開口部、２６・
・・・・・５ｉｓＮｎ膜、２８・・・・・シリコン基板
を等方向にエツチングした開口部、２９．２９’・・・
・・・酸化膜、３０・・・・・・島領域。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第１図
８・ ａ
第２図
第２図
２９′Figures 1a-f are cross-sectional views of the manufacturing process of the main parts of a semiconductor device using a separation method separately proposed by the present inventors; Figure 2a-f
FIG. 2 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention. 21...Silicon substrate, 24...Opening portion etched into the silicon substrate in a reverse tapered shape, 26.
...5isNn film, 28... Openings etched in the same direction on the silicon substrate, 29.29'...
...Oxide film, 30...Island region. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 8・a Figure 2 Figure 2 29'
Claims (2)
マスクとして前記半導体基体に第１の側口部上部より開
口部下部が広い逆テーパ状の開口部を形成する工程と、
第２の耐酸化性被膜を前記半導体基体上に形成する工程
と、異方性エッチングにより前記第１の開口部側面及び
前記第１の耐酸化性被膜より内側の前記第１の開口部底
面に前記第２の耐酸化性被膜を残存させる工程と、前記
第１の開口部底部から前記半導体基体をエッチングし第
２の開口部を形成する工程と、前記第１、第２の耐酸化
性被膜をマスクとして酸化性雰囲気で前記半導体基体を
熱処理して、前記第２の開口部に酸化膜を形成する工程
とを含むことを特徴とする半導体装置の製造方法。(1) using a first oxidation-resistant film formed on the semiconductor substrate as a mask to form an inversely tapered opening in the semiconductor substrate, the bottom of which is wider than the top of the first side opening;
forming a second oxidation-resistant film on the semiconductor substrate; and anisotropic etching to form a second oxidation-resistant film on the side surface of the first opening and the bottom face of the first opening inside the first oxidation-resistant film. a step of leaving the second oxidation-resistant coating; a step of etching the semiconductor substrate from the bottom of the first opening to form a second opening; and the first and second oxidation-resistant coatings. a step of heat-treating the semiconductor substrate in an oxidizing atmosphere using a mask as a mask to form an oxide film in the second opening.
た第２の開口部と酸化物を介して接続されることを特徴
とする特許請求の範囲第１項記載の半導体装置の製造方
法。(2) The semiconductor device according to claim 1, wherein the second opening filled with an oxide is connected to an adjacent second opening via the oxide. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15434584A JPS6132540A (en) | 1984-07-25 | 1984-07-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15434584A JPS6132540A (en) | 1984-07-25 | 1984-07-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6132540A true JPS6132540A (en) | 1986-02-15 |
Family
ID=15582124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15434584A Pending JPS6132540A (en) | 1984-07-25 | 1984-07-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6132540A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4965221A (en) * | 1989-03-15 | 1990-10-23 | Micron Technology, Inc. | Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions |
| US5416041A (en) * | 1993-09-27 | 1995-05-16 | Siemens Aktiengesellschaft | Method for producing an insulating trench in an SOI substrate |
-
1984
- 1984-07-25 JP JP15434584A patent/JPS6132540A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4965221A (en) * | 1989-03-15 | 1990-10-23 | Micron Technology, Inc. | Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions |
| US5416041A (en) * | 1993-09-27 | 1995-05-16 | Siemens Aktiengesellschaft | Method for producing an insulating trench in an SOI substrate |
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