JPS6131578B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a relay sequence control circuit.

For example, when sequentially turning on power to devices connected in series, a power-on completion signal may not be returned even though a turn-on signal has been sent to the devices. In order to monitor this time, in conventional relay control circuits, the timer is reset by the contact of the relay that operates in response to the control completion signal from the controlled device, and then another relay is driven, and the contact of that relay is used to reset the timer. A method is used in which a timer is set at the same time as the control signal is sent to the controller. Therefore, at least two or more relays are required for one device. In addition, in another conventional method, the expected control completion time per stage is determined, a time corresponding to the number of controlled devices is set in a timer, and the last device to be sequentially controlled within the set time is set. This is to detect whether or not a control completion signal has been received from the controller. Therefore, it is necessary to change the time set in the timer depending on the number of controlled devices connected.

An object of the present invention is to be able to perform sequence control and timer reset and setting using one relay for one device, and to change the time set in the timer depending on the number of controlled devices connected. The object of the present invention is to provide an unnecessary relay sequence control circuit.

The circuit of the present invention is a sequential relay circuit consisting of a plurality of stages connected in series, and includes a relay in each stage that starts driving in response to a control completion signal, and a relay in the previous stage that starts operating each part of the stage. a drive piece that operates when the relays in each stage are driven; and a transfer contact that operates when the relays in each stage are driven; and while the relay in the stage is being driven, the transfer contact is charged and in contact with any contact while it is not in contact with any contact. A time constant circuit that is discharged, and a comparator that sends out a signal when the voltage of the time constant circuit is lower than a reference voltage. It is characterized by monitoring the time until the start of operation.

The present invention is based on the principle that an open state of about 200 μs (microseconds) always exists between when a relay operates and its transfer contact leaves the break contact and contacts the make contact.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, one embodiment of the present invention has an input terminal
Relay Ai( i = 0, 1, 2, ..., n), a grounded terminal 200, a terminal to which a predetermined positive voltage V _B is applied
201, and the contacts ai ₁ , ai ₂ (i=0,
1, 2,..., n), and the contact ai ₂ (i
=0, 1, 2,..., n-1) is the next stage controlled device i
+1 (i=0, 1,..., n-1) relay Bi+ ₁
(i=0, 1, 2,..., n-1), and one contact ai ₁ (i=0, 1,...,
n) are alternately connected in series so that the input _V1 to the timer becomes open during its operation.

The operation in FIG. 1 will be explained below with reference to FIG. 2.

First, when input terminals 50 are short-circuited by a sequential control start signal, relay A ₀ is driven and contacts a ₀₁ and a ₀₂ are operated (time t ₀ ). When contact a ₀₁ is made, point V ₁ is grounded through contacts a ₀₁ and a ₁₁ , diode 2 is reverse biased, and point V ₂ begins to fall with a time constant of the product of capacitor 3 and resistor 4.
A timer is set. On the other hand, when contact a ₀₂ is made, a control signal is sent to device 1, and relay B ₁ of device 1 is driven. When the operation is completed in device 1, contact C ₁ is made to send out a completion signal and relay A ₁ is driven (time t ₁ ). If the time from when contact a ₀₂ closes to when contact C ₁ closes is shorter than the preset time T, contact a ₁₁ will break and V ₁ will break before the V ₂ point falls below the V ₃ point.
Since the points are open, _{the two} V points are connected to capacitors 3 of 2.2μF (micro/farad) and 20V each.
The time constant (22 μs) of the product of Ω and the parallel connection of resistors 1 and 4 of 470 kΩ charges quickly and resets the timer. Next, contacts a ₁₁ and a ₁₂ are made simultaneously and send a control signal to device 2, and at the same time
Since the _V1 point is grounded through contacts _a21 and _a11 , a timer is set (time _t2 ).

Thereafter, control signals are sent to devices 3, . . . , n and timers are reset and set in the same manner. If the control signal is sent and the completion signal is not returned even after the preset time T has elapsed, the timer is not reset and the _V2 point becomes _V3.
, and sends a time-up signal to the output terminal 60 (time t ₃ ).

Also, in order to guarantee sufficient timer reset time (i.e. charging time for capacitor 3),
The circuit shown in the figure may be inserted between terminals 6 and 7 of FIG. Now, the open time of the contact (i.e. the time during which high level voltage V _H is applied to terminal 6) is τ
₁ , the time during which high level voltage is obtained at terminal 7 is τ ₂
shall be. One-shot multivibrator (One
shot) becomes the ground potential V _L (a potential lower than the high level potential V _H ) for a predetermined period of time τ ₂ from the fall of the input signal applied to the input terminal, and remains at a high level for the rest of the time. Outputs a signal that becomes a potential. The potential of terminal 6, the potential of the output of the one-shot multivibrator, the potential of the output of the first NAND gate connected to terminal 6 and the output terminal of the one-shot multivibrator, and the output terminal of the multivibrator and the first
A second terminal connected to the output terminal of the NAND gate
The potential of the output of the NAND gate is υ ₁ and υ
₂ , υ ₃ , and υ ₄ , consider the case of τ ₁ <τ ₂ . From time t ₀ (time when the contact becomes open) to time (t ₀ +τ ₁ ), υ ₁ = V _H and υ ₂ = V _L , so υ ₃ = V _H , and as a result, υ ₄ = It becomes _VH . From time (t ₀ +τ ₂ ) to time (t ₀ +r ₂ ), υ ₁ =V _L and υ ₂ =V _L , so υ ₃ =V _H , and as a result, υ ₄ =V _H. After time (t ₀ + τ ₂ ), υ ₁ = V _L and υ ₂ = V _H , so υ ₃ = V _H , and υ ₄ =
It becomes _VL . In other words, the potential at terminal 7 changes over time τ ₂
Only _VH becomes. Also, considering the case of τ ₁ > τ ₂ , from time t ₀ to time (t ₀ + τ ₂ ), υ ₁ = υ _H
Since υ ₂ =V _L , υ ₃ =V _H , and as a result, υ ₄ =V _H. Time (t ₀ + τ ₂ ) ~
At time (t ₀ +τ ₁ ), υ ₁ =V _H and υ ₂ =
Since V _H , υ ₃ = V _L , and as a result, υ ₄
= _VH . After time (t ₀ + τ ₁ A), υ ₁
=V _L and υ ₂ =V _H , so υ ₃ =V _H , and as a result, υ ₄ =V _L. That is, the potential of the terminal 7 becomes V _H for a time τ ₁ , which also guarantees that the timer will not start while the contact is open.

The present invention has the advantage that sequence control and timer reset and setting can be performed simultaneously and easily using one relay for one device.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a typical voltage waveform at each terminal in Fig. 1,
FIG. 3 is a circuit diagram showing an embodiment for improving the present invention. ai ₁ , ai ₂ (i = 0, 1, 2, ..., n) ... transfer contact of relay Ai (i = 0, 1, 2, ..., n), Bi (i = 1, 2, ..., n)...Device i
Control signal receiving relays at (i=1, 2,...,n), Ci(i=1, 2,...,n) devices, i(i
=1, 2,..., n), control completion signal sending contact, 1, 4...resistance, 2...diode, 3...
Capacitor, 5...Comparator, 50...Sequence control instruction signal input terminal, 60...Time-up signal output terminal, 100, 101, 200, 201...
...DC power supply, 11...Input waveform to timer, 12
...Reference voltage and input waveform of comparator 5, 1
3...Timer output waveform.

Claims (1)

[Claims] 1. Relays Ak in which n stages are cascade-connected and each starts driving in response to a control completion signal Ck (k=0 to n).
and n first drive pieces a that start the operation of each part of the stage in order to generate the control completion signal C _l+1 by driving the relay Al (l=0 to n-1) in the previous stage. _l , ₂ , a plurality of second drive pieces a i , 1 driven by the i-th (i is 0 or an even number equal to or less than n) stage relay A _i , and the (i+ ₁ )-th stage relay A _i A plurality of second drive pieces a _i+1 , ₁ driven by +1 and a first connection point to which the stationary contacts of the second drive pieces _{a i} , ₁ are all connected in common; Drive piece a
and a second connection point to which all the stationary contacts of _i+1 , ₁ are connected in common, and the second driving piece a _i ' ₁
a contact circuit in which the make contact of the second drive piece a _i+1 , ₁ is connected and the make contact of the second drive piece a _i , ₁ is connected; and the relay of the kth stage. While driving Ak, the second
A time constant circuit in which the stationary contact of the driving piece a _k , ₁ is charged when it is not in contact with the make contact and the break contact and discharged while it is in contact with the make contact, and the voltage of this time constant circuit is the reference voltage. and a comparator that sends out a signal when the following conditions are met, and monitors the time from when the first drive piece driven by the relay in the preceding stage starts operating to when the relay in the stage starts operating. Features a relay sequence control circuit.