SU1450084A1 - Pulser - Google Patents

Abstract

The invention can be used to form time intervals in automation equipment, teleautomatics, computational and impulse engineering using an element base that provides a logic zero level close to zero potential, for example, using CMOS series microcircuits. The purpose of the invention is to increase the accuracy due to the fact that in the pulse generator after the signal arrives on the control code bus, the selected key is closed, the time of the driver circuit 2 is connected between points with zero potential — between elements whose output is set to a logical zero, and the time of the master resistor 4 is discharged almost to zero. Such a mode can be maintained for an arbitrarily long time, which does not reflect on the accuracy of the characteristics of the generator. The drawing also shows a voltage comparator 1, time specifying capacitors 3-1 ... 3-N, resistive voltage divider 5 on resistors 6 and 7, trigger 8, logical element OR 9, controllable key Yu, logical element OR- NOT 11, bus 12 control, code bus 13 and demultiplexer 14. 2 Il. g with (L 4 SP

Description

 The device belongs to the field of: impulse technology and can be used to form time intervals in automation equipment, telemechanics and computing equipment using an element base that provides a level of logical zero 5 close to zero potential, for example, using micro-I CMOS circuits,

I The purpose of the invention is to increase the accuracy of the device.

I The goal is achieved due to the fact that after the signal arrives at the code I control and the selected key is closed, the time setting circuit is switched on j between points with zero potentials — between the elements - I toric is set to a logical zero, I and the time setting the capacitor discharged I almost to zero. Such a situation can persist for an arbitrarily long time, which does not reflect on the accuracy characteristics of the device. ; Fig, 1 shows fukkt-; generator circuit diagram; on f: g. 2: stress diagrams for the following e: - o work:

i The pulse generator contains a comparator I voltage 1, the inputs of which are connected respectively to the outputs of the time of the driving circuit 2, consisting of the time of the driving capacitors 3-1 + 3-, one terminals of which are combined and connected to one of the outputs of the time of the master resistor 4 and resistive voltage divider 5, consisting of resistors 6 and 7, trigger 8, the direct output of which is connected to another output of resistor 4 of the time of the driving circuit 2, one of the inputs of the logic element OR 9, and information and control inputs of control key is 10 output which It is connected to the inverse output of the trigger 8 through the voltage divider 5 mentioned above. Compressor 1 voltage output is connected to another input of logical element OR 9, reset input of trigger 8 and one of the inputs of logic element 11 OR-H, the other input of which is connected to control bus 12 and output to trigger input B. Kodova bus 1 control is connected to the control inputs of the multiplexer-demultiplex 14, the information input of the demultiplexer which is connected to the output

0

five

Comparator 1 is the home of voltages, and the information outputs are with other terminals of capacitors 3, the time of the driving circuit 2. For example, a 564KP1 chip can be used as a multiplexer-de-multiplex pexor 14. The device works as follows.

When operating in the standby mode, in the initial state on bus 12 of the control 1, logical 1 is set, on the direct and inverse trigger 8 outputs logical O (U p) and 1 (ujug), respectively, at outputs of comparator 1 and ISH1 9 logical О (U ° and U °), Key 10 is open and the inverting input of comparator 1 is set to Uf ,,.

Suppose that control bus 13 is set to logical O. Then the channel X-X of the multiplexer 14 is zagged and the capacitor 3-1 is connected to the output of comparator 1.

Since the forward output of the trigger and the output of comparator 1 are set to logical 0%, the initial ng voltage on the capacitor 3. -1 is O

When a pulse (logical O) is received, the control bus 12 is triggered to the state S, at which logical 1 (U i-, p) & on the inverse z-code - logical O (and ° iib).

On the manager; The key input 10 from the direct output of the trigger 8 comes: logical 1, it staggers, and the inverting input to the terminal I of the device i sets the voltage

and m (U pr - and UKB) 1 ° IU,

where m (R, + y.) f

resistances of resistors 6 and 7 of the voltage divider 5,

The timing of driver circuit 2 (4.3 - 1) is turned on under the voltage E 3.1 and f, p - and ° C and the capacitor 3-1 begins to charge.

The charge of the capacitor 3-1 ends when the voltage at the non-inverting input of the comparator 1 reaches the value and „o, and at the capacitor 3-1 it is the value and with (, 1 and pg U i

Comparator 1 switches and logical 1O 1 sets its trigger 8 to its initial state from its output.

R, R

3145

The magnitude of the time interval formed from the moment the device starts up and until the trigger 8 switches to the initial state (a pulse is generated at the output of the trigger 8) is determined from the expression

t, R, Cj., ln C (Ej, r 0) / (E, „- Ueo,) J.

It is assumed that U lr%, and pr and IN6 and 1s

we get t R4Cj., ln 1 / (1-m). Since the logical output of the trigger 8 is set to logical 8,

When the binary code changes to

the key 10 is opened and on the inverting bus 13 of the control is connected to the other input of the comparator 1 a voltage U is set.

The time setting circuit 2 (4.3-1) is turned on under the voltage

E ,,. and, - and

opposite to the initial voltage Ucc 1 on the capacitor 3-1, and the latter starts to recharge.

In this case, a positive voltage jump U E 311 + +, + U (((p, confirming the unit state of comparator 1) occurs at the non-inverting input of comparator 1.

Resampling of the capacitor 3-1 ends when the voltage on the non-inlet., Q the rotating input of the comparator 1 reaches the value UHI, and on the capacitor 3-1 - the value Ucoi ep m + + U pr ".0. In this case, the comparator 1 switches, a logical O is set at its output, and the device returns to its initial state.

The magnitude of the time interval formed from the moment the trigger 8 is set to the initial state and until the device returns to the initial state (a pulse is formed at the output of the comparator 1) determines the correct output capacitor and the value of the time interval being formed varies.

In order to ensure the alignment of the level, which by the sign of the voltage across it and the voltage U, in the case of using the element base, in particular the comparator 1, which has a logic zero level that differs from the logic zero level at the output 25 of the trigger 8, Energy solutions, for example, the inclusion of the converter of the corresponding chip series at the output of the comparator 1.

Claims (1)

The formula of the invention. ki A pulse generator containing a voltage comparator, the inputs of which are respectively connected to the outputs of the time of the driving circuit, consisting of N time of the driving capacitors, one terminals of which are combined and connected to one of the terminals of the time of the driving resistor, and a resistive voltage divider, trigger, direct the input of which is connected to another output of the resistor of the master circuit time, one of the inputs of the logical element OR, and 35 A pulse generator containing a voltage comparator, the inputs of which are respectively connected to the outputs of the time of the driving circuit, consisting of N time of the driving capacitors, one terminals of which are combined and connected to one of the terminals of the time of the driving resistor, and a resistive voltage divider, trigger, direct the input of which is connected to another output of the resistor of the master circuit time, one of the inputs of the logical element OR, and c out of expression t KtsSzn1n (E 3, xf UC.,) / (E, .- and, „,) 45 information and control inputs  controlled key whose output is or t, 2 К4Сз.Дп (1 + т). connected to the inverse output of the trigger. Then the duration of the pulse at the output 15 of the element 9 is determined from the discharge 50 Pa through the mentioned resistive voltage divider, the output of the voltage comparator is connected to another input of the OR logic element, the trigger reset input and one of the inputs of the OR-NOT logic element, the other input of which is connected to the control bus, and the output to the trigger installation input, control code bus, characterized in that, with the aim of increasing the accuracy of the generator, it introduces a multi-plug-demulti-TOO t, + ti R4C,., ln. (1 + ia) / (1-in) 3. When operating in a self-oscillating mode, a logical O is applied to the control bus 12 and the operation of the device is similar to that in the standby mode. The difference is that when the device returns to its initial state at the output of the element OR NOT 11 is set to logical 1 and a restart occurs. devices. At the same time, each subsequent period of the pulse begins to form at zero initial voltage on the co-sensor 3. When the device is in standby mode, the time interval also starts and ends at zero initial voltage across the capacitor 3. When the binary code changes to control bus 13 is connected to another type of publishing capacitor and the value of the time interval being formed is changed. To ensure leveling The formula of the invention. ki A pulse generator containing a voltage comparator, the inputs of which are respectively connected to the outputs of the time of the driving circuit, consisting of N time of the driving capacitors, one terminals of which are combined and connected to one of the terminals of the time of the driving resistor, and a resistive voltage divider, trigger, direct the input of which is connected to another output of the resistor of the master circuit time, one of the inputs of the logical element OR, and Pa through the mentioned resistive voltage divider, the output of the voltage comparator is connected to another input of the OR logic element, the trigger reset input and one of the inputs of the OR-NOT logic element, the other input of which is connected to the control bus, and the output to the trigger installation input, control code bus, characterized in that, with the aim of increasing the accuracy of the generator, it introduced multi-plug-demulti-5150084 6 plexor, information input of the control code bus, and. -informational output terminals are connected to the output — with other output voltages; control inputs — from the time of the master circuit; world log in / - 7. Nein8irl / inh.kong1, R I -1F1 .eg